Abstract: Server resources in a data center are disaggregated into shared server resource pools, which include a pool of secure processors. Advantageously, servers are constructed dynamically, on-demand and based on a tenant's workload requirements, by allocating from these resource pools. According to this disclosure, secure processor modules for new servers are allocated to provide security for data-in-use (and data-at-rest) in a dynamic fashion so that virtual and non-virtual capacity can be adjusted in the disaggregate compute system without any downtime, e.g., based on workload security requirements and data sensitivity characteristics. The approach herein optimizes an overall utilization of an available secure processors resource pool in the disaggregated environment. The resulting disaggregate compute system that is configured according to the approach cryptographically-protects workload data whenever it is outside the CPU chip.

Abstract: Code generation relating to providing table of contents (TOC) pointer values. Code to be compiled is obtained by a processor. Based on obtaining the code, a determination is made as to whether the code is to access a reference data structure. Based on determining the code is to access the reference data structure, other code is included in the code to provide a pointer to the reference data structure. The other code includes an architectural definition to provide the pointer to the reference data structure.

Abstract: Embodiments for disaster recovery in a disaggregated computing system. A memory pool is allocated including allocated memory elements at a secondary, disaster recovery site for data received from memory pool elements within the memory pool at a primary site. Data is continuously replicated to the allocated memory elements at the disaster recovery site without requiring any compute resources to be attached to the allocated memory elements during the replicating. An orchestration mechanism is used to regulate an available amount of resources to be assigned to the allocated memory elements at the disaster recovery site during a failover operation for performing failover workloads associated with the replicated data upon the primary site becoming inoperable.

Abstract: Code-specific affiliated register prediction. A determination is made as to whether a unit of code is a candidate for affiliated register prediction. The determining employs a code specific indicator specific to the unit of code. Based on determining the unit of code is a candidate for affiliated register prediction, an indication of an affiliated register is loaded into a selected location. Based on the loading, the affiliated register is employed in speculative processing.

Abstract: Embodiments for optimizing dynamic resource allocations in a disaggregated computing environment. A data heat map associated with a data access pattern of data elements associated with a workload is maintained. The workload is classified into one of a plurality of classes, each class characterized by the data access pattern associated with the workload. The workload is then assigned to a dynamically constructed disaggregated system optimized with resources according to the one of the plurality of classes the workload is classified into to increase efficiency during a performance of the workload.

Abstract: A computer security protection may be provided by dynamic computer system certification. User usage of a computer system may be monitored. Based on the monitoring a role of the user in the usage of the computer system is determined. A certification required for the role and whether the user has the certification sufficient for the role are determined. Responsive to determining that the user does not have the certification sufficient for the role, a certification process is initiated.

Abstract: Detecting that a sequence of instructions creates an affiliated relationship. A determination is made that a sequence of instructions creates an affiliated relationship. Based on determining that the sequence of instructions creates the affiliated relationship, a sequence of operations is generated. The sequence of operations provides a predicted target address to be included in a selected register and to be used in branching.

Abstract: Prediction of an affiliated register. A determination is made as to whether an affiliated register is to be predicted for a particular branch instruction. The affiliated register is a register, separate from a target address register, selected to store a predicted target address based on prediction of a target address. Based on determining that the affiliated register is to be predicted, predictive processing is performed. The predictive processing includes providing the predicted target address in a location associated with the affiliated register.

Abstract: In a transactional memory environment including a first processor and one or more additional processors, a computer-implemented method includes identifying a memory location and sending a probe request from the first processor to the additional processors. The probe request includes the memory location. The computer implemented method further includes generating, by each additional processor, an indication including whether the memory location is in use for a transaction by the additional processor. The computer-implemented method further includes sending the indication from each additional processor to the first processor and proceeding, by the first processor, based on the indication.

Abstract: A Set Table of Contents (TOC) Register instruction. An instruction to provide a pointer to a reference data structure, such as a TOC, is obtained by a processor and executed. The executing includes determining a value for the pointer to the reference data structure, and storing the value in a location (e.g., a register) specified by the instruction.

Abstract: A Set Table of Contents (TOC) Register instruction. An instruction to provide a pointer to a reference data structure, such as a TOC, is obtained by a processor and executed. The executing includes determining a value for the pointer to the reference data structure, and storing the value in a location (e.g., a register) specified by the instruction.

Abstract: A fashion display method, system, and non-transitory computer readable medium, include a customer identification circuit configured to identify a fashion style of a customer viewing a fashion display, a customer assessing circuit configured to determine an assessed trait of the customer by assessing the fashion style of the customer, and a display augmenting circuit configured to augment the fashion display to display a new fashion display customized to the customer based on the assessed trait.

Abstract: For measuring component utilization in a computing system, a server energy utilization reading of a statistical significant number of servers out of a total number of servers located in the datacenter is obtained by measuring, at predetermined intervals, a collective energy consumed by all processing components within each server. The collective energy is measured by virtually probing thereby monitoring an energy consumption of individual ones of all the processing components to each collect an individual energy utilization reading, where the individual energy utilization reading is aggregated over a predetermined time period to collect an energy consumption pattern associated with the server utilization reading.

Abstract: A determination is made as to whether an instruction is an affiliation-creating instruction that provides an affiliation between a plurality of registers. Based on determining the instruction is an affiliation-creating instruction, an affiliation is specified. Further, a branch instruction is obtained. The branch instruction is separated from the instruction by one or more instructions. Based on the branch instruction and specifying the affiliation, processing is performed.

Abstract: Detecting that a sequence of instructions creates an affiliated relationship. A determination is made that a sequence of instructions creates an affiliated relationship. Based on determining that the sequence of instructions creates the affiliated relationship, a sequence of operations is generated. The sequence of operations provides a predicted target address to be included in a selected register and to be used in branching.

Abstract: A transaction within a computer program or computer application comprises program instructions performing multiple store operations that appear to run and complete as a single, atomic operation. The program instructions forming a current transaction comprise a transaction begin indicator, a plurality of instructions (e.g., store operations), and a transaction end indicator. A near-end of transaction indicator is triggered based on a speculative look ahead operation such that an interfering transaction requiring a halt operation may be delayed to allow the current transaction to end. A halt operation, also referred to as an abort operation, as used herein refers to an operation responsive to a condition where two transactions have been detected to interfere where at least one transaction must be aborted and the state of the processor is reset to the state at the beginning of the aborted transaction by performing a rollback.

Abstract: Facilitating processing in a computing environment. A request to access a cache of the computing environment is obtained from a transaction executing on a processor of the computing environment. Based on obtaining the request, a determination is made as to whether a tracking set to be used to track cache accesses is to be updated. The tracking set includes a read set to track read accesses of at least a selected portion of the cache and a write set to track write accesses of at least the selected portion of the cache. The tracking set is assigned to the transaction, and another transaction to access the cache has another tracking set assigned thereto. The tracking set assigned to the transaction is updated based on the determining indicating the tracking set is to be updated.

Abstract: A Set Table of Contents (TOC) Register instruction. An instruction to provide a pointer to a reference data structure, such as a TOC, is obtained by a processor and executed. The executing includes determining a value for the pointer to the reference data structure, and storing the value in a location (e.g., a register) specified by the instruction.

Abstract: For power management in a disaggregated computing system, initial electrical power levels are distributed thereby allocating a voltage and a clock speed to each one of a set of processor cores in the disaggregated computing system. The voltage and the clock speed of respective processor cores within the set of processor cores are adjusted according to a workload priority of respective workloads performed by each respective one of the processor cores, wherein the workload priority is assigned based upon a service level agreement (SLA).

Abstract: A load request to restore a plurality of architected registers is obtained. Based on obtaining the load request, one or more architected registers of the plurality of architected registers are restored. The restoring uses a snapshot that maps architected registers to physical registers to replace one or more physical registers currently assigned to the one or more architected registers with one or more physical registers of the snapshot corresponding to the one or more architected registers.