Abstract: A semiconductor having a n-doped cathode layer, a p-doped anode layer, and a drift region, arranged between the cathode layer and the anode layer, with a dopant concentration of at most 8·1015 cm?3. The drift region has a lightly n-doped drift layer and a lightly p-doped drift layer, arranged between the n-doped drift layer and the anode layer, both drift layers each have a layer thickness of at least 5 ?m. The cathode layer has a first section with a dopant concentration of at least 1·1017 cm?3 and a second section, arranged between the first section and the drift region, the second section has a layer thickness of at least 1 ?m and a dopant concentration gradient that increases in the direction of the first section up to a dopant concentration maximum. The dopant concentration maximum is smaller or equal to the dopant concentration of the first section.

Abstract: A stacked III-V semiconductor diode comprising or consisting of GaAs, with a heavily n-doped cathode layer, a heavily p-doped anode layer, and a drift region arranged between the cathode layer and the anode layer with a dopant concentration of at most 8·1015 cm?3, and a layer thickness of at least 10 ?m, wherein the cathode layer has a delta layer section with a layer thickness of 0.1 ?m to 2 ?m and a dopant concentration of at least 1·1019 cm?3.

Abstract: A stacked III-V semiconductor diode comprising or consisting of GaAs with a highly n-doped cathode layer, a highly p-doped anode layer and a drift region arranged between the cathode layer and the anode layer, wherein the drift region has a low n-doped drift layer and a low p-doped drift layer, the n-doped drift layer is arranged between the p-doped drift layer and the cathode layer, both drift layers each have a layer thickness of at least 5 ?m and, along the respective layer thickness, have a dopant concentration maximum of not more than 8·1015 cm?3, the dopant concentration maxima of the two drift layers have a ratio of 0.1 to 10 to each other and a ratio of the layer thickness of the n-doped drift layer to the layer thickness of the p-doped drift layer is between 0.5 and 3.

Abstract: A stacked, high-blocking III-V semiconductor power diode having a first metallic terminal contact layer, formed at least in regions, and a highly doped semiconductor contact region of a first conductivity type and a first lattice constant. A drift layer of a second conductivity type and having a first lattice constant is furthermore provided. A semiconductor contact layer of a second conductivity, which includes an upper side and an underside, and a second metallic terminal contact layer are formed, and the second metallic terminal contact layer being integrally connected to the underside of the semiconductor contact layer, and the semiconductor contact layer having a second lattice constant at least on the underside, and the second lattice constant being the lattice constant of InP, and the drift layer and the highly doped semiconductor contact region each comprising an InGaAs compound or being made up of InGaAs.

Abstract: A stacked III-V semiconductor diode comprising or consisting of GaAs with a highly n-doped cathode layer, a highly p-doped anode layer and a drift region arranged between the cathode layer and the anode layer, wherein the drift region has a low n-doped drift layer and a low p-doped drift layer, the n-doped drift layer is arranged between the p-doped drift layer and the cathode layer, both drift layers each have a layer thickness of at least 5 ?m and, along the respective layer thickness, have a dopant concentration maximum of not more than 8·1015 cm?3, the dopant concentration maxima of the two drift layers have a ratio of 0.1 to 10 to each other and a ratio of the layer thickness of the n-doped drift layer to the layer thickness of the p-doped drift layer is between 0.5 and 3.

Abstract: A stacked III-V semiconductor diode comprising or consisting of GaAs, with a heavily n-doped cathode layer, a heavily p-doped anode layer, and a drift region arranged between the cathode layer and the anode layer with a dopant concentration of at most 8·1015 cm?3, and a layer thickness of at least 10 ?m, wherein the cathode layer has a delta layer section with a layer thickness of 0.1 ?m to 2 ?m and a dopant concentration of at least 1·1019 cm?3.

Abstract: A semiconductor having a n-doped cathode layer, a p-doped anode layer, and a drift region, arranged between the cathode layer and the anode layer, with a dopant concentration of at most 8·1015 cm?3. The drift region has a lightly n-doped drift layer and a lightly p-doped drift layer, arranged between the n-doped drift layer and the anode layer, both drift layers each have a layer thickness of at least 5 ?m. The cathode layer has a first section with a dopant concentration of at least 1·1017 cm?3 and a second section, arranged between the first section and the drift region, the second section has a layer thickness of at least 1 ?m and a dopant concentration gradient that increases in the direction of the first section up to a dopant concentration maximum. The dopant concentration maximum is smaller or equal to the dopant concentration of the first section.

Abstract: A stacked, high-blocking III-V semiconductor power diode having a first metallic terminal contact layer, formed at least in regions, and a highly doped semiconductor contact region of a first conductivity type and a first lattice constant. A drift layer of a second conductivity type and having a first lattice constant is furthermore provided. A semiconductor contact layer of a second conductivity, which includes an upper side and an underside, and a second metallic terminal contact layer are formed, and the second metallic terminal contact layer being integrally connected to the underside of the semiconductor contact layer, and the semiconductor contact layer having a second lattice constant at least on the underside, and the second lattice constant being the lattice constant of InP, and the drift layer and the highly doped semiconductor contact region each comprising an InGaAs compound or being made up of InGaAs.

Abstract: A stacked high-blocking III-V power semiconductor diode, with a p+ or n+ substrate layer, a p? layer, an n? region with a layer thickness of 10 ?m-150 ?m, and an n+ or p+ layer, wherein all layers comprise a GaAs compound, a first metallic contact layer and a second metallic contact layer and a hard mask layer with at least one seed opening, wherein the hard mask layer is integrally bonded to the substrate layer or integrally bonded to the p? layer, the n? region extends within the seed opening and over an edge region, adjacent to the seed opening, of a top side of the hard mask layer and the n? region within the seed opening is integrally bonded to the p? layer or to the n+ substrate layer and in the edge region of the top side of the hard mask layer to the hard mask layer.

Abstract: A stacked, high-blocking III-V semiconductor power diode having a first metallic terminal contact layer, formed at least in regions, and a highly doped semiconductor contact region of a first conductivity type and a first lattice constant. A drift layer of a second conductivity type and having a first lattice constant is furthermore provided. A semiconductor contact layer of a second conductivity, which includes an upper side and an underside, and a second metallic terminal contact layer are formed, and the second metallic terminal contact layer being integrally connected to the underside of the semiconductor contact layer, and the semiconductor contact layer having a second lattice constant at least on the underside, and the second lattice constant being the lattice constant of InP, and the drift layer and the highly doped semiconductor contact region each comprising an InGaAs compound or being made up of InGaAs.

Abstract: IGBT semiconductor structure having a p+ substrate, an n? layer, at least one p region adjacent to the n? layer, and at least one n+ region adjacent to the p region, a dielectric layer and three terminal contacts. The p region forms a first p-n junction together with the n? layer, and the n+ region forms a second p-n junction together with the at least one p region. The dielectric layer covers the first p-n junction and the second p-n junction. The second terminal contact is implemented as a field plate on the dielectric layer and a doped intermediate layer with a layer thickness of 1 ?m-50 ?m and a dopant concentration of 1012-1017 cm?3 is arranged between the p+ substrate and the n? layer, wherein the intermediate layer is integrally joined to at least the p+ substrate.

Abstract: A stacked III-V semiconductor diode having an n? layer having a first surface, a second surface, a dopant concentration of 1012 N/cm3 to 1017 N/cm3 and a layer thickness of 50 ?m to 1,000 ?m, a p+ layer, which is integrally connected to the first surface and has a dopant concentration of 5·1018 N/cm3 to 5·1020 N/cm3, an n+ layer, which is integrally connected to the second surface and has a dopant concentration of at least 1019 N/cm3. The p+ layer, the n? layer and the n+ layer each having a monolithic design and each being made up of a GaAs compound. The dopant concentration of the n? layer having a first value on the first surface and a second value on the second surface, and the second value of the dopant concentration being greater than the first value at least by a factor between 1.5 and 2.5.

Abstract: A stacked III-V semiconductor component having a p+ region with a top side, a bottom side, and a dopant concentration of 5·1018-5·1020 N/cm3, a first n? layer with a top side and a bottom side, a dopant concentration of 1012-1017 N/cm3, and a layer thickness of 10-300 ?m, an n+ region with a top side, a bottom side, and a dopant concentration of at least 1018 N/cm3, wherein the p+ regions, the n? layer, and the n+ region follow one another in the stated order, are each formed monolithically, and each comprise a GaAs compound or consist of a GaAs compound, the n+ region or the p+ region is formed as the substrate layer, and the n? layer comprises chromium with a concentration of at least 1014 N/cm3 or at least 1015 N/cm3.

Abstract: A stacked, high-blocking III-V semiconductor power diode having a first metallic terminal contact layer, formed at least in regions, and a highly doped semiconductor contact region of a first conductivity type and a first lattice constant. A drift layer of a second conductivity type and having a first lattice constant is furthermore provided. A semiconductor contact layer of a second conductivity, which includes an upper side and an underside, and a second metallic terminal contact layer are formed, and the second metallic terminal contact layer being integrally connected to the underside of the semiconductor contact layer, and the semiconductor contact layer having a second lattice constant at least on the underside, and the second lattice constant being the lattice constant of InP, and the drift layer and the highly doped semiconductor contact region each comprising an InGaAs compound or being made up of InGaAs.

Abstract: A method and stacked semiconductor device having a top surface, a bottom surface, and at least one side surface that connects the top surface with the bottom surface. The bottom surface is formed of a substrate layer or a rear side contact layer arranged below the substrate layer. On the substrate layer, a first semiconductor layer of a first conductivity type is arranged and on the first semiconductor layer at least one second semiconductor layer of a second conductivity type is arranged. The first and second semiconductor layers are formed of a III-V material or consist of a III-V material. The first and second conductivity types are different. The top surface is at least partially formed by a passivation layer. Along the side surface, an amorphized and/or insulating region extending to a depth is formed, and the depth is perpendicular or substantially perpendicular to the layer stack.

Abstract: A stacked III-V semiconductor component having a stack with a top, a bottom, a side surface, and a longitudinal axis. The stack has a p+ region, an n? layer, and an n+ region. The p+ region, the n? layer, and the n+ region follow one another in the specified order along the longitudinal axis and are monolithic in design, and include a GaAs compound. The n+ region or the p+ region is a substrate layer. The stack has, in the region of the side surface, a first and a second peripheral, shoulder-like edge. The first edge is composed of the substrate layer; the second edge is composed of the n? layer or of an intermediate layer adjacent to the n? layer and to the p+ region and the first and the second peripheral edges each have a width of at least 10 ?m.

Abstract: A stacked high-blocking III-V power semiconductor diode, with a p+ or n+ substrate layer, a p? layer, an n? region with a layer thickness of 10 ?m-150 ?m, and an n+ or p+ layer, wherein all layers comprise a GaAs compound, a first metallic contact layer and a second metallic contact layer and a hard mask layer with at least one seed opening, wherein the hard mask layer is integrally bonded to the substrate layer or integrally bonded to the p? layer, the n? region extends within the seed opening and over an edge region, adjacent to the seed opening, of a top side of the hard mask layer and the n? region within the seed opening is integrally bonded to the p? layer or to the n+ substrate layer and in the edge region of the top side of the hard mask layer to the hard mask layer.

Abstract: A stacked III-V semiconductor component having a stack with a top, a bottom, a side surface, and a longitudinal axis. The stack has a p+ region, an n? layer, and an n+ region. The p+ region, the n? layer, and the n+ region follow one another in the specified order along the longitudinal axis and are monolithic in design, and include a GaAs compound. The n+ region or the p+ region is a substrate layer. The stack has, in the region of the side surface, a first and a second peripheral, shoulder-like edge. The first edge is composed of the substrate layer; the second edge is composed of the n? layer or of an intermediate layer adjacent to the n? layer and to the p+ region and the first and the second peripheral edges each have a width of at least 10 ?m.

Abstract: A stacked III-V semiconductor diode having an n+-layer with a dopant concentration of at least 1019 N/cm3, an n?-layer with a dopant concentration of 1012-1016 N/cm3, a layer thickness of 10-300 microns, a p+-layer with a dopant concentration of 5×1018-5×1020 cm3, with a layer thickness greater than 2 microns, wherein said layers follow one another in the sequence mentioned, each comprising a GaAs compound. The n+-layer or the p+-layer is formed as the substrate and a lower side of the n?-layer is materially bonded with an upper side of the n+-layer, and a doped intermediate layer is arranged between the n?-layer and the p+-layer and materially bonded with an upper side and a lower side.

Abstract: A method and stacked semiconductor device having a top surface, a bottom surface, and at least one side surface that connects the top surface with the bottom surface. The bottom surface is formed of a substrate layer or a rear side contact layer arranged below the substrate layer. On the substrate layer, a first semiconductor layer of a first conductivity type is arranged and on the first semiconductor layer at least one second semiconductor layer of a second conductivity type is arranged. The first and second semiconductor layers are formed of a III-V material or consist of a III-V material. The first and second conductivity types are different. The top surface is at least partially formed by a passivation layer. Along the side surface, an amorphized and/or insulating region extending to a depth is formed, and the depth is perpendicular or substantially perpendicular to the layer stack.