Abstract: A lateral MOS transistor is provided with a channel region, which has a channel width delimited by dielectric-filled trenches and which is covered with a gate dielectric, whose layer thickness varies over the channel width. An outer layer thickness, which the gate dielectric has over junctions of the channel region to the dielectric-filled trenches, is greater than an inner layer thickness, which the dielectric has over a central part of the channel region. Furthermore, a method for manufacturing the MOS transistor is provided.

Abstract: An SOI wafer including an active semiconductor material layer on an insulating layer is processed to form thereon first and second active semiconductor regions that respectively have different thicknesses and that are vertically and laterally insulated. In the process, a trench is etched into the SOI wafer, seed openings are formed in the bottom of the trench to reach the underlying active material layer, the trench is filled with epitaxially grown semiconductor material progressing from the seed openings, some of the epitaxially grown material is removed to form the second active regions, and oxide layers are provided so that the second active regions are laterally and vertically insulated from the first active regions formed by remaining portions of the active semiconductor material layer.

Abstract: An integrated circuit layout having a first circuit connection, a second circuit connection, and active components is provided, whereby the active components each have an input connection and an output connection and a predefined maximum reverse voltage between the input connection and the output connection, and whereby a maximum value of a voltage swing, achieved between the first circuit connection and the second circuit connection, is greater than the predefined maximum reverse voltage. The circuit layout is characterized in that an input connection of an n-th active component is connected to an output connection of an (n?1)-th active component, and that the circuit layout changes the potentials of terminal gates of the (n?1)-th component and the n-th component synchronously to a control signal.

Abstract: In a method of producing a doped semiconductor structure with a trench, it is possible to set the doping of the trench side walls independently from the doping of the trench bottom, and to set different doping concentrations of the individual trench side walls relative to each other. In the method, a mask layer with a window therein is provided on a surface of a semiconductor body, and then a first doping step, a trench etching step, and a second doping step are carried out successively through this window while this one mask layer remains in place on the surface of the semiconductor body. Further etching and doping steps can be carried out successively also through this window of the mask layer.

Abstract: A MOS transistor, and a method for producing the same, is provided with a source region, a gate-region, a drain region, and a drift region in an SOI wafer. The SOI-wafer has a carrier layer, which carries an insulating intermediate layer, and whereby the insulating intermediate layer carries an active semiconductor layer, in which laterally different doping material concentrations define the source region, the drift region, and the drain region. Whereby, the active semiconductor layer, at least in a portion of the drift region, is thicker than in the source region. The MOS transistor is characterized in that the active semiconductor layer, in a vertical direction, is completely separated by the insulating intermediate layer from the carrier layer.

Abstract: An SOI wafer including an active semiconductor material layer on an insulating layer is processed to form thereon first and second active semiconductor regions that respectively have different thicknesses and that are vertically and laterally insulated. In the process, a trench is etched into the SOI wafer, seed openings are formed in the bottom of the trench to reach the underlying active material layer, the trench is filled with epitaxially grown semiconductor material progressing from the seed openings, some of the epitaxially grown material is removed to form the second active regions, and oxide layers are provided so that the second active regions are laterally and vertically insulated from the first active regions formed by remaining portions of the active semiconductor material layer.

Abstract: Vertically insulated active semiconductor regions having different thicknesses in an SOI wafer, which has an insulating layer, is produced. On the wafer, first active semiconductor regions having a first thickness are arranged in a layer of active semiconductor material. The second active semiconductor regions having a relatively smaller thickness are produced by epitaxial growth proceeding from at least one seed opening in a trench structure. The second semiconductor regions are substantially completely dielectrically insulated, laterally and vertically, from the first semiconductor regions by oxide layers. The width of the seed opening can be defined by lithography.

Abstract: A semiconductor element such as a DMOS-transistor is fabricated in a semiconductor substrate. Wells of opposite conductivity are formed by implanting and then thermally diffusing respective well dopants into preferably spaced-apart areas in the substrate. At least one trench and active regions are formed in the substrate. The trench may be a shallow drift zone trench of a DMOS-transistor, and/or a deep isolation trench. The thermal diffusion of the well dopants includes at least one first diffusion step during a first high temperature drive before forming the trench, and at least one second diffusion step during a second high temperature drive after forming the trench. Dividing the thermal diffusion steps before and after the trench formation achieves an advantageous balance between reducing or avoiding lateral overlapping diffusion of neighboring wells and reducing or avoiding thermally induced defects along the trench boundaries.

Abstract: In a new process of making a DMOS transistor, the doping of the sloping side walls can be set independently from the doping of the floor region in a trench structure. Furthermore, different dopings can be established among the side walls. This is achieved especially by a sequence of implantation doping, etching to form the trench, formation of a scattering oxide protective layer on the side walls, and two-stage perpendicular and tilted final implantation doping. For DMOS transistors, this achieves high breakthrough voltages even with low turn-on resistances, and reduces the space requirement, in particular with regard to driver structures.

Abstract: A DMOS-transistor has a trench bordered by a drift region including two doped wall regions and a doped floor region extending along the walls and the floor of the trench. The laterally extending floor region has a dopant concentration gradient in the lateral direction. For example, the floor region includes at least two differently-doped floor portions successively in the lateral direction. This dopant gradient in the floor region is formed by carrying out at least one dopant implantation from above through the trench using at least one mask to expose a first area while covering a second area of the floor region.

Abstract: To form a semiconductor component having active regions separated from one another by trenches as isolation structures, a method involves forming a shallow trench in a semiconductor body, thereafter forming a deep trench within the shallow trench in the semiconductor body, and thereafter completely driving dopant atoms into the semiconductor body to form a well region doped with the dopant. The dopant may be previously introduced by implantation into a surface layer, and then the dopant is finally completely driven into the well region by thermally supported diffusion after forming the deep trench. The shallow and deep trenches together form a compound trench with stepped side walls. Two oppositely doped wells may be formed on opposite sides of the compound trench, which thus isolates the two wells from one another. Active regions may be formed in the two wells.

Abstract: In a new process of making a DMOS transistor, the doping of the sloping side walls can be set independently from the doping of the floor region in a trench structure. Furthermore, different dopings can be established among the side walls. This is achieved especially by a sequence of implantation doping, etching to form the trench, formation of a scattering oxide protective layer on the side walls, and two-stage perpendicular and tilted final implantation doping. For DMOS transistors, this achieves high breakthrough voltages even with low turn-on resistances, and reduces the space requirement, in particular with regard to driver structures.

Abstract: In a new process of making a DMOS transistor, the doping of the sloping side walls can be set independently from the doping of the floor region in a trench structure. Furthermore, different dopings can be established among the side walls. This is achieved especially by a sequence of implantation doping, etching to form the trench, formation of a scattering oxide protective layer on the side walls, and two-stage perpendicular and tilted final implantation doping. For DMOS transistors, this achieves high breakthrough voltages even with low turn-on resistances, and reduces the space requirement, in particular with regard to driver structures.

Abstract: An SOI wafer includes a substrate, and an insulating intermediate layer and a surface layer successively thereon. At least one laterally limited suicide area is formed in and/or on the surface layer. Then an oxide layer is provided on the surface layer of the SOI wafer and/or on a second silicon wafer, before the two wafers are bonded to each other along the oxide layer. The substrate and the insulating intermediate layer are removed to leave a bonded multi-layered wafer. At least one device component is fabricated in and/or on the surface layer to include the silicide area as a functional element of the device component. Different types of components, e.g. MOS and bipolar transistors, can be fabricated together on the same wafer, and HF characteristics are improved by the low ohmic suicide area(s).

Abstract: A manufactured multi-layered silicon wafer with a buried insulating layer and buried areas with different parameters is formed by bonding together a first wafer and a second wafer. Before the bonding, areas with modified layer parameters, which will be buried by bonding with the second wafer, are created on the surface of the first wafer, which also has an insulating intermediate layer. A further insulating layer is then applied, and the surface of the first wafer is bonded to the surface of the second wafer. The substrate layer and the insulating intermediate layer of the first wafer are subsequently removed. This eliminates the conventional thinning of the second wafer. In addition, areas with vertical gradients can be created in the layer parameters without processing the second wafer.

Abstract: In a method for manufacturing a silicon wafer with an insulating intermediate layer, the surface of a first wafer, which has an insulating intermediate layer, is bonded to the surface of a second wafer, and then the substrate layer and the insulating intermediate layer of the fist wafer are removed. The new silicon surface created in this manner has a high layer quality which is achieved at a low cost.

Abstract: In the processes known so far, for a trench-shaped structure the doping of the side walls is coupled to the doping of the floor region.

Abstract: In the processes known so far, for a trench-shaped structure the doping of the side walls is coupled to the doping of the bottom region.

Abstract: In the processes known so far, for a trench-shaped structure the doping of the side walls is coupled to the doping of the floor region.

Abstract: In the processes known so far, for a trench-shaped structure the doping of the side walls is coupled to the doping of the floor region.