Patents by Inventor Volker Dudek
Volker Dudek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7973333Abstract: A lateral DMOS-transistor is provided that includes a MOS-diode made of a semi-conductor material of a first type of conductivity, a source-area of a second type of conductivity and a drain-area of a second type of conductivity which is separated from the MOS-diode by a drift region made of a semi-conductor material of a second type of conductivity which is at least partially covered by a dielectric gate layer which also covers the semi-conductor material of the MOS-diode. The dielectric gate-layer comprises a first region of a first thickness and a second region of a second thickness. The first region covers the semi-conductor material of the MOS-diode and the second region is arranged on the drift region. A transition takes place from the first thickness to the second thickness such that an edge area of the drift region which is oriented towards the MOS-diode is arranged below the second area of the gate layer. The invention also relates to a method for the production of these types of DMOS-transistors.Type: GrantFiled: April 2, 2007Date of Patent: July 5, 2011Assignee: Telefunken Semiconductors GmbH & Co. KGInventors: Franz Dietz, Volker Dudek, Thomas Hoffmann, Michael Graf, Stefan Schwantes
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Patent number: 7923362Abstract: A method for manufacturing a metal-semiconductor contact in semiconductor Components is disclosed. There is a relatively high risk of contamination in the course of metal depositions in prior-art methods. In the disclosed method, the actual metal -semiconductor or Schottky contact is produced only after the application of a protective layer system, as a result of which it is possible to use any metals, particularly platinum, without the risk of contamination.Type: GrantFiled: June 6, 2006Date of Patent: April 12, 2011Assignee: TELEFUNKEN Semiconductors GmbH & Co. KGInventors: Franz Dietz, Volker Dudek, Tobias Florian, Michael Graf
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Patent number: 7851326Abstract: A method for producing deep trench structures in an STI structure of a semiconductor substrate is provided, with the following successive process steps: subsequent to a full-area filling of STI recesses introduced into a semiconductor substrate with a first filler material, a first surface of a semiconductor structure is subjected to a CMP process to level the applied filler material and produce the STI structure; the leveled STI structure thus produced is structured; using the structured, leveled STI structure as a hard mask, at least one deep trench is etched in the area of this STI structure to create the deep trench structures.Type: GrantFiled: June 18, 2007Date of Patent: December 14, 2010Assignee: TELEFUNKEN Semiconductors GmbH & Co. KGInventors: Franz Dietz, Volker Dudek, Michael Graf, Thomas Hoffmann
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Patent number: 7848070Abstract: An electrostatic discharge (ESD) protection structure is disclosed. The ESD protection structure includes an active device. The active device includes a plurality of drains. Each of the drains has a contact row and at least one body contact row. The at least one body contact row is located on the active device in a manner to reduce the amount of voltage required for triggering the ESD protection structure.Type: GrantFiled: July 21, 2008Date of Patent: December 7, 2010Assignee: Atmel CorporationInventors: Stefan Schwantes, Michael Graf, Volker Dudek, Gayle W. Miller, Jr., Irwin Rathbun, Peter Grombach, Manfred Klaussner
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Patent number: 7816758Abstract: An integrated circuit is disclosed that includes a first layer made of active semiconductor material and extending along a first side of a buried layer, and trench structures, which cut through the layer made of active semiconductor material and have dielectric wall regions, whereby the dielectric wall regions isolate electrically subregions of the layer, made of active semiconductor material in the lateral direction, and whereby the trench structures, furthermore, have first inner regions, which are filled with electrically conductive material and contact the buried layer in an electrically conductive manner. The integrated circuit is notable in that the first wall regions of the trench structures completely cut through the buried layer and the second wall regions of the trench structures extend into the buried layer, without cutting it completely. Furthermore, a method for manufacturing such an integrated circuit is disclosed.Type: GrantFiled: July 24, 2006Date of Patent: October 19, 2010Assignee: Atmel Automotive GmbHInventor: Volker Dudek
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Publication number: 20090273883Abstract: A method and system for fabricating a stacked capacitor and a DMOS transistor are disclosed. In one aspect, the method and system include providing a bottom plate, an insulator, and an additional layer including first and second plates. The insulator covers at least a portion of the bottom plate and resides between the first and second top plates and the bottom plate. The first and second top plates are electrically coupled through the bottom plate. In another aspect, the method and system include forming a gate oxide. The method and system also include providing SV well(s) after the gate oxide is provided. A portion of the SV well(s) resides under a field oxide region of the device. Each SV well includes first, second, and third implants having a sufficient energy to provide the portion of the SV well at a desired depth under the field oxide region without significant additional thermal processing. A gate, source, and drain are also provided.Type: ApplicationFiled: July 13, 2009Publication date: November 5, 2009Inventors: Stefan Schwantes, Volker Dudek, Michael Graf, Alan Renninger, James Shen
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Patent number: 7601568Abstract: A MOS transistor, and a method for producing the same, is provided with a source region, a gate-region, a drain region, and a drift region in an SOI wafer. The SOI-wafer has a carrier layer, which carries an insulating intermediate layer, and whereby the insulating intermediate layer carries an active semiconductor layer, in which laterally different doping material concentrations define the source region, the drift region, and the drain region. Whereby, the active semiconductor layer, at least in a portion of the drift region, is thicker than in the source region. The MOS transistor is characterized in that the active semiconductor layer, in a vertical direction, is completely separated by the insulating intermediate layer from the carrier layer.Type: GrantFiled: March 28, 2007Date of Patent: October 13, 2009Assignee: Atmel Germany GmbHInventor: Volker Dudek
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Patent number: 7560334Abstract: A method and system for fabricating a stacked capacitor and a DMOS transistor are disclosed. In one aspect, the method and system include providing a bottom plate, an insulator, and an additional layer including first and second plates. The insulator covers at least a portion of the bottom plate and resides between the first and second top plates and the bottom plate. The first and second top plates are electrically coupled through the bottom plate. In another aspect, the method and system include forming a gate oxide. The method and system also include providing SV well(s) after the gate oxide is provided. A portion of the SV well(s) resides under a field oxide region of the device. Each SV well includes first, second, and third implants having a sufficient energy to provide the portion of the SV well at a desired depth under the field oxide region without significant additional thermal processing. A gate, source, and drain are also provided.Type: GrantFiled: October 20, 2005Date of Patent: July 14, 2009Assignee: Atmel CorporationInventors: Stefan Schwantes, Volker Dudek, Michael Graf, Alan Renninger, James Shen
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Publication number: 20090160009Abstract: Semiconductor array and method for manufacturing a semiconductor array, wherein a conductive substrate (100), an element region (400), and an insulation layer (200), isolating the element region (400) from the conductive substrate (100), are formed, a trench (700) is etched in the element region (400) as far as the insulation layer (200), the trench (700) is etched further in the insulation layer (200) as far as the conductive substrate (100), and within the trench (700), the conductive substrate (100) is at least partially etched to form conductive substrate regions (141, 142, 143, 144, 145, 146), isolated from one another.Type: ApplicationFiled: September 28, 2006Publication date: June 25, 2009Applicant: ATMEL Germany GmbHInventors: Franz Dietz, Volker Dudek, Tobias Florian, Holger Hoehnemann, Stefan Schwantes
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Patent number: 7539965Abstract: An integrated circuit layout having a first circuit connection, a second circuit connection, and active components is provided, whereby the active components each have an input connection and an output connection and a predefined maximum reverse voltage between the input connection and the output connection, and whereby a maximum value of a voltage swing, achieved between the first circuit connection and the second circuit connection, is greater than the predefined maximum reverse voltage. The circuit layout is characterized in that an input connection of an n-th active component is connected to an output connection of an (n?1)-th active component, and that the circuit layout changes the potentials of terminal gates of the (n?1)-th component and the n-th component synchronously to a control signal.Type: GrantFiled: August 5, 2005Date of Patent: May 26, 2009Assignee: Atmel Germany GmbHInventors: Christoph Bromberger, Volker Dudek
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Patent number: 7504692Abstract: High-voltage field-effect transistor is provided that includes a drain terminal, a source terminal, a body terminal, and a gate terminal. A gate oxide and a gate electrode, adjacent to the gate oxide, is connected to the gate terminal. A drain semiconductor region of a first conductivity type is connected to the drain terminal. A source semiconductor region of a first conductivity type is connected to the source terminal. A body terminal semiconductor region of a second conductivity type is connected to the body terminal. A body semiconductor region of the second conductivity type, is partially adjacent to the gate oxide to form a channel and is adjacent to the body terminal semiconductor region. A drift semiconductor region of the first conductivity type is adjacent to the drain semiconductor region and the body semiconductor region, wherein in the drift semiconductor region, a potential barrier is formed in a region distanced from the body semiconductor region.Type: GrantFiled: September 11, 2006Date of Patent: March 17, 2009Assignee: Atmel Germany GmbHInventors: Volker Dudek, Michael Graf, Stefan Schwantes
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Publication number: 20080290426Abstract: A method of fabricating an electronic device and a resulting electronic device. The method includes forming a pad oxide layer on a substrate, forming a silicon nitride layer over the pad oxide layer, and forming a top oxide layer over the silicon nitride layer. A first dopant region is then formed in a first portion of the substrate. A first portion of the top oxide layer is removed; a remaining portion of the top oxide layer is used to align a second dopant mask and a second dopant region is formed. An annealing step drives-in the dopants but oxygen diffusion to the substrate is limited by the silicon nitride layer; the silicon nitride layer thereby assures that the uppermost surface of the silicon is substantially planar in an area proximate to the dopant regions after the annealing step.Type: ApplicationFiled: August 4, 2008Publication date: November 27, 2008Applicant: Atmel CorporationInventors: Gayle W. Miller, Irwin D. Rathbun, Stefan Schwantes, Michael Graf, Volker Dudek
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Publication number: 20080278874Abstract: An electrostatic discharge (ESD) protection structure is disclosed. The ESD protection structure includes an active device. The active device includes a plurality of drains. Each of the drains has a contact row and at least one body contact row. The at least one body contact row is located on the active device in a manner to reduce the amount of voltage required for triggering the ESD protection structure.Type: ApplicationFiled: July 21, 2008Publication date: November 13, 2008Inventors: Stefan Schwantes, Michael Graf, Volker Dudek, Gayle W. Miller, JR., Irwin Rathbun, Peter Grombach, Manfred Klaussner
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Patent number: 7407851Abstract: A method of fabricating an electronic device and a resulting electronic device. The method includes forming a pad oxide layer on a substrate, forming a silicon nitride layer over the pad oxide layer, and forming a top oxide layer over the silicon nitride layer. A first dopant region is then formed in a first portion of the substrate. A first portion of the top oxide layer is removed; a remaining portion of the top oxide layer is used to align a second dopant mask and a second dopant region is formed. An annealing step drives-in the dopants but oxygen diffusion to the substrate is limited by the silicon nitride layer; the silicon nitride layer thereby assures that the uppermost surface of the silicon is substantially planar in an area proximate to the dopant regions after the annealing step.Type: GrantFiled: March 22, 2006Date of Patent: August 5, 2008Inventors: Gayle W. Miller, Irwin D. Rathbun, Stefan Schwantes, Michael Graf, Volker Dudek
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Publication number: 20080173940Abstract: A method of fabricating an electronic device and the resulting electronic device. The method includes forming a gate oxide on an uppermost side of a silicon-on-insulator substrate; forming a first polysilicon layer over the gate oxide; and forming a first silicon dioxide layer over the first polysilicon layer. A first silicon nitride layer is then formed over the first silicon dioxide layer followed by a second silicon dioxide layer. Shallow trenches are etched through all preceding dielectric layers and into the SOI substrate. The etched trenches are filled with another dielectric layer (e.g., silicon dioxide) and planarized. Each of the preceding dielectric layers are removed, leaving an uppermost sidewall area of the dielectric layer exposed for contact with a later-applied polysilicon gate area. Formation of the sidewall area assures a full-field oxide thickness thereby producing a device with a reduced-electric field and a reduced capacitance between gate and drift regions.Type: ApplicationFiled: January 23, 2008Publication date: July 24, 2008Applicant: Atmel CorporationInventors: Gayle W. Miller, Volker Dudek, Michael Graf
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Patent number: 7402846Abstract: An electrostatic discharge (ESD) protection structure is disclosed. The ESD protection structure includes an active device. The active device includes a plurality of drains. Each of the drains has a contact row and at least one body contact row. The at least one body contact row is located on the active device in a manner to reduce the amount of voltage required for triggering the ESD protection structure.Type: GrantFiled: October 20, 2005Date of Patent: July 22, 2008Assignee: Atmel CorporationInventors: Stefan Schwantes, Michael Graf, Volker Dudek, Gayle W. Miller, Jr., Irwin Rathbun, Peter Grombach, Manfred Klaussner
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Publication number: 20080135933Abstract: A method of fabricating an electronic device and the resulting electronic device. The method includes forming a gate oxide on an uppermost side of a silicon-on-insulator substrate; forming a first polysilicon layer over the gate oxide; and forming a first silicon dioxide layer over the first polysilicon layer. A first silicon nitride layer is then formed over the first silicon dioxide layer followed by a second silicon dioxide layer. Shallow trenches are etched through all preceding dielectric layers and into the SOI substrate. The etched trenches are filled with another dielectric layer (e.g., silicon dioxide) and planarized. Each of the preceding dielectric layers are removed, leaving an uppermost sidewall area of the dielectric layer exposed for contact with a later-applied polysilicon gate area. Formation of the sidewall area assures a full-field oxide thickness thereby producing a device with a reduced-electric field and a reduced capacitance between gate and drift regions.Type: ApplicationFiled: January 23, 2008Publication date: June 12, 2008Applicant: Atmel CorporationInventors: Gayle W. Miller, Volker Dudek, Michael Graf
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Patent number: 7348256Abstract: A method of fabricating an electronic device and the resulting electronic device. The method includes forming a gate oxide on an uppermost side of a silicon-on-insulator substrate; forming a first polysilicon layer over the gate oxide; and forming a first silicon dioxide layer over the first polysilicon layer. A first silicon nitride layer is then formed over the first silicon dioxide layer followed by a second silicon dioxide layer. Shallow trenches are etched through all preceding dielectric layers and into the SOI substrate. The etched trenches are filled with another dielectric layer (e.g., silicon dioxide) and planarized. Each of the preceding dielectric layers are removed, leaving an uppermost sidewall area of the dielectric layer exposed for contact with a later-applied polysilicon gate area. Formation of the sidewall area assures a full-field oxide thickness thereby producing a device with a reduced-electric field and a reduced capacitance between gate and drift regions.Type: GrantFiled: July 25, 2005Date of Patent: March 25, 2008Assignee: Atmel CorporationInventors: Gayle W. Miller, Jr., Volker Dudek, Michael Graf
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Publication number: 20070264792Abstract: A method for producing deep trench structures in an STI structure of a semiconductor substrate is provided, with the following successive process steps: subsequent to a full-area filling of STI recesses introduced into a semiconductor substrate with a first filler material, a first surface of a semiconductor structure is subjected to a CMP process to level the applied filler material and produce the STI structure; the leveled STI structure thus produced is structured; using the structured, leveled STI structure as a hard mask, at least one deep trench is etched in the area of this STI structure to create the deep trench structures.Type: ApplicationFiled: June 18, 2007Publication date: November 15, 2007Inventors: Franz Dietz, Volker Dudek, Michael Graf, Thomas Hoffmann
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Publication number: 20070262376Abstract: High-voltage field-effect transistor is provided that includes a drain terminal, a source terminal, a body terminal, and a gate terminal. A gate oxide and a gate electrode, adjacent to the gate oxide, is connected to the gate terminal. A drain semiconductor region of a first conductivity type is connected to the drain terminal. A source semiconductor region of a first conductivity type is connected to the source terminal. A body terminal semiconductor region of a second conductivity type is connected to the body terminal. A body semiconductor region of the second conductivity type, is partially adjacent to the gate oxide to form a channel and is adjacent to the body terminal semiconductor region. A drift semiconductor region of the first conductivity type is adjacent to the drain semiconductor region and the body semiconductor region, wherein in the drift semiconductor region, a potential barrier is formed in a region distanced from the body semiconductor region.Type: ApplicationFiled: September 11, 2006Publication date: November 15, 2007Inventors: Volker Dudek, Michael Graf, Stefan Schwantes