Abstract: Embodiments include techniques for static random access memory (SRAM) bitline equalization using phase change material (PCM). The techniques include detecting a defect in SRAM bitlines, and programming a variable resistance PCM cell to offset the detected defect. The techniques also include measuring signal development time for the SRAM bitlines, and adjusting the programming of the variable resistance PCM cell based at least in part on the measured signal development for the SRAM bitlines.

Abstract: Embodiments of the present invention provide systems and methods for re-balancing the stability of a SRAM cell. Embodiments of the present invention identify SRAM cells with negative voltage threshold margins and write a “zero” state bit with in the bi-stable flip-flop of the SRAM. Raising the voltage of the CMOS set containing the “zero” state bit and selective transistor biasing, skews the “zero” state bit towards the complementary “one” state bit. This induces an increase voltage thresholds of the identified SRAM cells.

Abstract: Embodiments include techniques for static random access memory (SRAM) bitline equalization using phase change material (PCM). The techniques include detecting a defect in SRAM bitlines, and programming a variable resistance PCM cell to offset the detected defect. The techniques also include measuring signal development time for the SRAM bitlines, and adjusting the programming of the variable resistance PCM cell based at least in part on the measured signal development for the SRAM bitlines.

Abstract: Embodiments of the present invention provide systems and methods for re-balancing the stability of a SRAM cell. Embodiments of the present invention identify SRAM cells with negative voltage threshold margins and write a “zero” state bit with in the bi-stable flip-flop of the SRAM. Raising the voltage of the CMOS set containing the “zero” state bit and selective transistor biasing, skews the “zero” state bit towards the complementary “one” state bit. This induces an increase voltage thresholds of the identified SRAM cells.

Abstract: Embodiments of the present invention provide systems and methods for re-balancing the stability of a SRAM cell. Embodiments of the present invention identify SRAM cells with negative voltage threshold margins and write a “zero” state bit with in the bi-stable flip-flop of the SRAM. Raising the voltage of the CMOS set containing the “zero” state bit and selective transistor biasing, skews the “zero” state bit towards the complementary “one” state bit. This induces an increase voltage thresholds of the identified SRAM cells.

Abstract: Embodiments of the present invention provide systems and methods for re-balancing the stability of a SRAM cell. Embodiments of the present invention identify SRAM cells with negative voltage threshold margins and write a “zero” state bit with in the bi-stable flip-flop of the SRAM. Raising the voltage of the CMOS set containing the “zero” state bit and selective transistor biasing, skews the “zero” state bit towards the complementary “one” state bit. This induces an increase voltage thresholds of the identified SRAM cells.

Abstract: Embodiments include techniques for static random access memory (SRAM) bitline equalization using phase change material (PCM). The techniques include detecting a defect in SRAM bitlines, and programming a variable resistance PCM cell to offset the detected defect. The techniques also include measuring signal development time for the SRAM bitlines, and adjusting the programming of the variable resistance PCM cell based at least in part on the measured signal development for the SRAM bitlines.

Abstract: Embodiments include techniques for static random access memory (SRAM) bitline equalization using phase change material (PCM). The techniques include detecting a defect in SRAM bitlines, and programming a variable resistance PCM cell to offset the detected defect. The techniques also include measuring signal development time for the SRAM bitlines, and adjusting the programming of the variable resistance PCM cell based at least in part on the measured signal development for the SRAM bitlines.

Abstract: A method for fabricating a circuit comprises identifying a target on the circuit with a transitional sensitivity, determining a test pattern that stresses the target, generating a verification model at the hierarchy of the target, creating a pattern and translating the pattern into a verification assertion, running the verification with the translated pattern, determining whether the verification assertion is a possible verification assertion following the running of the verification, obtaining a state of source laches and pin inputs responsive to determining that the formal verification assertion is a possible verification assertion following the running of the formal verification, translating the formal verification assertion into a coverage event, running a simulation with the coverage event, determining whether the coverage event occurred, and creating a manufacturing test responsive to determining that the coverage event occurred.

Abstract: Aspects of present disclosure relate to an integrated circuit chip (chip), a method and a computer program product of testing the chip. The method of testing the chip may include: partitioning the chip into various partitions, loading built-in self-test (BIST) test instructions into BIST engine and initializing a current partition counter, performing BIST test on current partition, transmitting test results of the current partition of the chip to an external test data storage, checking whether current partition is the last partition, incrementing current partition counter, and returning to performing BIST on a next partition when current partition is not the last partition, and exiting BIST test when current partition is the last partition. The test results may be stored in one or more inactive storage elements of the chip. The number of partitions may include: one partition, a predetermined number of partitions, and a variable number of partitions.

Abstract: A method for fabricating a circuit comprises identifying a target on the circuit with a transitional sensitivity, determining a test pattern that stresses the target, generating a verification model at the hierarchy of the target, creating a pattern and translating the pattern into a verification assertion, running the verification with the translated pattern, determining whether the verification assertion is a possible verification assertion following the running of the verification, obtaining a state of source laches and pin inputs responsive to determining that the formal verification assertion is a possible verification assertion following the running of the formal verification, translating the formal verification assertion into a coverage event, running a simulation with the coverage event, determining whether the coverage event occurred, and creating a manufacturing test responsive to determining that the coverage event occurred.

Abstract: An apparatus and method may detect and reduce noise on data busses by adjusting the phase of the input/output (I/O) signals in a controlled, predictable manner. The control may allow a maximum data rate to be achieved. In one embodiment, an algorithm used to determine phase change data may be handled by a feedback loop and may be dynamically adjusted. The system may detect noise on rails and critical signals for logging in call home data. The system may maintain a database of settings as a function of a workload. The system may be used in the field as the workload changes to determine that a signal has reached a first threshold. In response to determining that the signal has reached the first threshold, an alert is initiated. A system may determine that the signal has reached a second threshold. In response to determining that the signal has reached the second threshold, the signal may be coupled to logic circuitry.

Abstract: A method for fabricating a circuit comprises identifying a target on the circuit with a transitional sensitivity, determining a test pattern that stresses the target, generating a verification model at the hierarchy of the target, creating a pattern and translating the pattern into a verification assertion, running the verification with the translated pattern, determining whether the verification assertion is a possible verification assertion following the running of the verification, obtaining a state of source latches and pin inputs responsive to determining that the formal verification assertion is a possible verification assertion following the running of the formal verification, translating the formal verification assertion into a coverage event, running a simulation with the coverage event, determining whether the coverage event occurred, and creating a manufacturing test responsive to determining that the coverage event occurred.

Abstract: A method detects electromigration in an electronic device. An integrated circuit, which is within an electronic device, is quiescented. An isolation power switch applies a test voltage from a field power source to a target voltage rail in the integrated circuit. An isolation power switch isolates the target voltage rail from the field power source. A voltage sensor coupled to the target voltage rail measures a field voltage decay rate for the target voltage rail. A voltage record comparator logic within the integrated circuit compares the field voltage decay rate to an initial voltage decay rate for the target voltage rail. In response to a difference between the field voltage decay rate and the initial voltage decay rate for the target voltage rail exceeding a predetermined limit, a signal is sent to an alarm associated with the electronic device.

Abstract: A method for fabricating a circuit comprises identifying a target on the circuit with a transitional sensitivity, determining a test pattern that stresses the target, generating a verification model at the hierarchy of the target, creating a pattern and translating the pattern into a verification assertion, running the verification with the translated pattern, determining whether the verification assertion is a possible verification assertion following the running of the verification, obtaining a state of source laches and pin inputs responsive to determining that the formal verification assertion is a possible verification assertion following the running of the formal verification, translating the formal verification assertion into a coverage event, running a simulation with the coverage event, determining whether the coverage event occurred, and creating a manufacturing test responsive to determining that the coverage event occurred.

Abstract: A method detects electromigration in a field replaceable unit. An integrated circuit, which is within a field replaceable unit (FRU) in an electronic device, is quiescented. An isolation power switch applies a test voltage from a field power source to a target voltage rail in the integrated circuit. An isolation power switch isolates the target voltage rail from the field power source. A voltage sensor coupled to the target voltage rail measures a field voltage decay rate for the target voltage rail. A voltage record comparator logic within the integrated circuit compares the field voltage decay rate to an initial voltage decay rate for the target voltage rail. In response to a difference between the field voltage decay rate and the initial voltage decay rate for the target voltage rail exceeding a predetermined limit, a signal is sent to an output device.

Abstract: Aspects of present disclosure relate to an integrated circuit chip (chip), a method and a computer program product of testing the chip. The method of testing the chip may include: partitioning the chip into various partitions, loading built-in self-test (BIST) test instructions into BIST engine and initializing a current partition counter, performing BIST test on current partition, transmitting test results of the current partition of the chip to an external test data storage, checking whether current partition is the last partition, incrementing current partition counter, and returning to performing BIST on a next partition when current partition is not the last partition, and exiting BIST test when current partition is the last partition. The test results may be stored in one or more inactive storage elements of the chip. The number of partitions may include: one partition, a predetermined number of partitions, and a variable number of partitions.

Abstract: A computer-implemented method for command-address-control calibration of a memory device includes starting, via a processor, a controller clock for the memory device, releasing, via the processor, a reset on the memory device, running, via the processor, a calibration pattern for calibrating the memory device by placing the memory device in calibration mode, where the calibration pattern is initiated prior to an initialization of the memory device, calibrating, via the processor, the memory device with a calibration setting based on the calibration pattern, and initializing the memory device based on the calibration setting.

Abstract: Aspects include a computer-implemented method for initializing scannable and non-scannable latches from a clock buffer. The method includes receiving a clock signal; receiving control signals including a hold signal, a scan enable signal, and a non-scannable latch force signal; responsive to receiving a low input from the hold signal and the scan enable signal, outputting a high signal from a functional clock port on a next cycle; responsive to receiving a high input from the scan enable signal and a low input from the hold signal, outputting a high slave latch scan clock signal on the next cycle; responsive to receiving a high input from the hold signal and the scan enable signal, outputting a high master latch clock signal on the next clock cycle; and responsive to receiving a high input from the non-scannable latch force signal, outputting a low master latch clock signal on a current cycle.

Abstract: Aspects include a computer-implemented method for initializing scannable and non-scannable latches from a clock buffer. The method includes receiving a clock signal; receiving control signals including a hold signal, a scan enable signal, and a non-scannable latch force signal; responsive to receiving a low input from the hold signal and the scan enable signal, outputting a high signal from a functional clock port on a next cycle; responsive to receiving a high input from the scan enable signal and a low input from the hold signal, outputting a high slave latch scan clock signal on the next cycle; responsive to receiving a high input from the hold signal and the scan enable signal, outputting a high master latch clock signal on the next clock cycle; and responsive to receiving a high input from the non-scannable latch force signal, outputting a low master latch clock signal on a current cycle.