Abstract: The semiconductor memory device comprises a plurality of memory cells. Each memory cell comprises a respective transistor and a respective capacitor unit. The transistor comprises a transistor body of a first conductivity type, a drain area and a source area each having a second conductivity type, the drain area and source area are embedded in the transistor body on a first surface of the transistor body, and a gate structure having a gate dielectric layer and a gate electrode, the gate structure is arranged between the drain area and the source area. An isolation trench is arranged adjacent to said transistor body, having a dielectric layer and a conductive material, wherein the isolation trench is at least partially filled with the conductive material. The conductive material is isolated by said dielectric layer from the transistor body. The capacitor unit is formed by the transistor body representing a first electrode and the conductive material representing the second electrode.

Abstract: A semiconductor memory device comprises a plurality of memory cells, each memory cell having a respective transistor. The transistor comprises a transistor body of a first conductivity type, a drain area and a source area each having a second conductivity type, wherein said drain area and source area are embedded in the transistor body on a first surface of said transistor body, a gate structure having a gate dielectric layer and a gate electrode. Said gate structure is arranged between said drain area and said source area. An emitter area of said first conductivity type is provided wherein said emitter area is arranged on top of said drain area.

Abstract: The invention relates to a vertical integrated component, a component arrangement and a method for production of a vertical integrated component. The vertical integrated component has a first electrical conducting layer, a mid layer, partly embodied from dielectric material on the first electrical conducting layer, a second electrical conducting layer on the mid layer and a nanostructure integrated in a through hold introduced in the mid layer. A first end section of the nanostructure is coupled to the first electrical conducting layer and a second end section is coupled to the second electrical conducting layer. The mid layer includes a third electrical conducting layer between two adjacent dielectric partial layers, the thickness of which is less than the thickness of at least one of the dielectric partial layers.

Abstract: An electrical feedthrough is provided to establish an electrical conduction path from an interior of a hermetically sealed housing to an exterior environment. The feedthrough comprises an elongated electrically conductive pin having opposing proximal and distal ends and a medial portion configured to be supported within a corresponding aperture in a first housing member. A first cantilevered spring contact is affixed to and projects from a selected one of the proximal and distal ends of the pin. Preferably, a second cantilevered spring contact is further affixed to and projects from the remaining one of the proximal and distal ends of the pin. A plurality of feedthroughs are preferably affixed through an insertion member to form a feedthrough assembly which is then affixed adjacent an aperture in the first housing member. An insulating member in the plate preferably supports and isolates a pair of the pins to transmit a differential signal.

Abstract: A hermetically sealed housing such as for use in a data storage device. The housing is formed from a pair of opposing, substantially planar first and second housing members. A gasket seal is compressed between the housing members to form a hermetic seal. A compression limit spacer limits the compression of the gasket seal to a predetermined compression level. Preferably, the gasket seal is nested within and is contactingly supported by the compression limit spacer. A plurality of fasteners secure the first and second housing members and apply a compressive force to the gasket seal. The compression limit spacer preferably comprises a plurality of discrete, spaced apart bosses through which the plurality of fasteners extend. The gasket seal preferably has a hexagonal or a c-shaped cross-sectional shape. An inert fluidic atmosphere is preferably retained within the housing.

Abstract: In an enclosure, electrical connections to a bulkhead connector may be made using a flex spring. The flex spring may have a frame and one or more spring members supported at their proximal ends by the frame. At their distal ends, the spring members may be configured to apply a distributed load to compress a set of contacts on a flex assembly against a corresponding set of contacts on a bulkhead connector. The pressure applied by the flex spring may be distributed to make reliable electrical connection between the corresponding sets of contacts. In one embodiment, the frame of the flex spring may be attached to a flex bracket. The flex bracket may mount to a wall of a base to which the bulkhead connector is mounted.

Abstract: An integrated circuit arrangement and method of fabricating the integrated circuit arrangement is described. The integrated circuit arrangement contains an insulating region and a sequence of regions which forms a capacitor. The sequence contains a near electrode region near the insulating region, a dielectric region, and a remote electrode region remote from the insulating region. The insulating region is part of an insulating layer arranged in a plane. The capacitor and an active component are arranged on the same side of the insulating layer and form a memory cell. The near electrode region and an active region of the component are arranged in a plane which lies parallel to the plane in which the insulating layer is arranged. A processor is also contained in the integrated circuit arrangement.

Abstract: A nonvolatile memory cell, memory cell arrangement, and method for production of a nonvolatile memory cell is disclosed. The nonvolatile memory cell includes a vertical field-effect transistor (FET). The FET contains a nanoelement arranged as a channel region and an electrically insulating layer. The electrically insulating layer at least partially surrounds the nanoelement and acts as a charge storage layer and as a gate-insulating layer. The electrically insulating layer is arranged such that electrical charge carriers may be selectively introduced into or removed from the electrically insulating layer and the electrical conductivity characteristics of the nanoelement may be influenced by the electrical charge carriers introduced into the electrically insulating layer.

Abstract: An integrated circuit arrangement contains an insulating region, which is part of a planar insulating layer, and a capacitor which contains: near and far electrode regions near and remote from the insulating region and a dielectric region. The capacitor and an active component are on the same side of the insulating layer, and the near electrode region and an active region of the component are planar and parallel to the insulating layer. The near electrode region is monocrystalline and contains multiple webs. Alternately, a FET is present in which: a channel region is the active region, the FET contains a web with opposing control electrodes connected by a connecting region that is isolated from the channel region by a thick insulating region. The thick insulating region is thicker than control electrode insulation regions. The control electrodes contain the same material as the far electrode region.

Abstract: The bar-type field effect transistor consists of a substrate, a bar placed above a substrate and a gate and spacer placed above part of the bar.

Abstract: A semiconductor substrate and a semiconductor circuit formed therein and associated fabrication methods are provided. A multiplicity of depressions with a respective dielectric layer and a capacitor electrode are formed for realizing buried capacitors in a carrier substrate and an actual semiconductor component layer being insulated from the carrier substrate by an insulation layer.

Abstract: A hermetically sealed housing such as for use in a data storage device. Opposing first and second housing members are coupled together with respective interior surfaces in facing relationship to form a hermetically sealed interior environment. An internally mounted shaft includes a medial portion about which a rotatable article rotates, a proximal end internally supported by the first housing member, and a distal end internally supported by the second housing member. In some embodiments, at least one of the proximal and distal ends fits into a corresponding recess formed in the respective housing member. In other embodiments, at least one of the proximal and distal ends includes a cup-shaped recess which accommodates a pin that projects from the respective housing member. Layers of compliant material are preferably provided at the interfaces between the ends of the shaft and the respective housing members.

Abstract: A floating gate field-effect transistor (400), which is preferably used as a memory cell, has, above or below a floating gate region (407), an electrically insulating layer sequence (408) having a lower layer (409) having a first relative permittivity, having a middle layer (410) having a second relative permittivity, and having an upper layer (411) having a third relative permittivity, the second relative permittivity being greater than the first relative permittivity and greater than the third relative permittivity.

Abstract: In a semiconductor memory, a plurality of FinFET arrangements with trapping layers or floating gate electrodes as storage mediums are present on respective top sides of fins made from semiconductor material. The material of the gate electrodes is also present on two side walls of the fins, in order to form side wall transistors, and between the gate electrodes forms parts of a word line belonging to the corresponding fin.

Abstract: A vertical semiconductor transistor component is built up on a substrate by using a statistical mask. The vertical semiconductor transistor component has vertical pillar structures statistically distributed over the substrate. The vertical pillar structures are electrically connected on a base side thereof to a first common electrical contact. The vertical pillar structures include, along the vertical direction, layer zones of differing conductivity, and have insulation layers on their circumferential walls. An electrically conductive material is deposited between the pillar structures and forms a second electrical contact of the semiconductor transistor component. The pillar structures are electrically contacted to a third common electrical contact on their capping side.

Abstract: The invention relates to a layer arrangement, a memory cell, a memory cell arrangement and a method for producing a layer arrangement. The layer arrangement has a monocrystalline substrate, a highly doped region in the substrate and a metallically conductive structure in the highly doped region, a partial region of the highly doped region that is arranged in a surface region of the substrate being monocrystalline.

Abstract: A double gate MOSFET transistor and a method for fabricating it are described. In this case, a semiconductor layer structure of a transistor channel to be formed is embedded in a spacer material and contact-connected by source and drain regions which are filled into depressions that are etched on opposite sides of the semiconductor layer structure. Afterwards, the spacer material is etched out selectively and replaced by the electrically conductive gate electrode material.

Abstract: A flex cable assembly for use in a disc drive data storage device includes a laminated flex cable and a flex cable support. The flex cable provides electrical communication paths between a moveable head stack assembly and a disc drive printed circuit board. The flex cable support comprises a base and adjacent first and second flex support portions with respective first and second flex support surfaces. The flex cable is routed along the flex support surfaces and exerts a spring force thereagainst as the flex cable attempts to return to a nominally planar orientation. The direction of the second flex support surface establishes the orientation of a dynamic loop between the flex cable support and the head stack assembly. Preferably, a portion of the flex cable pulls away from the second flex support surface to lengthen the dynamic loop in response to movement of the head stack assembly.

Abstract: A DRAM memory cell is provided with a selection transistor, which is arranged horizontally at a semiconductor substrate surface and has a first source/drain electrode, a second source/drain electrode, a channel layer arranged between the first and the second source/drain electrode in the semiconductor substrate, and a gate electrode, which is arranged along the channel layer and is electrically insulated from the channel layer, a storage capacitor, which has a first capacitor electrode and a second capacitor electrode, insulated from the first capacitor electrode, one of the capacitor electrodes of the storage capacitor being electrically conductively connected to one of the source/drain electrodes of the selection transistor, and a semiconductor substrate electrode on the rear side, the gate electrode enclosing the channel layer at at least two opposite sides.

Abstract: An electrical feedthrough is provided to establish an electrical conduction path from an interior of a hermetically sealed housing to an exterior environment. The feedthrough comprises an elongated electrically conductive pin having opposing proximal and distal ends and a medial portion configured to be supported within a corresponding aperture in a first housing member. A first cantilevered spring contact is affixed to and projects from a selected one of the proximal and distal ends of the pin. Preferably, a second cantilevered spring contact is further affixed to and projects from the remaining one of the proximal and distal ends of the pin. A plurality of feedthroughs are preferably affixed through an insertion member to form a feedthrough assembly which is then affixed adjacent an aperture in the first housing member. An insulating member in the plate preferably supports and isolates a pair of the pins to transmit a differential signal.