Abstract: A nanotube array and a method for producing a nanotube array. The nanotube array has a substrate, a catalyst layer, which includes one or more subregions, on the surface of the substrate and at least one nanotube arranged on the surface of the catalyst layer, parallel to the surface of the substrate. The at least one nanotube being arranged parallel to the surface of the substrate results in a planar arrangement of at least one nanotube. Therefore, the nanotube array of the invention is suitable for coupling to conventional silicon microelectronics. Therefore, according to the invention it is possible for a nanotube array to be electronically coupled to macroscopic semiconductor electronics. Furthermore, the nanotube array according to the invention may have an electrically insulating layer between the substrate and the catalyst layer.

Abstract: The invention relates to a molecular electronics arrangement comprising a substrate, at least one first strip conductor having a surface and being arranged in or on the substrate, a spacer which is arranged on the surface of the at least one first strip conductor and which partially covers the surface of the at least one first strip conductor, and at least one second strip conductor which is arranged on the spacer and comprises a surface which faces the surface of the at least one first strip conductor in a plane manner. The spacer partially covers the surface of the at least one second strip conductor, and defines a pre-determined distance between the at least one first strip conductor and the at least one second strip conductor.

Abstract: The invention provides a very compact, yet reliable heterostructure and method of manufacture thereof. The invention provides a heterostructure component, and method of manufacture, having a single hetero-nanotube, which includes: a first region made from a first nanotube material with a first value for the bandgap, and a second region made from a second nanotube material having a second value for the bandgap, which is different from the first value for the bandgap. The second region is arranged at the upper end of the first region in the longitudinal direction of the hetero-nanotube. The first nanotube material is a different material than the second nanotube material.

Abstract: A hermetically sealed housing such as for use in a data storage device. Opposing first and second housing members are coupled together with respective interior surfaces in facing relationship to form a hermetically sealed interior environment. An internally mounted shaft includes a medial portion about which a rotatable article rotates, a proximal end internally supported by the first housing member, and a distal end internally supported by the second housing member. In some embodiments, at least one of the proximal and distal ends fits into a corresponding recess formed in the respective housing member. In other embodiments, at least one of the proximal and distal ends includes a cup-shaped recess which accommodates a pin that projects from the respective housing member. Layers of compliant material are preferably provided at the interfaces between the ends of the shaft and the respective housing members.

Abstract: A hermetically sealed housing such as for use in a data storage device. The housing is formed from a pair of opposing, substantially planar first and second housing members. A gasket seal is compressed between the housing members to form a hermetic seal. A compression limit spacer limits the compression of the gasket seal to a predetermined compression level. Preferably, the gasket seal is nested within and is contactingly supported by the compression limit spacer. A plurality of fasteners secure the first and second housing members and apply a compressive force to the gasket seal. The compression limit spacer preferably comprises a plurality of discrete, spaced apart bosses through which the plurality of fasteners extend. The gasket seal preferably has a hexagonal or a c-shaped cross-sectional shape. An inert fluidic atmosphere is preferably retained within the housing.

Abstract: A memory element with organic material comprises two metallized layers, arranged one on top of the other, with first lines and second lines which are arranged to intersect with each other. A channel is formed at the intersections between the first line and the second line, which overlaps the first line partially and completely overlaps the second line. The channels are filled with a filling material, the electrical conductivity of which may be altered by an applied electrical voltage.

Abstract: The bar-type field effect transistor consists of a substrate, a bar placed above a substrate and a gate and spacer placed above part of the bar.

Abstract: A memory element with organic material comprises two metallised layers, arranged one on top of the other, with first lines and second lines which are arranged to intersect with each other. A channel is formed at the intersections between the first line and the second line, which overlaps the first line partially and completely overlaps the second line. The channels are filled with a filling material, the electrical conductivity of which may be altered by an applied electrical voltage.

Abstract: A nonvolatile semiconductor memory cell includes a transistor component formed on a substrate and a storage node that determines the switching state of the transistor component. The storage node is arranged near a control gate electrode. The storage node has a group of vertically oriented column structures having at least two semiconductor layer zones and an insulating layer zone situated between the two semiconductor layer zones.

Abstract: A flex cable assembly for use in a disc drive data storage device includes a laminated flex cable and a flex cable support. The flex cable provides electrical communication paths between a moveable head stack assembly and a disc drive printed circuit board. The flex cable support comprises a base and adjacent first and second flex support portions with respective first and second flex support surfaces. The flex cable is routed along the flex support surfaces and exerts a spring force thereagainst as the flex cable attempts to return to a nominally planar orientation. The direction of the second flex support surface establishes the orientation of a dynamic loop between the flex cable support and the head stack assembly. Preferably, a portion of the flex cable pulls away from the second flex support surface to lengthen the dynamic loop in response to movement of the head stack assembly.

Abstract: A floating gate field-effect transistor (400), which is preferably used as a memory cell, has, above or below a floating gate region (407), an electrically insulating layer sequence (408) having a lower layer (409) having a first relative permittivity, having a middle layer (410) having a second relative permittivity, and having an upper layer (411) having a third relative permittivity, the second relative permittivity being greater than the first relative permittivity and greater than the third relative permittivity.

Abstract: The invention relates to a layer arrangement, a memory cell, a memory cell arrangement and a method for producing a layer arrangement. The layer arrangement has a monocrystalline substrate, a highly doped region in the substrate and a metallically conductive structure in the highly doped region, a partial region of the highly doped region that is arranged in a surface region of the substrate being monocrystalline.

Abstract: In an integrated optoelectronic microelectronic system, an optoelectronically active diode part is formed in a semiconductor substrate by zones forming depletion layers. The system is provided in a mesa that stands vertically on a semiconductor substrate and runs in a direction of extension thereof. A light waveguide is optically coupled to the diode part in such a way that light is coupled into the diode part via the mesa side wall.

Abstract: A memory cell configuration has word lines and bit lines that extend transversely with respect thereto. Memory elements with a giant magnetoresistive effect are respectively connected between one of the word lines and one of the bit lines. The bit lines are each connected to a sense amplifier by means of which the potential on the respective bit line can be regulated to a reference potential and at which an output signal can be picked off. The memory cell configuration can be used both as an MRAM and as an associative memory.

Abstract: A nonvolatile semiconductor memory cell includes a transistor component formed on a substrate and a storage node that determines the switching state of the transistor component. The storage node is arranged near a control gate electrode. The storage node has a group of vertically oriented column structures having at least two semiconductor layer zones and an insulating layer zone situated between the two semiconductor layer zones.

Abstract: A vertical semiconductor transistor component is built up on a substrate by using a statistical mask. The vertical semiconductor transistor component has vertical pillar structures statistically distributed over the substrate. The vertical pillar structures are electrically connected on a base side thereof to a first common electrical contact. The vertical pillar structures include, along the vertical direction, layer zones of differing conductivity, and have insulation layers on their circumferential walls. An electrically conductive material is deposited between the pillar structures and forms a second electrical contact of the semiconductor transistor component. The pillar structures are electrically contacted to a third common electrical contact on their capping side.

Abstract: At least one CMOS component which is configured in a semiconductor substrate is part of the inventive circuit assembly. An insulating layer is configured on the semiconductor substrate. The insulating layer covers the CMOS component. A nanoelectronic component is configured above the insulating layer. At least one conducting structure is configured in the insulating layer and serves to link the nanoelectronic component with the CMOS component. If several nanoelectronic components are provided, they are preferably grouped to nano-circuit blocks. Each of the nano-circuit blocks is so small that the RC times of their lines do not exceed 1 ns.

Abstract: In an integrated optoelectronic microelectronic system, an optoelectronically active diode part is formed in a semiconductor substrate by zones forming depletion layers. The system is provided in a mesa that stands vertically on a semiconductor substrate and runs in a direction of extension thereof. A light waveguide is optically coupled to the diode part in such a way that light is coupled into the diode part via the mesa side wall.

Abstract: A read/write architecture for a MRAM is described. The read/write architecture uses resistance bridges during the read process, whereby a memory cell in the resistance bridges having a known state of magnetization is compared with a memory cell that is to be measured.

Abstract: Resistors are connected between word lines and bit lines running transversely with respect thereto. The resistors have a higher resistance than the word lines and the bit lines. The bit lines are each connected to a sense amplifier which regulates the potential on the respective bit line to a reference potential and at which an output signal can be picked off. If one of the word lines is selected and all the other word lines are put at reference potential, then the resistance of the resistor, which is assigned to an information item, can be read from the output signal.