Abstract: The present disclosure relates to interface structures and, more particularly, to integrated interface structures with both parallel and serial interfaces and methods of manufacture. The integrated interface structure includes: a substrate; a plurality of serial interface connections integrated on the substrate; and a plurality of parallel interface connections on the integrated substrate and within spaces between sets of the plurality of serial interface connections.

Abstract: The disclosure relates to semiconductor structures and, more particularly, to barrier structures for underfill blockout regions uses in phonotics chip packaging and methods of manufacture. The structure includes a substrate with a plurality of solder connections and at least one optical fiber interface disposed within at least one cavity of the substrate. The structure further includes a barrier structure formed about the cavity which is structured to prevent underfill material from degrading an optical coupling of the optical fiber.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to photonics chips and methods of manufacture. A structure includes: a photonics chip having a grated optical coupler; an interposer attached to the photonics chip, the interposer having a grated optical coupler; an optical epoxy material provided between the grated optical coupler of the photonics chip and the grated optical coupler of the interposer; and epoxy underfill material provided at interstitial regions between the photonics chip and the interposer which lie outside of an area of the grated optical couplers of the photonics chip and the interposer.

Abstract: A method forming an interconnect structure includes depositing a first solder bump on a chip; depositing a second solder bump on a laminate, the second solder bump including a nickel copper colloid surrounded by a nickel or copper shell and suspended in a tin-based solder; aligning the chip with the laminate; performing a first reflow process to join the chip to the laminate; depositing an underfill material around the first solder bump and the second solder bump; and performing a second reflow process at a temperature that is lower than the first reflow process to convert the first solder bump and the second solder bump to an all intermetallic interconnect; wherein depositing the underfill material is performed before or after performing the second reflow process.

Abstract: A method forming an interconnect structure includes depositing a first solder bump on a chip; depositing a second solder bump on a laminate, the second solder bump including a nickel copper colloid surrounded by a nickel or copper shell and suspended in a tin-based solder; aligning the chip with the laminate; performing a first reflow process to join the chip to the laminate; depositing an underfill material around the first solder bump and the second solder bump; and performing a second reflow process at a temperature that is lower than the first reflow process to convert the first solder bump and the second solder bump to an all intermetallic interconnect; wherein depositing the underfill material is performed before or after performing the second reflow process.

Abstract: An embodiment of the invention may include a semiconductor structure, and method of forming the semiconductor structure. The semiconductor structure may include a first set of pillars located on a first substrate. The semiconductor structure may include a second set of pillars located on a second substrate. The semiconductor structure may include a joining layer connecting the first pillar to the second pillar. The semiconductor structure may include an underfill layer located between the first and second substrate.

Abstract: A method forming an interconnect structure includes depositing a first solder bump on a chip; depositing a second solder bump on a laminate, the second solder bump including a nickel copper colloid surrounded by a nickel or copper shell and suspended in a tin-based solder; aligning the chip with the laminate; performing a first reflow process to join the chip to the laminate; depositing an underfill material around the first solder bump and the second solder bump; and performing a second reflow process at a temperature that is lower than the first reflow process to convert the first solder bump and the second solder bump to an all intermetallic interconnect; wherein depositing the underfill material is performed before or after performing the second reflow process.

Abstract: An embodiment of the invention may include a semiconductor structure, and method of forming the semiconductor structure. The semiconductor structure may include a first set of pillars located on a first substrate. The semiconductor structure may include a second set of pillars located on a second substrate. The semiconductor structure may include a joining layer connecting the first pillar to the second pillar. The semiconductor structure may include an underfill layer located between the first and second substrate.

Abstract: An embodiment of the invention may include a semiconductor structure, and method of forming the semiconductor structure. The semiconductor structure may include a first set of pillars located on a first substrate. The semiconductor structure may include a second set of pillars located on a second substrate. The semiconductor structure may include a joining layer connecting the first pillar to the second pillar. The semiconductor structure may include an underfill layer located between the first and second substrate.

Abstract: An embodiment of the invention may include a semiconductor structure, and method of forming the semiconductor structure. The semiconductor structure may include a first set of pillars located on a first substrate. The semiconductor structure may include a second set of pillars located on a second substrate. The semiconductor structure may include a joining layer connecting the first pillar to the second pillar. The semiconductor structure may include an underfill layer located between the first and second substrate.

Abstract: Various embodiments include methods of forming interconnect structures, and the structures formed by such methods. In one embodiment, an interconnect structure can include: a photosensitive polyimide (PSPI) layer including a pedestal portion; a controlled collapse chip connection (C4) bump overlying the pedestal portion of the PSPI layer; a solder overlying the C4 bump and contacting a side of the C4 bump; and an underfill layer abutting the pedestal portion of the PSPI and the C4 bump, wherein the underfill layer and the solder form a first interface separated from the PSPI pedestal.

Abstract: A multi-chip module, and method of fabricating the multi-chip module. The multi-chip module includes: a substrate containing multiple wiring layers, each wiring layer having first pads on a top surface of the substrate and second pads on a bottom surface of the substrate, wherein the second pads include split pad and a conventional pad; a first solder ball in direct physical contact with a contiguous bottom surface of the conventional pad and connected to a next level of packaging under the conventional pad, wherein the first solder ball has a first height; and a second solder ball in direct physical contact with first and second sections of the split pad separated by a gap, wherein the second solder ball has a second height that is sufficiently less than the first height such that the second solder ball is not connected to the next level of packaging.

Abstract: The disclosure relates to semiconductor structures and, more particularly, to barrier structures for underfill blockout regions uses in phonotics chip packaging and methods of manufacture. The structure includes a substrate with a plurality of solder connections and at least one optical fiber interface disposed within at least one cavity of the substrate. The structure further includes a barrier structure formed about the cavity which is structured to prevent underfill material from degrading an optical coupling of the optical fiber.

Abstract: A method of fabricating a pillar-type connection includes forming, on a bond pad, a first conductive layer including a hollow core. A second conductive layer is formed on a first conductive layer to define a conductive pillar that includes a non-planar top surface defining a recess aligned with the hollow core.

Abstract: Solder bump connections and methods for fabricating solder bump connections. A passivation layer is formed on a dielectric layer. Via openings extend through the passivation layer from a top surface of the passivation layer to a metal line in the passivation layer. A conductive layer is formed on the top surface of the passivation layer and within each via opening. When the passivation layer and the conductive layer are planarized, a plug is formed that includes sections in the via openings. Each section is coupled with the metal line.

Abstract: A multi-chip module and method of fabricating a multi-chip module. The multi-chip module includes: a substrate having a top surface and a bottom surface and containing multiple wiring layers, first pads on the top surface of the substrate and second pads on the bottom surface of the substrate; a first active component attached to a first group of the first pads and a second active component attached to a second group of the first pads; wherein at least one pad of the second pads is a split pad having a first section and a non-contiguous second section separated by a gap, the first section connected by a first wire of the multiple wires to a pad of the first group of first pads and the second section is connected by a second wire of the multiple wires to a pad of the second group of first pads.

Abstract: A spacer structure formed adjacent a solder connection which prevents solder extrusion and methods of manufacture are disclosed. The method includes forming a solder preform connection on a bond pad of a chip. The method further includes forming a spacer structure on sidewalls of the solder preform connection. The method further includes subjecting the solder preform connection to a predetermined temperature to form a solder connection with the spacer structure remaining thereabout.

Abstract: Various embodiments include methods of forming interconnect structures, and the structures formed by such methods. In one embodiment, a method can include: providing a precursor interconnect structure having: a photosensitive polyimide (PSPI) layer; a controlled collapse chip connection (C4) bump overlying the PSPI layer; and a solder overlying the C4 bump and contacting a side of the C4 bump. The method can further include recessing a portion of the PSPI layer adjacent to the C4 bump to form a PSPI pedestal under the C4 bump. The method can additionally include forming an underfill abutting the PSPI pedestal and the C4 bump, wherein the underfill and the solder form an interface separated from the PSPI pedestal.

Abstract: A multi-chip module and method of fabricating a multi-chip module. The multi-chip module includes: a substrate having a top surface and a bottom surface and containing multiple wiring layers, first pads on the top surface of the substrate and second pads on the bottom surface of the substrate; a first active component attached to a first group of the first pads and a second active component attached to a second group of the first pads; wherein at least one pad of the second pads is a split pad having a first section and a non-contiguous second section separated by a gap, the first section connected by a first wire of the multiple wires to a pad of the first group of first pads and the second section is connected by a second wire of the multiple wires to a pad of the second group of first pads.

Abstract: Pillar-type connections and methods for fabricating a pillar-type connection. A conductive layer is formed on a bond pad. A second conductive layer is formed on the first conductive layer to define a conductive pillar. The conductive pillar includes a non-planar top surface defining a recess. The recess may receive a portion of a solder body used to connect the conductive pillar with a package.