Patents by Inventor Wolfgang Sauter

Wolfgang Sauter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • CONTACT AND SOLDER BALL INTERCONNECT
    Publication number: 20150311170
    Abstract: A semiconductor device fabrication method includes forming a barrier layer upon a dielectric layer, forming a pillar interconnect structure upon the barrier layer, forming solder upon the pillar interconnect structure, reflowing the solder to release solder voids, forming a perimeter material around at least a portion of an exposed sidewall of the pillar, and removing the barrier layer exterior to the pillar interconnect structure. Another fabrication method includes forming the barrier layer, forming the pillar interconnect structure, forming the solder upon the pillar interconnect structure, forming a perimeter material on exposed surfaces of the pillar interconnect structure, and removing the barrier layer on the surface of the dielectric layer exterior to the pillar interconnect structure.
    Type: Application
    Filed: April 24, 2014
    Publication date: October 29, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles L. Arvin, Eric D. Perfecto, Wolfgang Sauter
  • Compensating for warpage of a flip chip package by varying heights of a redistribution layer on an integrated circuit chip
    Patent number: 9165850
    Abstract: Structures and methods of making a flip chip package that employ polyimide pads of varying heights at a radial distance from a center of an integrated circuit (IC) chip for a flip chip package. The polyimide pads may be formed under electrical connectors, which connect the IC chip to a chip carrier of the flip chip package, so that electrical connectors formed on polyimide pads of greater height are disposed at a greater radial distance from the center of the IC chip, while electrical connectors formed on polyimide pads of a lesser height are disposed more proximately to the center of the IC chip. Electrical connectors of a greater relative height to the IC chip's surface may compensate for a gap, produced by heat-induced warpage during the making of the flip chip package, that separates the electrical connectors on the IC chip from flip chip attaches on the chip carrier.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: October 20, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Christopher D. Muzzy, Wolfgang Sauter, Timothy D. Sullivan
  • Dice before grind with backside metal
    Patent number: 9165831
    Abstract: A method including forming a plurality of dicing channels in a front side of a wafer; the plurality of dicing channels including a depth at least greater than a desired final thickness of the wafer, filling the plurality of dicing channels with a fill material and removing a portion of the wafer from a back side of the wafer until the desired final thickness is achieved, where a portion of the fill material within the plurality of dicing channel is exposed. The method further including depositing a metal layer on the back side of the wafer; removing the fill material from within the plurality of dicing channels to expose the metal layer at a bottom of the plurality of dicing channels, and removing a portion of the metal layer located at the bottom of the plurality of dicing channels.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: October 20, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Charles F. Musante, Christopher D. Muzzy, Wolfgang Sauter, Timothy D. Sullivan
  • Plug via formation by patterned plating and polishing
    Patent number: 9159696
    Abstract: Solder bump connections and methods for fabricating solder bump connections. A passivation layer is formed on a dielectric layer. A via opening extends through the passivation layer from a top surface of the passivation layer to a metal line in the dielectric layer. A mask on the top surface of the passivation layer includes a mask opening that is aligned with the via opening. A conductive layer is selectively formed in the via opening and the mask opening. The conductive layer projects above the top surface of the passivation layer. The method further includes planarizing the passivation layer and the conductive layer to define a plug in the via opening that is coupled with the metal line.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: October 13, 2015
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Ekta Misra, Christopher D. Muzzy, Wolfgang Sauter
  • Under ball metallurgy (UBM) for improved electromigration
    Patent number: 9142501
    Abstract: An interconnect structure that includes a substrate having an electrical component present therein, and a under-bump metallurgy (UBM) stack that is present in contact with a contact pad to the electrical component that is present in the substrate. The UBM stack includes a metallic adhesion layer that is direct contact with the contact pad to the electrical component, a copper (Cu) seed layer that is in direct contact with the metallic adhesion layer layer, a first nickel (Ni) barrier layer that is present in direct contact with copper (Cu) seed layer, and a layered structure of at least one copper (Cu) conductor layer and at least one second nickel (Ni) barrier layer present on the first nickel (Ni) barrier layer. A solder ball may be present on second nickel (Ni) barrier layer.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: September 22, 2015
    Assignee: International Business Machines Corporation
    Inventors: Charles L. Arvin, Minhua Lu, Eric D. Perfecto, David J. Russell, Wolfgang Sauter, Krystyna Semkow, Thomas A. Wassick
  • Wafer edge conditioning for thinned wafers
    Patent number: 9105465
    Abstract: The present invention relates to a method for minimizing breakage of wafers during or after a wafer thinning process. A method of forming a rounded edge to the portion of a wafer remaining after surface grinding process is provided. The method comprises providing a semiconductor wafer having an edge and forming a recess in the edge of the wafer using any suitable mechanical or chemical process. The method further comprises forming a substantially continuous curved shape for at least the edge of the wafer located above the recess. Advantageously, the shape of the wafer is formed prior to the backside grind process to prevent problems caused by the otherwise presence of a sharp edge during the backside grind process.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: August 11, 2015
    Assignee: International Business Machines Corporation
    Inventors: Timothy Harrison Daubenspeck, Jeffrey P. Gambino, Christopher David Muzzy, Wolfgang Sauter, Timothy Dooling Sullivan
  • Structures and methods for improving solder bump connections in semiconductor devices
    Patent number: 9087754
    Abstract: Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The structure includes a via formed in a dielectric layer to expose a contact pad and a capture pad formed in the via and over the dielectric layer. The capture pad has openings over the dielectric layer to form segmented features. The solder bump is deposited on the capture pad and the openings over the dielectric layer.
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: July 21, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Christopher D. Muzzy, Wolfgang Sauter, Timothy D. Sullivan
  • SURGICAL PROTECTIVE DEVICE FOR A SURGICAL SEALING ELEMENT AND SURGICAL SEALING SYSTEM
    Publication number: 20150196322
    Abstract: The invention relates to a surgical protective device for a surgical sealing element of a surgical sealing system comprising a trocar sleeve, the surgical sealing element having an expandable insertion opening. Said protective device comprises a ring-shaped or substantially ring-shaped main body adapted to be arranged on the trocar sleeve, on a part thereof or on the sealing element and defines a through-opening with a plurality of protective elements arranged in the circumferential direction and extending parallel to or pointing towards a longitudinal axis of the protective device. Each of the protective elements is configured asymmetrically in relation to a plane containing a longitudinal axis defined by the main body.
    Type: Application
    Filed: March 13, 2015
    Publication date: July 16, 2015
    Inventor: Wolfgang Sauter
  • MEDICAL INSERTION AID COMPRISING DRAWN INSERTION DUCT
    Publication number: 20150164547
    Abstract: A medical insertion aid for surgical instruments and/or optical systems includes a shank forming an insertion duct, at the inner wall of which at least one groove extending in the longitudinal duct direction or being longitudinally orientated is formed. In addition or as an alternative, a medical insertion aid includes a distal end portion (axial central portion preferably in the distal end area) and a radially outwardly extending, preferably closed peripheral fluid flow inhibiting edge in the distal end portion. The inhibiting edge preferably forms at least one axially opening circular channel or groove, with the opening being directed distally and/or proximally.
    Type: Application
    Filed: July 10, 2013
    Publication date: June 18, 2015
    Inventors: Wolfgang Sauter, Manfred Dworschak, Axel Wittmer
  • Thermally-optimized metal fill for stacked chip systems
    Patent number: 9058460
    Abstract: Stacked chip systems and design structures for stacked chip systems, as well as methods and computer program products for placing thermal conduction paths in a stacked chip system. The method may include determining an availability of space in a layout of an interconnect structure of a first chip for a fill shape structure extending partially through the interconnect structure to thermally couple a metal feature in the interconnect structure with a bonding layer between the interconnect structure of the first chip and a second chip. If space is available, the fill shape structure may be placed in the layout of the interconnect structure of the first chip. The stacked chip system may include the first and second chips, the bonding layer between the interconnect structure of the first chip and the second chip, and the fill shape structure.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: June 16, 2015
    Assignee: International Business Machines Corporation
    Inventors: Douglas M. Daley, Wolfgang Sauter, Hung H. Tran, Wayne H. Woods, Ze Zhang
  • Compensating for warpage of a flip chip package by varying heights of a redistribution layer on an integrated circuit chip
    Patent number: 9059106
    Abstract: Structures and methods of making a flip chip package that employ polyimide pads of varying heights at a radial distance from a center of an integrated circuit (IC) chip for a flip chip package. The polyimide pads may be formed under electrical connectors, which connect the IC chip to a chip carrier of the flip chip package, so that electrical connectors formed on polyimide pads of greater height are disposed at a greater radial distance from the center of the IC chip, while electrical connectors formed on polyimide pads of a lesser height are disposed more proximately to the center of the IC chip. Electrical connectors of a greater relative height to the IC chip's surface may compensate for a gap, produced by heat-induced warpage during the making of the flip chip package, that separates the electrical connectors on the IC chip from flip chip attaches on the chip carrier.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: June 16, 2015
    Assignee: International Business Machines Corporation
    Inventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Christopher D. Muzzy, Wolfgang Sauter, Timothy D. Sullivan
  • Releasable buried layer for 3-D fabrication and methods of manufacturing
    Patent number: 9040390
    Abstract: A releasable buried layer for 3-D fabrication and methods of manufacturing is disclosed. The method includes forming an interposer structure which includes forming a carbon rich dielectric releasable layer over a wafer. The method further includes forming back end of the line (BEOL) layers over the carbon rich dielectric layer, including wiring layers and solder bumps. The method further includes bonding the solder bumps to a substrate using flip chip processes. The flip chip processes comprises reflowing the solder bumps and rapidly cooling down the solder bumps which releases the carbon rich dielectric releasable layer from the wafer.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: May 26, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Timothy H. Daubenspeck, Steven E. Molis, Gordon C. Osborne, Jr., Wolfgang Sauter, Edmund J. Sprogis
  • Solder interconnect with non-wettable sidewall pillars and methods of manufacture
    Patent number: 9018760
    Abstract: A solder interconnect structure is provided with non-wettable sidewalls and methods of manufacturing the same. The method includes forming a nickel or nickel alloy pillar on an underlying surface. The method further includes modifying the sidewall of the nickel or nickel alloy pillar to prevent solder wetting on the sidewall.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: April 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Charles L. Arvin, Raschid J. Bezama, Timothy H. Daubenspeck, Jeffrey P. Gambino, Christopher D. Muzzy, David L. Questad, Wolfgang Sauter, Timothy D. Sullivan, Brian R. Sundlof
  • INTEGRATED CRACKSTOP
    Publication number: 20150108645
    Abstract: A method including forming a first dielectric layer above a conductive pad and above a metallic structure, the conductive pad and the metallic structure are each located within an interconnect level above a substrate, forming a first opening and a second opening in the first dielectric layer, the first opening is aligned with and exposes the conductive pad and the second opening is aligned with and exposes the metallic structure, and forming a metallic liner on the conductive pad, on the metallic structure, and above the first dielectric layer. The method may further include forming a second dielectric layer above the metallic liner, and forming a third dielectric layer above the second dielectric layer, the third dielectric layer is thicker than either the first dielectric layer or the second dielectric layer.
    Type: Application
    Filed: October 22, 2013
    Publication date: April 23, 2015
    Applicant: International Business Machines Corporation
    Inventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Christopher D. Muzzy, Wolfgang Sauter
  • STRUCTURE TO PREVENT SOLDER EXTRUSION
    Publication number: 20150108642
    Abstract: A spacer structure formed adjacent a solder connection which prevents solder extrusion and methods of manufacture are disclosed. The method includes forming a solder preform connection on a bond pad of a chip. The method further includes forming a spacer structure on sidewalls of the solder preform connection. The method further includes subjecting the solder preform connection to a predetermined temperature to form a solder connection with the spacer structure remaining thereabout.
    Type: Application
    Filed: October 18, 2013
    Publication date: April 23, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Christopher D. Muzzy, Wolfgang Sauter, Timothy D. Sullivan
  • PLUG VIA FORMATION WITH GRID FEATURES IN THE PASSIVATION LAYER
    Publication number: 20150097283
    Abstract: Solder bump connections and methods for fabricating solder bump connections. A passivation layer is formed on a dielectric layer. Via openings extend through the passivation layer from a top surface of the passivation layer to a metal line in the passivation layer. A conductive layer is formed on the top surface of the passivation layer and within each via opening. When the passivation layer and the conductive layer are planarized, a plug is formed that includes sections in the via openings. Each section is coupled with the metal line.
    Type: Application
    Filed: October 8, 2013
    Publication date: April 9, 2015
    Applicant: International Business Machines Corporation
    Inventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Ekta Misra, Christopher D. Muzzy, Wolfgang Sauter
  • Structure, semiconductor structure and method of manufacturing a semiconductor structure and packaging thereof
    Patent number: 9000585
    Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a dielectric material formed between a design sensitive structure and a passivation layer. The design sensitive structure comprising a lower wiring layer electrically and mechanically connected to a higher wiring level by a via farm. A method and structure is also provided.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: April 7, 2015
    Assignee: International Business Machines Corporation
    Inventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Christopher D. Muzzy, Wolfgang Sauter, Jeffrey S. Zimmerman
  • Solder bump connection and method of making
    Patent number: 8994173
    Abstract: A layer of material can protect a surface of a passivation layer against damage during a final via plug process. The protective layer can be a conductive bump limiting metallurgy (BLM) base layer and can include titanium tungsten (TiW), though other materials can be employed. Examples include applying the protective layer after formation of a via opening and prior to formation of a via opening, and can include applying more protective material after conductor plug formation to enhance protection. Photosensitive and non-photosensitive passivation layers can be so protected.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: March 31, 2015
    Assignee: International Business Machines Corporation
    Inventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Christopher D. Muzzy, Wolfgang Sauter
  • PLUG VIA FORMATION BY PATTERNED PLATING AND POLISHING
    Publication number: 20150076688
    Abstract: Solder bump connections and methods for fabricating solder bump connections. A passivation layer is formed on a dielectric layer. A via opening extends through the passivation layer from a top surface of the passivation layer to a metal line in the dielectric layer. A mask on the top surface of the passivation layer includes a mask opening that is aligned with the via opening. A conductive layer is selectively formed in the via opening and the mask opening. The conductive layer projects above the top surface of the passivation layer. The method further includes planarizing the passivation layer and the conductive layer to define a plug in the via opening that is coupled with the metal line.
    Type: Application
    Filed: September 13, 2013
    Publication date: March 19, 2015
    Applicant: International Business Machines Corporation
    Inventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Ekta Misra, Christopher D. Muzzy, Wolfgang Sauter
  • PREVENTING MISSHAPED SOLDER BALLS
    Publication number: 20150048502
    Abstract: “Thick line dies” that, during manufacture, avoid locating an upstanding edge of a photoresist layer (for example, the edge of a dry film photoresist layer) on top of a “discontinuity.” In this way solder does not flow into the mechanical interface between the photoresist layer and the layer under the photoresist layer in the vicinity of an upstanding edge of the photoresist layer.
    Type: Application
    Filed: August 14, 2013
    Publication date: February 19, 2015
    Applicant: International Business Machines Corporation
    Inventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Christopher D. Muzzy, Wolfgang Sauter, Timothy D. Sullivan