Patents by Inventor Won Seok Cho

Won Seok Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11973035
    Abstract: A semiconductor memory device includes a first substrate including a first region and a second region, a stacked structure only on the first region of the first substrate among the first region and the second region of the first substrate, the stacked structure including word lines, an interlayer insulating film covering the stacked structure, a dummy conductive structure inside the interlayer insulating film, the dummy conductive structure extending through the stacked structure to contact the first substrate, and a plate contact plug inside the interlayer insulating film, the plate contact plug being connected to the second region of the first substrate, and a height of an upper surface of the dummy conductive structure being greater than a height of an upper surface of the plate contact plug relative to an upper surface of the first substrate.
    Type: Grant
    Filed: April 18, 2023
    Date of Patent: April 30, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ha-Min Hwang, Jong Soo Kim, Ju-Young Lim, Won Seok Cho
  • Publication number: 20240133519
    Abstract: A liquefied gas storage tank includes a corner block disposed on a corner portion, wherein the corner block includes a lower block, an upper block and an upper connecting block, the upper block includes a first inner fixing unit and a second inner fixing unit respectively provided inside a first surface and a second surface, bonded and connected to a secondary barrier, and each having a structure in which a primary inner plywood, a primary corner insulating material, and a primary outer plywood are stacked, and an inner bent portion installed at a corner spatial portion between the first inner fixing unit and the second inner fixing unit, and both side surfaces of the inner bent portion that are perpendicular to the secondary barrier each have a height reduced from a total height of each of the first and second inner fixing units.
    Type: Application
    Filed: December 14, 2021
    Publication date: April 25, 2024
    Inventors: Won Seok HEO, Seong Bo PARK, Hye Min CHO, Ki Joong KIM, Cheon Jin PARK, Min Kyu PARK, Jung Kyu PARK, Byeong Jin JEONG, Dong Woo KIM, Sung Kyu HONG, Gwang Soo GO, Jee Yeon HEO
  • Patent number: 11967076
    Abstract: A computing device includes at least one memory, and at least one processor configured to generate, based on first analysis on a pathological slide image, first biomarker expression information, generate, based on a user input for updating at least some of results of the first analysis, second biomarker expression information about the pathological slide image, and control a display device to output a report including medical information about at least some regions included in the pathological slide image, based on at least one of the first biomarker expression information or the second biomarker expression information.
    Type: Grant
    Filed: March 17, 2023
    Date of Patent: April 23, 2024
    Assignee: LUNIT INC.
    Inventors: Jeong Seok Kang, Dong Geun Yoo, Soo Ick Cho, Won Kyung Jung
  • Publication number: 20240090805
    Abstract: According to one embodiment, a method by which a device provides a service so as to enable cognitive function rehabilitation by using a virtual object model comprises the steps of: generating a virtual object model in a virtual space matched to correspond to a real space where a subject is located; generating a plurality of first preliminary stimuli for identifying egocentric neglect in the visual range of the subject on the basis of the virtual object model; obtaining and collecting first reaction information about whether the subject has recognized the first preliminary stimuli; determining an egocentric cognition range in which the subject can egocentrically recognize visual stimuli on the basis of the first reaction information; sequentially generating a plurality of second preliminary stimuli for identifying allocentric neglect in the egocentric cognition range on the basis of the virtual object model; obtaining and collecting second reaction information about whether the subject has recognized the secon
    Type: Application
    Filed: November 5, 2021
    Publication date: March 21, 2024
    Inventors: Sung Min CHO, Won Seok KIM, Jung Taek PARK, Young Hoo CHO
  • Publication number: 20240084969
    Abstract: The liquefied gas storage tank includes a primary barrier, a primary insulation wall, a secondary barrier, and a secondary insulation wall. In a state where unit elements are arranged adjacent to each other, each of the unit elements being formed by stacking the secondary insulation wall, the secondary barrier, and a fixed insulation wall which is a part of the primary insulation wall, the primary insulation wall may comprise: a connection insulation wall provided in the space between the adjacent fixed insulation walls; first slits formed between the fixed insulation walls and the connection insulation wall when the connection insulation wall is inserted and installed between the adjacent fixed insulation walls; a plurality of second slits formed in a lengthwise direction and a widthwise direction of the fixed insulation walls; and a first insulating filler material for filling the first slits.
    Type: Application
    Filed: December 15, 2021
    Publication date: March 14, 2024
    Inventors: Seong Bo PARK, Won Seok HEO, Hye Min CHO, Ki Joong KIM, Cheon Jin PARK, Min Kyu PARK, Jung Kyu PARK, Byeong Jin JEONG, Dong Woo KIM, Sung Kyu HONG, Gwang Soo GO, Jee Yeon HEO
  • Publication number: 20230253329
    Abstract: A semiconductor memory device includes a first substrate including a first region and a second region, a stacked structure only on the first region of the first substrate among the first region and the second region of the first substrate, the stacked structure including word lines, an interlayer insulating film covering the stacked structure, a dummy conductive structure inside the interlayer insulating film, the dummy conductive structure extending through the stacked structure to contact the first substrate, and a plate contact plug inside the interlayer insulating film, the plate contact plug being connected to the second region of the first substrate, and a height of an upper surface of the dummy conductive structure being greater than a height of an upper surface of the plate contact plug relative to an upper surface of the first substrate.
    Type: Application
    Filed: April 18, 2023
    Publication date: August 10, 2023
    Inventors: Ha-Min HWANG, Jong Soo KIM, Ju-Young LIM, Won Seok CHO
  • Publication number: 20230152214
    Abstract: Provided is a method of evaluating electrode quality capable of simply and quickly filtering out defective electrodes by measuring a color coordinate value of electrodes before roll-pressing, which specifically includes: providing an electrode which includes a current collector and an active material layer formed on the current collector and has not been roll-pressed; measuring a color coordinate value of the active material layer using an optical instrument; and evaluating the electrode as a good product when the measured color coordinate value satisfies a predetermined electrode quality evaluation criterion and as defective when the measured color coordinate value does not satisfy the predetermined electrode quality evaluation criterion.
    Type: Application
    Filed: April 1, 2021
    Publication date: May 18, 2023
    Applicant: LG ENERGY SOLUTION, LTD.
    Inventors: Hyun Sup LEE, Hyun Jin YANG, Kyun Il RAH, Kyoung Ho KIM, Myung Han LEE, Kyung Mee LEE, Won Seok CHO
  • Patent number: 11652056
    Abstract: A semiconductor memory device includes a first substrate including a first region and a second region, a stacked structure only on the first region of the first substrate among the first region and the second region of the first substrate, the stacked structure including word lines, an interlayer insulating film covering the stacked structure, a dummy conductive structure inside the interlayer insulating film, the dummy conductive structure extending through the stacked structure to contact the first substrate, and a plate contact plug inside the interlayer insulating film, the plate contact plug being connected to the second region of the first substrate, and a height of an upper surface of the dummy conductive structure being greater than a height of an upper surface of the plate contact plug relative to an upper surface of the first substrate.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: May 16, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ha-Min Hwang, Jong Soo Kim, Ju-Young Lim, Won Seok Cho
  • Publication number: 20230127402
    Abstract: The present invention relates to an apparatus for evaluating drying quality of an electrode, and the apparatus includes: an oven configured to provide a space in which an electrode is dried; a measuring unit configured to be positioned at an outlet of the oven and measure a color coordinate value of an electrode active material layer with respect to the dried electrode; and an determination unit configured to determine whether the electrode is dry from the color coordinate value, wherein the determination unit sets a reference value, and determines that a dry state of the electrode is defective if the measured color coordinate value is less than the reference value, and a difference between the measured color coordinate value and the reference value is more than a preset value.
    Type: Application
    Filed: November 11, 2020
    Publication date: April 27, 2023
    Applicant: LG ENERGY SOLUTION, LTD.
    Inventors: Kyung Mee LEE, Won Seok CHO, Hyun Jin YANG, Kyoung Ho KIM, Myung Han LEE
  • Publication number: 20220336711
    Abstract: A light-emitting element and a display device including the same are provided. The light-emitting element comprises a first semiconductor layer doped with an n-type dopant, a second semiconductor layer disposed below the first semiconductor layer and doped with a p-type dopant, a light-emitting layer disposed between the first semiconductor layer and the second semiconductor layer, a first intermediate layer disposed on the first semiconductor layer, and including a metal, and an electrode layer disposed on the first intermediate layer. Light from the light-emitting layer transmits through the first semiconductor layer, the first intermediate layer, and the electrode layer at a transmittance equal to or greater than about 70%.
    Type: Application
    Filed: March 15, 2022
    Publication date: October 20, 2022
    Applicants: Samsung Display Co., LTD., POSTECH Research and Business Development Foundation
    Inventors: Se Young KIM, Jong Lam LEE, Won Seok CHO, Dong Uk KIM, Jae Yong PARK, Chul Jong YOO
  • Publication number: 20220223525
    Abstract: A semiconductor memory device includes a first substrate including a first region and a second region, a stacked structure only on the first region of the first substrate among the first region and the second region of the first substrate, the stacked structure including word lines, an interlayer insulating film covering the stacked structure, a dummy conductive structure inside the interlayer insulating film, the dummy conductive structure extending through the stacked structure to contact the first substrate, and a plate contact plug inside the interlayer insulating film, the plate contact plug being connected to the second region of the first substrate, and a height of an upper surface of the dummy conductive structure being greater than a height of an upper surface of the plate contact plug relative to an upper surface of the first substrate.
    Type: Application
    Filed: September 29, 2021
    Publication date: July 14, 2022
    Inventors: Ha-Min HWANG, Jong Soo KIM, Ju-Young LIM, Won Seok CHO
  • Patent number: 11177274
    Abstract: Provided is a vertical non-volatile memory device having a metal source line. The vertical non-volatile memory device includes cell string units that are formed on first portions of a semiconductor substrate and are vertically arranged with respect to a surface of the semiconductor substrate, impurity regions formed on second portions of the semiconductor substrate between the cell string units, conductive lines formed on the impurity regions, and spacers that are formed on the sidewalls of the cell string units and insulate the conductive lines from the cells string units.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: November 16, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Min Hwang, Han-Soo Kim, Won-Seok Cho, Jae-Hoon Jang
  • Patent number: 10864169
    Abstract: Disclosed are conjugated polymer nanoparticles and a method of producing the same. The conjugated polymer nanoparticles include a conjugated polymer, fatty acid and an amphiphile polymer. The conjugated polymer nanoparticles can be doped even under a neutral environment, thus exhibiting high electrical conductivity and exerting absorbance properties in the near-infrared band even under a neutral environment such as in vivo.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: December 15, 2020
    Assignee: Industry-Academic Cooperation Foundation, Yonsei University
    Inventors: Jae Moon Yang, Jung Hyun Kim, Jeong Hun Kim, Yoo Chan Hong, Won Seok Cho, Seung Yeon Hwang, Jin Suck Suh
  • Publication number: 20190074292
    Abstract: Provided is a vertical non-volatile memory device having a metal source line. The vertical non-volatile memory device includes cell string units that are formed on first portions of a semiconductor substrate and are vertically arranged with respect to a surface of the semiconductor substrate, impurity regions formed on second portions of the semiconductor substrate between the cell string units, conductive lines formed on the impurity regions, and spacers that are formed on the sidewalls of the cell string units and insulate the conductive lines from the cells string units.
    Type: Application
    Filed: November 1, 2018
    Publication date: March 7, 2019
    Inventors: SUNG-MIN HWANG, Han-Soo Kim, Won-Seok Cho, Jae-Hoon Jang
  • Patent number: 10147739
    Abstract: Provided is a vertical non-volatile memory device having a metal source line. The vertical non-volatile memory device includes cell string units that are formed on first portions of a semiconductor substrate and are vertically arranged with respect to a surface of the semiconductor substrate, impurity regions formed on second portions of the semiconductor substrate between the cell string units, conductive lines formed on the impurity regions, and spacers that are formed on the sidewalls of the cell string units and insulate the conductive lines from the cells string units.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: December 4, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Min Hwang, Han-Soo Kim, Won-Seok Cho, Jae-Hoon Jang
  • Patent number: 9966115
    Abstract: A vertical non-volatile memory device includes a substrate, and a first stack of word lines and a second stack of word lines extending in a first direction on the substrate and separated from each other in a second direction perpendicular to the first direction. The device further includes first array lines extending in the second direction on the first and the second stack, and connected to word lines of the first and the second stack through at least two of first via contacts in a same level. The device further include first word select lines being in a same level and extending in the first direction, and connected to each of the first array lines through at least one of second via contacts. Ends of each of the first and the second stack have a form of stairs on the substrate.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: May 8, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Min Hwang, Han-Soo Kim, Won-Seok Cho, Jae-Hoon Jang, Sun-Il Shim, Jae-Hun Jeong, Ki-Hyun Kim
  • Patent number: 9881934
    Abstract: Provided is a vertical non-volatile memory device having a metal source line. The vertical non-volatile memory device includes cell string units that are formed on first portions of a semiconductor substrate and are vertically arranged with respect to a surface of the semiconductor substrate, impurity regions formed on second portions of the semiconductor substrate between the cell string units, conductive lines formed on the impurity regions, and spacers that are formed on the sidewalls of the cell string units and insulate the conductive lines from the cells string units.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: January 30, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-min Hwang, Han-soo Kim, Won-seok Cho, Jae-hoon Jang
  • Publication number: 20170266124
    Abstract: Disclosed are conjugated polymer nanoparticles and a method of producing the same. The conjugated polymer nanoparticles include a conjugated polymer, fatty acid and an amphiphile polymer. The conjugated polymer nanoparticles can be doped even under a neutral environment, thus exhibiting high electrical conductivity and exerting absorbance properties in the near-infrared band even under a neutral environment such as in vivo.
    Type: Application
    Filed: March 19, 2015
    Publication date: September 21, 2017
    Inventors: Jae Moon Yang, Jung Hyun Kim, Jeong Hun Kim, Yoo Chan Hong, Won Seok Cho, Seung Yeon Hwang, Jin Suck Suh
  • Publication number: 20170243885
    Abstract: Provided is a vertical non-volatile memory device having a metal source line. The vertical non-volatile memory device includes cell string units that are formed on first portions of a semiconductor substrate and are vertically arranged with respect to a surface of the semiconductor substrate, impurity regions formed on second portions of the semiconductor substrate between the cell string units, conductive lines formed on the impurity regions, and spacers that are formed on the sidewalls of the cell string units and insulate the conductive lines from the cells string units.
    Type: Application
    Filed: May 10, 2017
    Publication date: August 24, 2017
    Inventors: SUNG-MIN HWANG, Han-Soo Kim, Won-Seok Cho, Jae-Hoon Jang
  • Publication number: 20170236559
    Abstract: A vertical non-volatile memory device includes a substrate, and a first stack of word lines and a second stack of word lines extending in a first direction on the substrate and separated from each other in a second direction perpendicular to the first direction. The device further includes first array lines extending in the second direction on the first and the second stack, and connected to word lines of the first and the second stack through at least two of first via contacts in a same level. The device further include first word select lines being in a same level and extending in the first direction, and connected to each of the first array lines through at least one of second via contacts. Ends of each of the first and the second stack have a form of stairs on the substrate.
    Type: Application
    Filed: May 3, 2017
    Publication date: August 17, 2017
    Inventors: SUNG-MIN HWANG, HAN-SOO KIM, WON-SEOK CHO, JAE-HOON JANG, SUN-IL SHIM, JAE-HUN JEONG, KI-HYUN KIM