Patents by Inventor Won Seok Cho
Won Seok Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110018036Abstract: A vertical non-volatile memory device is structured/fabricated to include a substrate, groups of memory cell strings each having a plurality of memory transistors distributed vertically so that the memory throughout multiple layers on the substrate, integrated word lines coupled to sets of the memory transistors, respectively, and stacks of word select lines. The memory transistors of each set are those transistors, of one group of the memory cell strings, which are disposed in the same layer above the substrate. The word select lines are respectively connected to the integrated word lines.Type: ApplicationFiled: December 14, 2009Publication date: January 27, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-min Hwang, Han-soo Kim, Won-seok CHO, Jae-hoon Jang, Sun-il Shim, Jae-hun Jeong, Ki-hyun Kim
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Publication number: 20110002178Abstract: Provided is a vertical non-volatile memory device having a metal source line. The vertical non-volatile memory device includes cell string units that are formed on first portions of a semiconductor substrate and are vertically arranged with respect to a surface of the semiconductor substrate, impurity regions formed on second portions of the semiconductor substrate between the cell string units, conductive lines formed on the impurity regions, and spacers that are formed on the sidewalls of the cell string units and insulate the conductive lines from the cells string units.Type: ApplicationFiled: June 17, 2010Publication date: January 6, 2011Inventors: Sung-min Hwang, Han-soo Kim, Won-seok Cho, Jae-hoon Jang
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Publication number: 20100304025Abstract: A deposition apparatus including a plurality of reaction chambers, and a method of controlling the deposition apparatus. The deposition apparatus includes a first chamber to deposit a first deposition material onto a deposition body, a second chamber to deposit a second and different deposition material onto the deposition body, a third chamber to deposit the first deposition material onto the deposition body, a transfer chamber connected to the first through third chambers, the transfer chamber to transfer the deposition body to ones of the first through third chambers and a control unit to transport the deposition body from the transfer chamber to ones of the first through third chambers.Type: ApplicationFiled: April 29, 2010Publication date: December 2, 2010Applicant: SAMSUNG MOBILE DISPLAY CO., LTD.Inventors: Min-Jeong Hwang, You-Min Cha, Won-Seok Cho, Jae-Mork Park, Jae-Wan Park, Jae-Hong Ahn
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Publication number: 20100275841Abstract: A deposition source capable of uniformly producing a deposition film. The deposition source includes a furnace, a first heating unit surrounding the furnace to heat the furnace and a second heating unit spaced-apart from the first heating unit by an interval and surrounding the furnace to heat the furnace, wherein the second heating unit comprises a plurality of separate sub-heating units that surround the furnace.Type: ApplicationFiled: April 29, 2010Publication date: November 4, 2010Applicant: SAMSUNG MOBILE DISPLAY CO., LTD.Inventors: Jong-Woo Lee, Tae-Seung Kim, Chang-Soon Ji, Won-Seok Cho, Hey-Yeon Shim, Yong-Hun Jo, Sang-Jin Han
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Publication number: 20100279021Abstract: An apparatus for depositing an organic material and a depositing method thereof, wherein a deposition process is performed with respect to a second substrate while transfer and alignment processes are performed with respect to a first substrate in a chamber, so that loss of an organic material wasted in the transfer and alignment processes can be reduced, thereby maximizing material efficiency and minimizing a processing tack time. The apparatus includes a chamber having an interior divided into a first substrate deposition area and a second substrate deposition area, an organic material deposition source transferred to within ones of the first and second substrate deposition areas to spray particles of an organic material onto respective ones of first and second substrates and a first transferring unit to rotate the organic material deposition source in a first direction from one of the first and second substrate deposition areas to an other of the first and second substrate deposition areas.Type: ApplicationFiled: April 19, 2010Publication date: November 4, 2010Applicant: SAMSUNG MOBILE DISPLAY CO., LTD.Inventors: Jae-Wan PARK, You-Min CHA, Won-Seok CHO, Jae-Mork PARK, Jae-Hong AHN, Min-Jeong HWANG, Tae-Wook KIM, Jong-Woo LEE, Tae-Seung KIM
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Publication number: 20100275842Abstract: Provided is an evaporating apparatus that deposits a deposition material onto a treatment object. The evaporating apparatus includes a base, a deposition source, and first and second correction units. The deposition source deposits the deposition material onto the treatment object. The base is disposed separately from the treatment object. The deposition source is placed on a surface of the base. The first and second correction units located between the deposition source and the treatment object. The first and second correction units are disposed on outer regions of the deposition source and face each other. Each of the first and second correction units rotates to control the thickness of a layer formed by the deposition material deposited on the treatment object.Type: ApplicationFiled: March 26, 2010Publication date: November 4, 2010Applicant: Samsung Mobile Display Co., Ltd.Inventors: Jae-Wan Park, You-Min Cha, Jae-Hong Ahn, Won-Seok Cho, Jae-Mork Park, Min-Jeong Hwang
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Publication number: 20100195395Abstract: A non-volatile memory device having a vertical structure includes a NAND string having a vertical structure. The NAND string includes a plurality of memory cells, and at least one pair of first selection transistors arranged to be adjacent to a first end of the plurality of memory cells. A plurality of word lines are coupled to the plurality of memory cells of the NAND string. A first selection line is commonly connected to the at least one pair of first selection transistors of the NAND string.Type: ApplicationFiled: February 2, 2010Publication date: August 5, 2010Applicant: Samsung Electronics Co., Ltd.Inventors: Jae-hun Jeong, Han-soo Kim, Won-seok Cho, Jae-hoon Jang, Sun-il Shim
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Patent number: 7719033Abstract: Semiconductor devices having thin film transistors (TFTs) and methods of fabricating the same are provided. The semiconductor devices include a semiconductor substrate and a lower interlayer insulating layer disposed on the semiconductor substrate. A lower semiconductor body disposed on or in the lower interlayer insulating layer. A lower TFT includes a lower source region and a lower drain region, which are disposed in the lower semiconductor body, and a lower gate electrode, which covers and crosses at least portions of at least two surfaces of the lower semiconductor body disposed between the lower source and drain regions.Type: GrantFiled: February 28, 2006Date of Patent: May 18, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Hun Jeong, Soon-Moon Jung, Hoon Lim, Won-Seok Cho, Jin-Ho Kim, Chang-Min Hong, Jong-Hyuk Kim, Kun-Ho Kwak
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Patent number: 7709323Abstract: Methods of forming a NAND-type nonvolatile memory device include: forming first common drains and first common sources alternatively in an active region which is defined in a semiconductor substrate and extends one direction, forming a first insulating layer covering an entire surface of the semiconductor substrate, patterning the first insulating layer to form seed contact holes which are arranged at regular distance and expose the active region, forming a seed contact structure filling each of the seed contact holes and a semiconductor layer disposed on the first insulating layer and contacting the seed contact structures, patterning the semiconductor layer to form a semiconductor pattern which extends in the one direction and is disposed over the active region, forming second common drains and second common sources disposed alternatively in the semiconductor pattern in the one direction, forming a second insulating layer covering an entire surface of the semiconductor substrate, forming a source line patteType: GrantFiled: May 29, 2009Date of Patent: May 4, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Hoo-Sung Cho, Soon-Moon Jung, Won-Seok Cho, Jong-Hyuk Kim, Jae-Hun Jeong, Jae-Hoon Jang
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Patent number: 7683404Abstract: A stacked memory includes at least two semiconductor layers each including a memory cell array. A transistor is formed in a peripheral circuit region of an uppermost semiconductor layer of the at least two semiconductor layers. The transistor is used to operate the memory cell array.Type: GrantFiled: February 22, 2007Date of Patent: March 23, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Chul Jang, Won-Seok Cho, Jae-Hoon Jang, Soon-Moon Jung, Hoo-Sung Cho, Jong-Hyuk Kim
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Publication number: 20100035386Abstract: A semiconductor device includes a semiconductor substrate including a first region having a cell region and a second region having a peripheral circuit region, first transistors on the semiconductor substrate, a first protective layer covering the first transistors, a first insulation layer on the first protective layer, a semiconductor pattern on the first insulation layer in the first region, second transistors on the semiconductor pattern, a second protective layer covering the second transistors, the second protective layer having a thickness greater than that of the first protective layer, and a second insulation layer on the second protective layer and the first insulation layer of the second region.Type: ApplicationFiled: October 8, 2009Publication date: February 11, 2010Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young-Chul Jang, Won-Seok Cho, Jae-Hoon Jang, Soon-Moon Jung, Yang-Soo Son, Min-Sung Song
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Publication number: 20100012980Abstract: On embodiment of a contact structure may include a lower insulation layer on a lower substrate, an upper substrate on the lower insulation layer, a groove penetrating the upper substrate to extend into the lower insulation layer, the groove below an interface between the upper substrate and the lower insulation layer, an upper insulation layer in the groove, and a contact plug penetrating the upper insulation layer in the groove to extend into the lower insulation layer.Type: ApplicationFiled: July 17, 2009Publication date: January 21, 2010Inventors: Min-Sung Song, Soon-Moon Jung, Han-Soo Kim, Young-Seop Rah, Won-Seok Cho, Yang-Soo Son, Jong-Hyuk Kim, Young-Chul Jang
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Patent number: 7602028Abstract: A NAND flash memory device includes a lower semiconductor layer and an upper semiconductor layer located over the lower semiconductor layer, a first drain region and a first source region located in the lower semiconductor layer, and a second drain region and a second source region located in the upper semiconductor layer. A first gate structure is located on the lower semiconductor layer, and a second gate structure is located on the upper semiconductor layer. A bit line is located over the upper semiconductor layer, and at least one bit line plug is connected between the bit line and the first drain region, where the at least one bit line plug extends through a drain throughhole located in the upper semiconductor layer.Type: GrantFiled: January 17, 2007Date of Patent: October 13, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Yang-Soo Son, Young-Seop Rah, Won-Seok Cho, Soon-Moon Jung, Jae-Hoon Jang, Young-Chul Jang
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Patent number: 7601998Abstract: A semiconductor device includes a semiconductor substrate including a first region having a cell region and a second region having a peripheral circuit region, first transistors on the semiconductor substrate, a first protective layer covering the first transistors, a first insulation layer on the first protective layer, a semiconductor pattern on the first insulation layer in the first region, second transistors on the semiconductor pattern, a second protective layer covering the second transistors, the second protective layer having a thickness greater than that of the first protective layer, and a second insulation layer on the second protective layer and the first insulation layer of the second region.Type: GrantFiled: January 19, 2007Date of Patent: October 13, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Chul Jang, Won-Seok Cho, Jae-Hoon Jang, Soon-Moon Jung, Yang-Soo Son, Min-Sung Song
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Publication number: 20090233405Abstract: Methods of forming a NAND-type nonvolatile memory device include: forming first common drains and first common sources alternatively in an active region which is defined in a semiconductor substrate and extends one direction, forming a first insulating layer covering an entire surface of the semiconductor substrate, patterning the first insulating layer to form seed contact holes which are arranged at regular distance and expose the active region, forming a seed contact structure filling each of the seed contact holes and a semiconductor layer disposed on the first insulating layer and contacting the seed contact structures, patterning the semiconductor layer to form a semiconductor pattern which extends in the one direction and is disposed over the active region, forming second common drains and second common sources disposed alternatively in the semiconductor pattern in the one direction, forming a second insulating layer covering an entire surface of the semiconductor substrate, forming a source line patteType: ApplicationFiled: May 29, 2009Publication date: September 17, 2009Inventors: Hoo-Sung Cho, Soon-Moon Jung, Won-Seok Cho, Jong-Hyuk Kim, Jae-Hun Jeong, Jae-Hoon Jang
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Patent number: 7563683Abstract: Disclosed is a method for fabricating a gate of a field effect transistor. The method comprises a) forming a field oxide layer on a silicon substrate and then applying a photoresist layer in order to define a gate, b) etching the silicon substrate using the photoresist layer as a mask, c) sequentially depositing a gate oxide layer and a gate polysilicon layer on an entire surface of the silicon substrate and defining the gate using the photoresist layer, d) etching the resulting silicon substrate using the photoresist layer as a mask to form the gate and forming an N? ion region by means of ion implantation, and e) depositing and etching back an oxide layer to form a sidewall oxide layer and forming an N+ ion region by means of ion implantation. Consequently, the gate is made by etching the silicon substrate. Thus, a length of the gate is reduced, so that it is possible not only to make a cell area smaller but also to prevent a short-channel effect.Type: GrantFiled: December 15, 2006Date of Patent: July 21, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Chul Jang, Won-Seok Cho, Soon-Moon Jung
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Patent number: 7554140Abstract: Provided is a NAND-type nonvolatile memory device and method of forming the same. In the method, a plurality of cell layers are stacked on a semiconductor substrate. Seed contact holes for forming a semiconductor pattern included in a stacked cell are formed at regular distance. At this time, the seed contact holes are arranged such that a bit line plug or a source line pattern is disposed at a center between one pair of seed contact holes adjacent to each other.Type: GrantFiled: January 10, 2007Date of Patent: June 30, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Hoo-Sung Cho, Soon-Moon Jung, Won-Seok Cho, Jong-Hyuk Kim, Jae-Hun Jeong, Jae-Hoon Jang
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Patent number: 7485535Abstract: Semiconductor devices and methods of fabricating semiconductor devices that include a substrate and a device isolation layer in the substrate that defines an active region of the substrate are provided. The device isolation layer has a vertically protruding portion having a sidewall that extends vertically beyond a surface of the substrate. An epitaxial layer is provided on the surface of the substrate in the active region and extends onto the device isolation layer. The epitaxial layer is spaced apart from the sidewall of the vertically protruding portion of the device isolation layer. A gate pattern is provided on the epitaxial layer and source/drain regions are provided in the epitaxial layer at opposite sides of the gate pattern.Type: GrantFiled: February 9, 2007Date of Patent: February 3, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Hoon Lim, Soon-Moon Jung, Won-Seok Cho
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Patent number: 7432560Abstract: A metal oxide semiconductor field effect transistor (MOSFET) includes a body pattern of a first conductivity type disposed on an insulating layer. A gate electrode is disposed on the body pattern. A drain region of a second conductivity type is disposed on the insulating layer and having a sidewall in contact with a first sidewall of the body pattern. An impurity-doped region of the first conductivity type is disposed on the insulating layer and having a sidewall in contact with a second sidewall of the body pattern. The MOSFET further includes a source region of the second conductivity type disposed on the impurity-doped region and having a sidewall in contact with the second sidewall of the body pattern, and a contact plug extending through the source region to contact the impurity-doped region.Type: GrantFiled: July 12, 2005Date of Patent: October 7, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Hoon Lim, Soon-Moon Jung, Won-Seok Cho, Jae-Hun Jeong
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Patent number: 7417286Abstract: Semiconductor integrated circuit devices having single crystalline thin film transistors and methods of fabricating the same are provided. The semiconductor integrated circuit devices include an interlayer insulating layer formed on a semiconductor substrate and a single crystalline semiconductor plug penetrating the interlayer insulating layer. A single crystalline semiconductor body pattern is provided on the interlayer insulating layer. The single crystalline semiconductor body pattern has an elevated region and contacts the single crystalline semiconductor plug. The method of forming the single crystalline semiconductor body pattern having the elevated region includes forming a sacrificial layer pattern covering the single crystalline semiconductor plug on the interlayer insulating layer. A capping layer is formed to cover the sacrificial layer pattern and the interlayer insulating layer, and the capping layer is patterned to form an opening which exposes a portion of the sacrificial layer pattern.Type: GrantFiled: November 15, 2005Date of Patent: August 26, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Jin Kim, Soon-Moon Jung, Won-Seok Cho, Jae-Hoon Jang, Jong-Hyuk Kim, Kun-Ho Kwak, Hoon Lim