Patents by Inventor Xiaobin Wang
Xiaobin Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190043947Abstract: Semiconductor devices are formed using a pair of thin epitaxial layers (nanotubes) of opposite conductivity type formed on sidewalls of dielectric-filled trenches. In one embodiment, a termination structure is formed in the termination area and includes a first termination cell formed in the termination area at an interface to the active area, the termination cell being formed in a mesa of the first semiconductor layer and having a first width; and an end termination cell being formed next to the first termination cell in the termination area, the end termination cell being formed in an end mesa of the first semiconductor layer and having a second width greater than the first width.Type: ApplicationFiled: July 26, 2018Publication date: February 7, 2019Inventors: Hamza Yilmaz, Xiaobin Wang, Anup Bhalla, John Chen, Hong Chang
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Patent number: 10153017Abstract: The present invention is directed to a method for sensing the resistance state of a memory cell that includes an MTJ memory element coupled to a two-terminal selector element in series. The method includes the steps of raising a cell voltage across the memory cell above a threshold voltage for the selector element to become conductive; decreasing the cell voltage to a first sensing voltage and measuring a first sensing current passing through the memory cell, the selector element being nominally conductive irrespective of the resistance state of the MTJ memory element at the first sensing voltage; and further decreasing the cell voltage to a second sensing voltage and measuring a second sensing current, the selector element being nominally conductive if the MTJ memory element is in the low resistance state or nominally insulative if the MTJ memory element is in the high resistance state at the second sensing voltage.Type: GrantFiled: September 14, 2016Date of Patent: December 11, 2018Assignee: Avalanche Technology, Inc.Inventors: Hongxin Yang, Xiaobin Wang, Jing Zhang, Xiaojie Hao, Zihui Wang, Kimihiro Satoh
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Publication number: 20180337274Abstract: Fabricating a semiconductor device includes: forming a first gate trench and a second gate trench in an epitaxial layer overlaying a semiconductor substrate; depositing gate material in the first gate trench to form a first gate and depositing gate material in the second gate trench to form a second gate; forming a body; forming a source; forming an active region contact trench that extends through the source and the body, and a gate contact trench within the second gate; forming an island region under the active region contact trench and disconnected from the body, the island region having an opposite polarity as the epitaxial layer; and disposing a first electrode within the active region contact trench and a second electrode within the gate contact trench.Type: ApplicationFiled: July 31, 2018Publication date: November 22, 2018Inventors: Anup Bhalla, Xiaobin Wang, Ji Pan, Sung-Po Wei
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Publication number: 20180323155Abstract: A trench-type metal-oxide-semiconductor field-effect transistor (MOSFET) device and a fabrication method are disclosed. A semiconductor substrate of a first conductivity type is provided. A plurality of first trenches arranged side by side in a first stripe layout extending along a first direction in a first preset area of the semiconductor substrate are formed. A plurality of second trenches arranged side by side in a second stripe layout extending along a second direction perpendicular to the first direction in a second preset area of the semiconductor substrate are formed. The plurality of first trenches and the plurality of second trenches are filled with a conductive material so as to form a plurality of control gates.Type: ApplicationFiled: June 21, 2018Publication date: November 8, 2018Applicant: Alpha and Omega Semiconductor IncorporatedInventors: Xiaobin Wang, Madhur Bobde, Paul Thorup
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Patent number: 10074742Abstract: A semiconductor device formed on a semiconductor substrate, comprising: an epitaxial layer overlaying the semiconductor substrate; a drain formed on back of the semiconductor substrate; a drain region that extends into the epitaxial layer; an active region; and an island region under the contact trench and disconnected from the body, the island region having an opposite polarity as the epitaxial layer. The active region comprises: a body disposed in the epitaxial layer; a source embedded in the body; a gate trench extending into the epitaxial layer; a gate disposed in the gate trench; an active region contact trench extending through the source and the body; and an active region contact electrode disposed within the active region contact trench.Type: GrantFiled: December 7, 2015Date of Patent: September 11, 2018Assignee: Alpha and Omega Semiconductor LimitedInventors: Anup Bhalla, Xiaobin Wang, Ji Pan, Sung-Po Wei
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Patent number: 10062755Abstract: Semiconductor devices are formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches. In one embodiment, a termination structure is formed in the termination area and includes an array of termination cells formed in the termination area, the array of termination cells including a first termination cell at an interface to the active area to a last termination cell, each termination cell in the array of termination cells being formed in a mesa of the first semiconductor layer and having a first width; and an end termination cell being formed next to the last termination cell in the termination area, the end termination cell being formed in an end mesa of the first semiconductor layer and having a second width greater than the first width.Type: GrantFiled: January 10, 2018Date of Patent: August 28, 2018Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Hamza Yilmaz, Xiaobin Wang, Anup Bhalla, John Chen, Hong Chang
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Publication number: 20180240844Abstract: The present invention is directed to a memory cell that includes a magnetic tunnel junction (MTJ) memory element, which has a low resistance state and a high resistance state, and a two-terminal selector coupled to the MTJ memory element in series. The MTJ memory element includes a magnetic free layer and a magnetic reference layer with an insulating tunnel junction layer interposed therebetween. The two-terminal selector has an insulative state and a conductive state. The two-terminal selector in the conductive state has substantially lower resistance when switching the MTJ memory element from the low to high resistance state than from the high to low resistance state. The voltages applied to the memory cell to respectively switch the MTJ memory element from the low to high resistance state and from the high to low resistance state may be substantially same.Type: ApplicationFiled: February 21, 2017Publication date: August 23, 2018Inventors: Hongxin Yang, Xiaojie Hao, Jing Zhang, Xiaobin Wang, Bing K. Yen
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Patent number: 10032728Abstract: A trench-type metal-oxide-semiconductor field-effect transistor (MOSFET) device and a fabrication method are disclosed. The trench MOSFET device comprises a semiconductor substrate of a first conductivity type. The semiconductor substrate has a plurality of first trenches arranged side by side in a first preset area of the semiconductor substrate extending along a first direction and a plurality of second trenches arranged side by side in a second preset area of the semiconductor substrate extending along a second direction perpendicular to the first direction. A control gate is formed in each of the pluralities of first and second trenches. A body region of a second conductivity type is formed at a top portion of the semiconductor substrate near sidewalls of the pluralities of first and second trenches. A source region of the first conductivity type is formed on a top portion of the body region.Type: GrantFiled: June 30, 2016Date of Patent: July 24, 2018Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATEDInventors: Xiaobin Wang, Madhur Bobde, Paul Thorup
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Patent number: 10008540Abstract: The present invention is directed to a spin-orbitronics device including an array of MTJs with each of the MTJs coupled to a respective one of a plurality of selection transistors; a plurality of transverse polarizing lines with each of the transverse polarizing lines coupled to a row of the MTJs along a first direction; a plurality of word lines with each of the word lines coupled to gates of a row of the selection transistors along a second direction; and a plurality of source lines with each of the source lines coupled to a row of the selection transistors along a direction substantially perpendicular to the second direction. Each MTJ includes a magnetic comparison layer structure having a pseudo-invariable magnetization direction, which is configured to switch between two stable states by passing a comparison current through one of the plurality of transverse polarizing lines formed adjacent to the magnetic comparison layer structure.Type: GrantFiled: May 4, 2017Date of Patent: June 26, 2018Assignee: Avalanche Technology, Inc.Inventors: Parviz Keshtbod, Xiaobin Wang, Kimihiro Satoh, Zihui Wang, Huadong Gan
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Patent number: 9997593Abstract: A trench type power semiconductor device with improved breakdown voltage and UIS performance and a method for preparation the device are disclosed. The trench type power semiconductor device includes a first contact hole formed in a mesa in the active area and a second contact hole formed in a mesa in an active to termination intermediate area, where the first contact hole is deeper and wider than the second contact hole. The method comprises the steps of providing a semiconductor substrate, etching an epitaxial layer, depositing a conductive material, depositing an insulation passivation layer and etching through the insulation passivation layer.Type: GrantFiled: July 10, 2017Date of Patent: June 12, 2018Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.Inventors: Yongping Ding, Hamza Yilmaz, Xiaobin Wang, Madhur Bobde
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Publication number: 20180130880Abstract: Semiconductor devices are formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches. In one embodiment, a termination structure is formed in the termination area and includes an array of termination cells formed in the termination area, the array of termination cells including a first termination cell at an interface to the active area to a last termination cell, each termination cell in the array of termination cells being formed in a mesa of the first semiconductor layer and having a first width; and an end termination cell being formed next to the last termination cell in the termination area, the end termination cell being formed in an end mesa of the first semiconductor layer and having a second width greater than the first width.Type: ApplicationFiled: January 10, 2018Publication date: May 10, 2018Inventors: Hamza Yilmaz, Xiaobin Wang, Anup Bhalla, John Chen, Hong Chang
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Patent number: 9960237Abstract: A termination structure with multiple embedded potential spreading capacitive structures (TSMEC) and method are disclosed for terminating an adjacent trench MOSFET atop a bulk semiconductor layer (BSL) with bottom drain electrode. The BSL has a proximal bulk semiconductor wall (PBSW) supporting drain-source voltage (DSV) and separating TSMEC from trench MOSFET. The TSMEC has oxide-filled large deep trench (OFLDT) bounded by PBSW and a distal bulk semiconductor wall (DBSW). The OFLDT includes a large deep oxide trench into the BSL and embedded capacitive structures (EBCS) located inside the large deep oxide trench and between PBSW and DBSW for spatially spreading the DSV across them. In one embodiment, the EBCS contains interleaved conductive embedded polycrystalline semiconductor regions (EPSR) and oxide columns (OXC) of the OFLDT, a proximal EPSR next to PBSW is connected to an active upper source region and a distal EPSR next to DBSW is connected to the DBSW.Type: GrantFiled: April 13, 2015Date of Patent: May 1, 2018Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Xiaobin Wang, Anup Bhalla, Hamza Yilmaz, Daniel Ng
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Publication number: 20180075891Abstract: The present invention is directed to a method for sensing the resistance state of a memory cell that includes an MTJ memory element coupled to a two-terminal selector element in series. The method includes the steps of raising a cell voltage across the memory cell above a threshold voltage for the selector element to become conductive; decreasing the cell voltage to a first sensing voltage and measuring a first sensing current passing through the memory cell, the selector element being nominally conductive irrespective of the resistance state of the MTJ memory element at the first sensing voltage; and further decreasing the cell voltage to a second sensing voltage and measuring a second sensing current, the selector element being nominally conductive if the MTJ memory element is in the low resistance state or nominally insulative if the MTJ memory element is in the high resistance state at the second sensing voltage.Type: ApplicationFiled: September 14, 2016Publication date: March 15, 2018Inventors: Hongxin Yang, Xiaobin Wang, Jing Zhang, Xiaojie Hao, Zihui Wang, Kimihiro Satoh
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Patent number: 9899474Abstract: Semiconductor devices includes a thin epitaxial layer (nanotube) formed on sidewalls of mesas formed in a semiconductor layer. In one embodiment, a semiconductor device includes a first semiconductor layer, a second semiconductor layer formed thereon and of the opposite conductivity type, and a first epitaxial layer formed on mesas of the second semiconductor layer. An electric field along a length of the first epitaxial layer is uniformly distributed.Type: GrantFiled: June 8, 2017Date of Patent: February 20, 2018Assignee: Alpha and Omega Semiconductor, Inc.Inventors: Hamza Yilmaz, Xiaobin Wang, Anup Bhalla, John Chen, Hong Chang
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Patent number: 9871191Abstract: The present invention is directed to an MRAM device comprising a plurality of MTJ memory elements. Each of the memory elements includes a magnetic free layer and a first magnetic reference layer with an insulating tunnel junction layer interposed therebetween; a second magnetic reference layer formed adjacent to the first magnetic reference layer opposite the insulating tunnel junction layer; an anti-ferromagnetic coupling layer formed adjacent to the second magnetic reference layer opposite the first magnetic reference layer; and a magnetic fixed layer formed adjacent to the anti-ferromagnetic coupling layer. The magnetic free layer has a variable magnetization direction substantially perpendicular to the layer plane thereof. The first and second magnetic reference layers have a first fixed magnetization direction substantially perpendicular to the layer planes thereof.Type: GrantFiled: June 3, 2015Date of Patent: January 16, 2018Assignee: Avalanche Technology, Inc.Inventors: Yuchen Zhou, Yiming Huai, Zihui Wang, Xiaojie Hao, Huadong Gan, Xiaobin Wang
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Patent number: 9871190Abstract: The present invention is directed to an MRAM device comprising a plurality of MTJ memory elements. Each of the memory elements includes a magnetic free layer and a first magnetic reference layer with an insulating tunnel junction layer interposed therebetween; a second magnetic reference layer formed adjacent to the first magnetic reference layer opposite the insulating tunnel junction layer; an anti-ferromagnetic coupling layer formed adjacent to the second magnetic reference layer opposite the first magnetic reference layer; and a magnetic fixed layer formed adjacent to the anti-ferromagnetic coupling layer. The magnetic free layer has a variable magnetization direction substantially perpendicular to the layer plane thereof. The first and second magnetic reference layers have a first fixed magnetization direction substantially perpendicular to the layer planes thereof.Type: GrantFiled: April 28, 2014Date of Patent: January 16, 2018Assignee: Avalanche Technology, Inc.Inventors: Huadong Gan, Yiming Huai, Yuchen Zhou, Xiaobin Wang, Zihui Wang
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Publication number: 20180005959Abstract: A trench-type metal-oxide-semiconductor field-effect transistor (MOSFET) device and a fabrication method are disclosed. The trench MOSFET device comprises a semiconductor substrate of a first conductivity type. The semiconductor substrate has a plurality of first trenches arranged side by side in a first preset area of the semiconductor substrate extending along a first direction and a plurality of second trenches arranged side by side in a second preset area of the semiconductor substrate extending along a second direction perpendicular to the first direction. A control gate is formed in each of the pluralities of first and second trenches. A body region of a second conductivity type is formed at a top portion of the semiconductor substrate near sidewalls of the pluralities of first and second trenches. A source region of the first conductivity type is formed on a top portion of the body region.Type: ApplicationFiled: June 30, 2016Publication date: January 4, 2018Applicant: Alpha and Omega Semiconductor IncorporatedInventors: Xiaobin Wang, Madhur Bobde, Paul Thorup
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Publication number: 20170370463Abstract: A steering gear housing and method of manufacturing same are provided. The steering gear housing is comprised of aluminum alloy and is at least partially anodized. The steering gear housing defines a plurality of mounting apertures. A plurality of nuts is fit into a respective one of the mounting apertures for use in mounting to a vehicle. Each of the nuts defines a plurality of splines for establishing a press-fit relationship between the mounting apertures and the nuts. The method involves casting a steering gear housing defining a plurality of mounting apertures out of aluminum alloy. Next, the casted steering gear housing is at least partially anodized. After anodization, a plurality of nuts is fit into respective ones of the mounting apertures. The nuts define splines for allowing a press-fit relationship to be established between the mounting apertures and the nuts.Type: ApplicationFiled: June 27, 2017Publication date: December 28, 2017Inventors: Haimian Cai, Shen Li, Bokai Jin, Gangchun Xu, Min Nie, Xiaobin Wang
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Publication number: 20170373139Abstract: A trench type power semiconductor device with improved breakdown voltage and UIS performance and a method for preparation the device are disclosed. The trench type power semiconductor device includes a first contact hole formed in a mesa in the active area and a second contact hole formed in a mesa in an active to termination intermediate area, where the first contact hole is deeper and wider than the second contact hole. The method comprises the steps of providing a semiconductor substrate, etching an epitaxial layer, depositing a conductive material, depositing an insulation passivation layer and etching through the insulation passivation layer.Type: ApplicationFiled: July 10, 2017Publication date: December 28, 2017Applicant: Alpha and Omega Semiconductor (Cayman) Ltd.Inventors: Yongping Ding, Hamza Yilmaz, Xiaobin Wang, Madhur Bobde
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Patent number: 9831421Abstract: The present invention is directed to an MTJ memory element including a magnetic free layer structure which includes one or more magnetic free layers that have a same variable magnetization direction substantially perpendicular to layer planes thereof; an insulating tunnel junction layer formed adjacent to the magnetic free layer structure; a magnetic reference layer structure comprising a first magnetic reference layer formed adjacent to the insulating tunnel junction layer and a second magnetic reference layer separated therefrom by a perpendicular enhancement layer with the first and second magnetic reference layers having a first fixed magnetization direction substantially perpendicular to layer planes thereof; an anti-ferromagnetic coupling layer formed adjacent to the second magnetic reference layer opposite the perpendicular enhancement layer; and a magnetic fixed layer comprising first and second magnetic fixed sublayers with the second magnetic fixed sublayer formed adjacent to the anti-ferromagneticType: GrantFiled: July 13, 2015Date of Patent: November 28, 2017Assignee: Avalanche Technology, Inc.Inventors: Zihui Wang, Huadong Gan, Yiming Huai, Yuchen Zhou, Xiaobin Wang, Bing K. Yen, Xiaojie Hao