Patents by Inventor Xiaobin Wang

Xiaobin Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170288137
    Abstract: The present invention is directed to an MTJ memory element including a magnetic free layer structure which includes one or more magnetic free layers that have a same variable magnetization direction substantially perpendicular to layer planes thereof; an insulating tunnel junction layer formed adjacent to the magnetic free layer structure; a magnetic reference layer structure comprising a first magnetic reference layer formed adjacent to the insulating tunnel junction layer and a second magnetic reference layer separated therefrom by a perpendicular enhancement layer with the first and second magnetic reference layers having a first fixed magnetization direction substantially perpendicular to layer planes thereof; an anti-ferromagnetic coupling layer formed adjacent to the second magnetic reference layer opposite the perpendicular enhancement layer; and a magnetic fixed layer comprising first and second magnetic fixed sublayers with the second magnetic fixed sublayer formed adjacent to the anti-ferromagnetic
    Type: Application
    Filed: July 13, 2015
    Publication date: October 5, 2017
    Inventors: Zihui Wang, Huadong Gan, Yiming Huai, Yuchen Zhou, Xiaobin Wang, Bing K. Yen, Xiaojie Hao
  • Publication number: 20170236868
    Abstract: The present invention is directed to a spin-orbitronics device including an array of MTJs with each of the MTJs coupled to a respective one of a plurality of selection transistors; a plurality of transverse polarizing lines with each of the transverse polarizing lines coupled to a row of the MTJs along a first direction; a plurality of word lines with each of the word lines coupled to gates of a row of the selection transistors along a second direction; and a plurality of source lines with each of the source lines coupled to a row of the selection transistors along a direction substantially perpendicular to the second direction. Each MTJ includes a magnetic comparison layer structure having a pseudo-invariable magnetization direction, which is configured to switch between two stable states by passing a comparison current through one of the plurality of transverse polarizing lines formed adjacent to the magnetic comparison layer structure.
    Type: Application
    Filed: May 4, 2017
    Publication date: August 17, 2017
    Inventors: Parviz Keshtbod, Xiaobin Wang, Kimihiro Satoh, Zihui Wang, Huadong Gan
  • Patent number: 9704948
    Abstract: A trench type power semiconductor device with improved breakdown voltage and UIS performance and a method for preparation the device are disclosed. The trench type power semiconductor device includes a first contact hole formed in a mesa in the active area and a second contact hole formed in a mesa in an active to termination intermediate area, where the first contact hole is deeper and wider than the second contact hole.
    Type: Grant
    Filed: August 9, 2014
    Date of Patent: July 11, 2017
    Assignee: Alpha & Omega Semiconductor (Cayman), Ltd.
    Inventors: Yongping Ding, Hamza Yilmaz, Xiaobin Wang, Madhur Bobde
  • Patent number: 9704955
    Abstract: Semiconductor devices are formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches. In one embodiment, a method for forming a semiconductor device includes forming a first epitaxial layer on sidewalls of trenches and forming second epitaxial layer on the first epitaxial layer where charges in the doped regions along the sidewalls of the first and second trenches achieve charge balance in operation. In another embodiment, the semiconductor device includes a termination structure including an array of termination cells.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: July 11, 2017
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Hamza Yilmaz, Xiaobin Wang, Anup Bhalla, John Chen, Hong Chang
  • Patent number: 9647202
    Abstract: The present invention is directed to an MRAM element comprising a plurality of magnetic tunnel junction (MTJ) memory elements. Each of the memory elements comprises a magnetic reference layer structure, which includes a first and a second magnetic reference layers with a tantalum perpendicular enhancement layer interposed therebetween, an insulating tunnel junction layer formed adjacent to the first magnetic reference layer opposite the tantalum perpendicular enhancement layer, and a magnetic free layer formed adjacent to the insulating tunnel junction layer. The first and second magnetic reference layers have a first fixed magnetization direction substantially perpendicular to the layer planes thereof.
    Type: Grant
    Filed: April 18, 2014
    Date of Patent: May 9, 2017
    Assignee: Avalanche Technology, Inc.
    Inventors: Huadong Gan, Yuchen Zhou, Yiming Huai, Zihui Wang, Xiaobin Wang
  • Patent number: 9647032
    Abstract: The present invention is directed to a spin-orbitronics device including a magnetic comparison layer structure having a pseudo-invariable magnetization direction; a magnetic free layer structure whose variable magnetization direction can be switched by a switching current passing between the magnetic comparison layer structure and the magnetic free layer structure; an insulating tunnel junction layer interposed between the magnetic comparison layer structure and the magnetic free layer structure; and a non-magnetic transverse polarizing layer formed adjacent to the magnetic comparison layer structure. The pseudo-invariable magnetization direction of the magnetic comparison layer structure may be switched by passing a comparison current through the transverse polarizing layer along a direction that is substantially parallel to a layer plane of the transverse polarizing layer. The pseudo-invariable magnetization direction of the magnetic comparison layer structure is not switched by the switching current.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: May 9, 2017
    Assignee: Avalanche Technology, Inc.
    Inventors: Xiaobin Wang, Parviz Keshtbod, Kimihiro Satoh, Zihui Wang, Huadong Gan
  • Publication number: 20170125531
    Abstract: Semiconductor device fabrication method and devices are disclosed. The semiconductor power device is formed on a semiconductor substrate having a plurality of trench transistor cells each having a trench gate. Each of the trench gates having a thicker bottom oxide (TBO) formed by a REOX process on a polysilicon layer deposited on a bottom surface of the trenches.
    Type: Application
    Filed: February 4, 2014
    Publication date: May 4, 2017
    Inventors: Yeeheng Lee, Xiaobin Wang
  • Patent number: 9627526
    Abstract: A semiconductor device having a plurality of transistors includes a termination area that features a transistor with an asymmetric gate.
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: April 18, 2017
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Yeeheng Lee, Yongping Ding, Xiaobin Wang
  • Publication number: 20170084694
    Abstract: Semiconductor devices are formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches. In one embodiment, a method for forming a semiconductor device includes forming a first epitaxial layer on sidewalls of trenches and forming second epitaxial layer on the first epitaxial layer where charges in the doped regions along the sidewalls of the first and second trenches achieve charge balance in operation. In another embodiment, the semiconductor device includes a termination structure including an array of termination cells.
    Type: Application
    Filed: October 19, 2016
    Publication date: March 23, 2017
    Inventors: Hamza Yilmaz, Xiaobin Wang, Anup Bhalla, John Chen, Hong Chang
  • Publication number: 20170069750
    Abstract: A semiconductor device having a plurality of transistors includes a termination area that features a transistor with an asymmetric gate.
    Type: Application
    Filed: March 24, 2014
    Publication date: March 9, 2017
    Applicant: ALPHA & OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Yeeheng Lee, Yongping Ding, Xiaobin Wang
  • Patent number: 9586570
    Abstract: A method for checking sets of components of a vehicle includes configuring a system control unit of a vehicle to perform a check of a first set of components and a second set of components of the vehicle, the first set of components being different from the second set of components. The first set of components is automatically checked using the system control unit. The second set of components is optionally checked using the system control unit, wherein the control unit is configured to disable the check of the second set of components based upon a disable command provided to the control system. Further, a system for verifying different sets of components and a further method for checking sets of components of a vehicle are described.
    Type: Grant
    Filed: January 26, 2015
    Date of Patent: March 7, 2017
    Assignee: SIEMENS INDUSTRY, INC.
    Inventors: Kimberly Richey, Xiaobin Wang
  • Publication number: 20170057271
    Abstract: A method for making a book is provided in the embodiments of the present invention. The method mainly comprises: cutting printed sheets for a book, brushing glue onto edges of the printed sheets, bonding the printed sheets through the glue, and positioning and fixing a plurality of bonded printed sheets by utilizing a right-angled mold; perforating each, of the positioned and fixed printed sheets, and stringing holes of the printed sheets so as to reinforce the printed sheets; and splicing front endpaper and rear endpaper onto endpaper connection cloth, and then, bonding the endpaper and bookblocks. The embodiments of the present invention adopt a right-angled mold to position register and fix a plurality of bonded printed sheets, and pages are unlikely to dislocate, thereby guaranteeing the binding quality of the book, improving the attractiveness of the book, reducing a making time of the book, and improving the production efficiency of the book.
    Type: Application
    Filed: October 29, 2016
    Publication date: March 2, 2017
    Inventor: Xiaobin Wang
  • Publication number: 20170053989
    Abstract: A termination structure with multiple embedded potential spreading capacitive structures (TSMEC) and method are disclosed for terminating an adjacent trench MOSFET atop a bulk semiconductor layer (BSL) with bottom drain electrode. The BSL has a proximal bulk semiconductor wall (PBSW) supporting drain-source voltage (DSV) and separating TSMEC from trench MOSFET. The TSMEC has oxide-filled large deep trench (OFLDT) bounded by PBSW and a distal bulk semiconductor wall (DBSW). The OFLDT includes a large deep oxide trench into the BSL and embedded capacitive structures (EBCS) located inside the large deep oxide trench and between PBSW and DBSW for spatially spreading the DSV across them. In one embodiment, the EBCS contains interleaved conductive embedded polycrystalline semiconductor regions (EPSR) and oxide columns (OXC) of the OFLDT, a proximal EPSR next to PBSW is connected to an active upper source region and a distal EPSR next to DBSW is connected to the DBSW.
    Type: Application
    Filed: April 13, 2015
    Publication date: February 23, 2017
    Inventors: Xiaobin Wang, Anup Bhalla, Hamza Yilmaz, Daniel Ng
  • Patent number: 9570404
    Abstract: A semiconductor power device comprises a plurality of power transistor cells each having a trenched gate disposed in a gate trench wherein the trenched gate comprising a shielding bottom electrode disposed in a bottom portion of the gate trench electrically insulated from a top gate electrode disposed in a top portion of the gate trench by an inter-electrode insulation layer. At least one of the transistor cells includes the shielding bottom electrode functioning as a source-connecting shielding bottom electrode electrically connected to a source electrode of the semiconductor power device and at least one of the transistor cells having the shielding bottom electrode functioning as a gate-connecting shielding bottom electrode electrically connected to a gate metal of the semiconductor power device.
    Type: Grant
    Filed: April 1, 2014
    Date of Patent: February 14, 2017
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Ji Pang, Daniel Ng, Anup Bhalla, Xiaobin Wang
  • Patent number: 9559144
    Abstract: The present invention is directed to a spin transfer torque (STT) MRAM device having a perpendicular magnetic tunnel junction (MTJ) memory element. The memory element includes a perpendicular MTJ structure in between a non-magnetic seed layer and a non-magnetic cap layer. The MTJ structure comprises a magnetic free layer structure and a magnetic reference layer structure with an insulating tunnel junction layer interposed therebetween, an anti-ferromagnetic coupling layer formed adjacent to the magnetic reference layer structure, and a magnetic fixed layer formed adjacent to the anti-ferromagnetic coupling layer. At least one of the magnetic free and reference layer structures includes a non-magnetic perpendicular enhancement layer, which improves the perpendicular anisotropy of magnetic layers adjacent thereto.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: January 31, 2017
    Assignee: Avalanche Technology, Inc.
    Inventors: Huadong Gan, Yiming Huai, Yuchen Zhou, Zihui Wang, Xiaobin Wang, Bing K. Yen
  • Patent number: 9548334
    Abstract: The present invention is directed to a spin transfer torque (STT) MRAM device having a perpendicular magnetic tunnel junction (MTJ) memory element. The memory element includes a perpendicular MTJ structure in between a non-magnetic seed layer and a non-magnetic cap layer. The MTJ structure comprises a magnetic free layer structure and a magnetic reference layer structure with an insulating tunnel junction layer interposed therebetween, an anti-ferromagnetic coupling layer formed adjacent to the magnetic reference layer structure, and a magnetic fixed layer formed adjacent to the anti-ferromagnetic coupling layer. At least one of the magnetic free and reference layer structures includes a non-magnetic perpendicular enhancement layer, which improves the perpendicular anisotropy of magnetic layers adjacent thereto.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: January 17, 2017
    Assignee: Avalanche Technology, Inc.
    Inventors: Huadong Gan, Yuchen Zhou, Yiming Huai, Zihui Wang, Xiaobin Wang
  • Patent number: 9548074
    Abstract: A perpendicular magnetic recording medium adapted for high recording density and high data recording rate comprises a non-magnetic substrate having at least one surface with a layer stack formed thereon, the layer stack including a perpendicular recording layer containing a plurality of columnar-shaped magnetic grains extending perpendicularly to the substrate surface for a length, with a first end distal the surface and a second end proximal the surface, wherein each of the magnetic grains has: (1) a gradient of perpendicular magnetic coercivity Hk extending along its length between the first end and second ends; and (2) predetermined local exchange coupling strengths along the length.
    Type: Grant
    Filed: February 24, 2015
    Date of Patent: January 17, 2017
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Shaoping Li, Kaizhong Gao, Lei Wang, Wenzhong Zhu, Xiaobin Wang
  • Patent number: 9543506
    Abstract: The present invention is directed to an MTJ memory element including a magnetic free layer structure which comprises one or more magnetic free layers that have a same variable magnetization direction substantially perpendicular to layer planes thereof; an insulating tunnel junction layer formed adjacent to the magnetic free layer structure; a magnetic reference layer structure comprising a first magnetic reference layer formed adjacent to the insulating tunnel junction layer and a second magnetic reference layer separated therefrom by a perpendicular enhancement layer with the first and second magnetic reference layers having a first fixed magnetization direction substantially perpendicular to layer planes thereof; an anti-ferromagnetic coupling layer formed adjacent to the second magnetic reference layer opposite the perpendicular enhancement layer; and a magnetic fixed layer comprising first and second magnetic fixed sublayers with the second magnetic fixed sublayer formed adjacent to the anti-ferromagnetic
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: January 10, 2017
    Assignee: Avalanche Technology, Inc.
    Inventors: Huadong Gan, Yiming Huai, Yuchen Zhou, Zihui Wang, Xiaobin Wang, Bing K. Yen, Xiaojie Hao
  • Publication number: 20160343409
    Abstract: The embodiments of the disclosure provide a method and device for video preview. The method includes: with the determination of a need to enter a video preview interface, obtaining a respective preview control corresponding to at least one playback position for playing a preview video in a video preview interface; loading video data of respective one way of preview video corresponding to each of the preview controls; and playing the video data of the respective one way of preview video in each of preview controls. The embodiments of the disclosure can reflect preview video contents accurately in real time, allowing the user to rapidly and accurately find the desirable video, improving the user experience. The video preview manner may have enhanced universality, especially applicable to the preview of the videos having varied contents in real time such as live broadcast and carousel.
    Type: Application
    Filed: May 18, 2016
    Publication date: November 24, 2016
    Inventors: Xiaobin WANG, Bo LI, Liang LI, Xizhe XIAO, Shengkai WANG, Shixing LI
  • Publication number: 20160342319
    Abstract: The embodiments of the present invention provide a method and a device for previewing and displaying multimedia streaming data, wherein the method includes: when a terminal displays a designated interface, determining a thumbnail display area corresponding to at least one previewing and playing area preset in the designated interface, acquiring multimedia streaming data corresponding to the previewing and playing area, loading a floating layer playing control in the previewing and playing area, and previewing and playing the multimedia streaming data.
    Type: Application
    Filed: May 19, 2016
    Publication date: November 24, 2016
    Inventors: Xiaobin WANG, Bo LI, Shengkai WANG, Xizhe XIAO, Shixing LI, Liang LI