Abstract: A sampling phase adjustment device and an adjusting method thereof are disclosed. Sampling phase adjustment device includes feedback summer, adaptive equalizer unit, clock and data recovery (CDR) circuit, data slicer, error slicer, sample calculator unit and enable circuit. The adjusting method is as follows: the data slicer and error slicer receive a sum value generated from the feedback summer, and generate a data signal and an error signal, respectively. The adaptive equalizer unit provides an equalizing signal to the feedback summer and a reference signal to the error slicer. The sample calculator unit generates a sampling adjustment signal based on the data signal and error signal. The CDR circuit is configured to output and adjust a clock signal based on the sampling adjustment signal and data signal. The enable circuit enables the adaptive equalizer unit and the sample calculator unit alternatively.

Abstract: A method includes providing a substrate having a gate structure over a first side of the substrate, forming a recess adjacent to the gate structure, and forming in the recess a first semiconductor layer having a dopant, the first semiconductor layer being non-conformal, the first semiconductor layer lining the recess and extending from a bottom of the recess to a top of the recess. The method further includes forming a second semiconductor layer having the dopant in the recess and over the first semiconductor layer, a second concentration of the dopant in the second semiconductor layer being higher than a first concentration of the dopant in the first semiconductor layer.

Abstract: Structures and formation methods of a semiconductor device are provided. The semiconductor device structure includes a substrate and a gate structure over the substrate. The semiconductor device structure also includes a source/drain structure near the gate structure. The source/drain structure has an inner portion and an outer portion surrounding an entirety of the inner portion. The inner portion has a greater average dopant concentration than that of the outer portion.

Abstract: A method of assisted takeoff of a movable object includes increasing output to an actuator that drives a propulsion unit of the movable object under a first feedback control scheme, determining whether the movable object has met a takeoff threshold, and controlling the output to the actuator using a second feedback control scheme different from the first feedback control scheme in response to the movable object having met the takeoff threshold.

Abstract: A method for patterning a substrate including multiple layers using a sulfur-based mask includes providing a substrate including a first layer and a second layer arranged on the first layer. The first layer includes a material selected from a group consisting of germanium, silicon germanium and type III/V materials. The method includes depositing a mask layer including sulfur species on sidewalls of the first layer and the second layer by exposing the substrate to a first wet chemistry. The method includes removing the mask layer on the sidewalls of the second layer while not completely removing the mask layer on the sidewalls of the first layer by exposing the substrate to a second wet chemistry. The method includes selectively etching the second layer relative to the first layer and the mask layer on the sidewalls of the first layer by exposing the substrate to a third wet chemistry.

Abstract: The present disclosure relates to treatment of a pulmonary disease. The methods and kits provided herein facilitate relieving the symptoms resulting from the pulmonary disease (e.g., asthma, chronic obstructive pulmonary disease (COPD), etc.).

Abstract: The application provides methods of treating or reducing thrombocytopenia, leukopenia, anemia, or neutropenia in a patient in need thereof, comprising the step of administering an effective amount of a compound selected from Compounds 1-6, disclosed herein.

Abstract: Structures and formation methods of a semiconductor device are provided. The semiconductor device structure includes a substrate and a gate structure over the substrate. The semiconductor device structure also includes a source/drain structure near the gate structure. The source/drain structure has an inner portion and an outer portion surrounding an entirety of the inner portion. The inner portion has a greater average dopant concentration than that of the outer portion.

Abstract: A method suitable for a head mounted device. The method includes: sensing a rotational data of the head mounted device; generating a tangling prediction according to a continuous degree of the rotational data; determining a cable tangling parameter according to the tangling prediction; determining that whether a cable is going to tangle according to the cable tangling parameter; and adjusting a virtual reality content when the cable is going to tangle.

Abstract: An adjustable signal equalization device includes an equalizer circuitry, an analog-to-digital converter (ADC), a calculation circuitry, and a comparator circuitry. The equalizer circuitry has a transfer function, and processes an input signal based on the transfer function to generate an output signal. The ADC generates a digital signal according to the output signal. The calculation circuitry performs an accumulation according to the first digital signal to generate a first accumulated value and a second accumulated value, and generates a first detection signal and a second detection signal according to the first accumulated value and the second accumulated value. The comparator circuitry compares the first detection signal with the second detection signal to output a control signal to the equalizer circuit if the first detection signal is different from the second detection signal, in order to adjust the transfer function.

Abstract: Systems, methods, and devices are provided for assisted takeoff of an aerial vehicle. The aerial vehicle may takeoff using a first control scheme and switch to a second control scheme for normal flight when a takeoff threshold is met. The first control scheme optionally does not use integral control while the second control scheme may use integral control. The aerial vehicle may determine that a takeoff threshold is met, based on an output to a motor of the aerial vehicle and/or an acceleration of the aerial vehicle.

Abstract: Tin oxide films are used as spacers and hardmasks in semiconductor device manufacturing. In one method, tin oxide layer is formed conformally over sidewalls and horizontal surfaces of protruding features on a substrate. A passivation layer is then formed over tin oxide on the sidewalls, and tin oxide is then removed from the horizontal surfaces of the protruding features without being removed at the sidewalls of the protruding features. The material of the protruding features is then removed while leaving the tin oxide that resided at the sidewalls of the protruding features, thereby forming tin oxide spacers. Hydrogen-based and chlorine-based dry etch chemistries are used to selectively etch tin oxide in a presence of a variety of materials. In another method a patterned tin oxide hardmask layer is formed on a substrate by forming a patterned layer over an unpatterned tin oxide and transferring the pattern to the tin oxide.

Abstract: A method, a virtual reality apparatus and a recording medium for displaying fast moving frames of virtual reality are provided. The method is adapted to a virtual reality apparatus including a head-mounted display (HMD), a locator and a computing device. In the method, the computing device executes an application of virtual reality, and displays frames of the application on the HMD. When fast moving of the frames of the application is about to be occurred, the computing device prompts the fast moving to guide a user wearing the HMD to turn a line of sight to a direction of gravity, and then fast moves a field of view of the frames to the direction of gravity.

Abstract: Methods of etching and smoothening films by exposing to a halogen-containing plasma and an inert plasma within a bias window in cycles are provided. Methods are suitable for etching and smoothening films of various materials in the semiconductor industry and are also applicable to applications in optics and other industries.

Abstract: Provided herein are methods and related apparatus that facilitate patterning by performing highly non-conformal (directional) deposition on patterned structures. The methods involve depositing films on a patterned structure, such as a hard mask. The deposition may be both substrate-selective such that the films have high etch selectivity with respect to an underlying material to be etched and pattern-selective such that the films are directionally deposited to replicate the pattern of the patterned structure. In some embodiments, the deposition is performed in the same chamber as a subsequent etch is performed. In some embodiments, the deposition may be performed in a separate chamber (e.g., a PECVD deposition chamber) that is connected to the etch chamber by a vacuum transfer chamber. The deposition may be performed prior to or at selected intermittences during at etch process. In some embodiments, the deposition involves multiple cycles of a deposition and treatment process.

Abstract: The present disclosure relates to treatment of a pulmonary disease. The methods and kits provided herein facilitate relieving the symptoms resulting from the pulmonary disease (e.g., asthma, chronic obstructive pulmonary disease (COPD), etc.).

Abstract: A method for patterning a substrate including multiple layers using a sulfur-based mask includes providing a substrate including a first layer and a second layer arranged on the first layer. The first layer includes a material selected from a group consisting of germanium, silicon germanium and type III/V materials. The method includes depositing a mask layer including sulfur species on sidewalls of the first layer and the second layer by exposing the substrate to a first wet chemistry. The method includes removing the mask layer on the sidewalls of the second layer while not completely removing the mask layer on the sidewalls of the first layer by exposing the substrate to a second wet chemistry. The method includes selectively etching the second layer relative to the first layer and the mask layer on the sidewalls of the first layer by exposing the substrate to a third wet chemistry.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a substrate, a first source portion and a first drain portion over the substrate, and a first semiconductor nanowire over the substrate and between the first source portion and the first drain portion. The first semiconductor nanowire includes a first portion over the substrate and a second portion over the first portion, and the first portion has a first width, and the second portion has a second width, and the second width is less than the first width. The semiconductor device structure also includes a first gate structure over the second portion of the first semiconductor nanowire.

Abstract: Structures of a semiconductor device are provided. The semiconductor device includes a substrate, a gate structure over the substrate, and a first recess and a second recess in the substrate and at opposite sides of the gate structure. The semiconductor device also includes two source/drain structures over the first recess and the second recess respectively. At least one of the source/drain structures includes a first doped region partially filling in the first recess, a second doped region over the first doped region, and a third doped region over the second doped region. The second doped region contains more dopants than the first doped region or the third doped region.

Abstract: A semiconductor device and method includes: forming a gate stack over a substrate; growing a source/drain region adjacent the gate stack, the source/drain region being n-type doped Si; growing a semiconductor cap layer over the source/drain region, the semiconductor cap layer having Ge impurities, the source/drain region free of the Ge impurities; depositing a metal layer over the semiconductor cap layer; annealing the metal layer and the semiconductor cap layer to form a silicide layer over the source/drain region, the silicide layer having the Ge impurities; and forming a metal contact electrically coupled to the silicide layer.