Patents by Inventor Yang Pan

Yang Pan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220011228
    Abstract: A method and apparatus for surface plasmon resonance imaging are provided for imaging the surface plasmon resonance signals caused by the interaction of biomolecules. In particular, the method and apparatus can image the slightly spectral change in a surface plasmon resonance mode by comparing the light intensities of two bands in the frequency domain of the surface plasmon.
    Type: Application
    Filed: October 3, 2019
    Publication date: January 13, 2022
    Inventors: Pei-Kuen WEI, Ming-Yang PAN, Kuang-Li LEE
  • Patent number: 11204611
    Abstract: A method of assisted takeoff of a movable object includes increasing output to an actuator that drives a propulsion unit of the movable object under a first feedback control scheme, determining whether the movable object has met a takeoff threshold, and controlling the output to the actuator using a second feedback control scheme different from the first feedback control scheme in response to the movable object having met the takeoff threshold.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: December 21, 2021
    Assignee: SZ DJI TECHNOLOGY CO., LTD.
    Inventors: Jun Shi, Xu Yang Pan
  • Publication number: 20210391355
    Abstract: A three-dimensional (3D) memory structure includes memory cells and a plurality of oxide layers and a plurality of word line layers. The plurality of oxide layers and the plurality of word line layers are alternately stacked in a first direction. A plurality of double channel holes extend through the plurality of oxide layers and the plurality of word line layers in the first direction. The plurality of double channel holes have a peanut-shaped cross-section in a second direction that is transverse to the first direction.
    Type: Application
    Filed: October 22, 2019
    Publication date: December 16, 2021
    Inventors: Thorsten LILL, Meihua SHEN, John HOANG, Hui-Jung WU, Gereng GUNAWAN, Yang PAN
  • Publication number: 20210359111
    Abstract: In a method of manufacturing a semiconductor device, a fin structure having a channel region protruding from an isolation insulating layer disposed over a semiconductor substrate is formed, a cleaning operation is performed, and an epitaxial semiconductor layer is formed over the channel region. The cleaning operation and the forming the epitaxial semiconductor layer are performed in a same chamber without breaking vacuum.
    Type: Application
    Filed: December 2, 2020
    Publication date: November 18, 2021
    Inventors: Ya-Wen CHIU, Yi Che CHAN, Lun-Kuang TAN, Zheng-Yang PAN, Cheng-Po CHAU, Pin-Ju LIANG, Hung-Yao CHEN, De-Wei YU, Yi-Cheng LI
  • Patent number: 11171220
    Abstract: A method of forming a gate dielectric material includes forming a high-K dielectric material in a first region over a substrate, where forming the high-K dielectric material includes forming a first dielectric layer comprising hafnium over the substrate, and forming a second dielectric layer comprising lanthanum over the first dielectric layer.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: November 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shahaji B. More, Cheng-Han Lee, Zheng-Yang Pan, Shih-Chieh Chang, Chun-Chieh Wang
  • Patent number: 11152362
    Abstract: A fin field effect transistor (FinFET) device structure and method for forming the same are provided. The FinFET device structure includes a fin structure extending above a substrate, and the fin structure has a first portion and a second portion below the first portion, and the first portion and the second portion are made of different materials. The FinFET device structure includes an isolation structure formed on the substrate, and an interface between the first portion and the second portion of the fin structure is above a top surface of the isolation structure. The FinFET device structure includes a liner layer formed on sidewalls of the second portion of the fin structure.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: October 19, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Chieh Wang, Zheng-Yang Pan, Yi-Min Huang, Shih-Chieh Chang, Tsung-Lin Lee
  • Publication number: 20210272814
    Abstract: A method for selectively etching silicon germanium with respect to silicon in a stack on a chuck in an etch chamber is provided. The chuck is maintained at a temperature below 15° C. The stack is exposed to an etch gas comprising a fluorine containing gas to selectively etch silicon germanium with respect to silicon.
    Type: Application
    Filed: July 12, 2019
    Publication date: September 2, 2021
    Inventors: Daniel PETER, Jun XUE, Samantha SiamHwa TAN, Yang PAN, Younghee LEE, Alexander KABANSKY
  • Publication number: 20210265173
    Abstract: Tin oxide films are used as mandrels in semiconductor device manufacturing. In one implementation the process starts by patterning a tin oxide layer using at least one of a hydrogen-based etch chemistry and a chlorine-based etch chemistry, and using patterned photoresist as a mask, thereby providing a substrate having a plurality of protruding tin oxide features (mandrels). Next, a conformal layer of spacer material is formed both on the horizontal surfaces and on the sidewalls of the mandrels. The spacer material is then removed from the horizontal surfaces exposing the tin oxide material of the mandrels, without fully removing the spacer material residing at the sidewalls of the mandrels. Next, mandrels are selectively removed (e.g., using hydrogen-based etch chemistry), while leaving the spacer material that resided at the sidewalls of the mandrels. The resulting spacers can be used for patterning underlying layers on the substrate.
    Type: Application
    Filed: May 13, 2021
    Publication date: August 26, 2021
    Inventors: Jengyi Yu, Samantha S.H. Tan, Seongjun Heo, Boris Volosskiy, Sivananda Krishnan Kanakasabapathy, Richard Wise, Yang Pan, Hui-Jung Wu
  • Publication number: 20210265163
    Abstract: Tin oxide film on a semiconductor substrate is etched selectively in a presence of photoresist by exposing the substrate to at least one of hydrogen-based chemistry and chlorine-based chemistry. In some implementations, a method of processing a semiconductor substrate starts by providing a semiconductor substrate having a patterned photoresist layer overlying a tin oxide layer. Next, openings are etched in the tin oxide layer using the patterned photoresist layer as a mask, and using at least one of a hydrogen-based etch chemistry and a chlorine-based etch chemistry. After the openings have been etched in the tin oxide layer, the photoresist layer is removed using an oxygen-based etch chemistry.
    Type: Application
    Filed: May 13, 2021
    Publication date: August 26, 2021
    Inventors: Jengyi Yu, Samantha S.H. Tan, Yu Jiang, Hui-Jung Wu, Richard Wise, Yang Pan, Nader Shamma, Boris Volosskiy
  • Publication number: 20210257263
    Abstract: A method includes forming a gate stack of a transistor. The formation of the gate stack includes forming a silicon oxide layer on a semiconductor region, depositing a hafnium oxide layer over the silicon oxide layer, depositing a lanthanum oxide layer over the hafnium oxide layer, and depositing a work-function layer over the lanthanum oxide layer. Source/drain regions are formed on opposite sides of the gate stack.
    Type: Application
    Filed: April 16, 2021
    Publication date: August 19, 2021
    Inventors: Shahaji B. More, Zheng-Yang Pan, Shih-Chieh Chang, Chun Chieh Wang
  • Publication number: 20210242032
    Abstract: Various embodiments herein relate to methods, apparatus, and systems for etching a feature in a substrate. Typically the feature is etched in a dielectric-containing stack. The etching process involves cyclically etching the feature and depositing a protective film on sidewalls of the partially etched feature. These stages are repeated until the feature reaches its final depth. The protective film may have a particular composition, for example including at least one of a tungsten carbonitride, a tungsten sulfide, tin, a tin-containing compound, molybdenum, a molybdenum-containing compound, a ruthenium carbonitride, a ruthenium sulfide, an aluminum carbonitride, an aluminum sulfide, zirconium, and a zirconium-containing compound. A number of optional steps may be taken including, for example, doping the mask layer, pre-treating the substrate prior to deposition, removing the protective film from the sidewalls, and oxidizing any remaining protective film.
    Type: Application
    Filed: August 19, 2019
    Publication date: August 5, 2021
    Inventors: Karthik S. COLINJIVADI, Samantha SiamHwa TAN, Shih-Ked LEE, George MATAMIS, Yongsik YU, Yang PAN, Patrick VAN CLEEMPUT, Akhil SINGHAL, Juwen GAO, Raashina HUMAYUN
  • Publication number: 20210238318
    Abstract: Disclosed is a composite functional resin, having the basic structure of Formula (I) and/or Formula (II), wherein AX is a quaternary ammonium group. In view of the problems that the existing resins have poor anti-interference ability, and poor ability to remove dissolved organic matter, disinfection by-product precursors, and anions such as nitrate, sulfate, phosphate and arsenate in water while sterilizing, the composite functional resin of the present invention has the ability to efficiently remove dissolved organic matter, disinfection by-product precursors, and anions such as nitrate, sulfate, phosphate, and arsenate in water, and has the advantages of efficient sterilization and high anti-interference ability. The composite functional resin can be applied in sterilization and water treatment.
    Type: Application
    Filed: October 24, 2018
    Publication date: August 5, 2021
    Inventors: Peng SHI, Huaicheng ZHANG, Aimin LI, Fangyu CHANG, Qing ZHOU, Chendong SHUANG, Qimeng LI, Yang PAN
  • Patent number: 11068058
    Abstract: An immersive system includes a processing device. The processing device is communicated with an interface device and an electronic display in a head mounted display device. The interface device includes a haptic feedback circuit. The haptic feedback circuit is configured to induce a haptic feedback. The interface device includes a haptic feedback circuit. The haptic feedback circuit is configured to induce a haptic feedback. The processing device is configured to provide an immersive content to the electronic display. The processing device is configured to identify a simulated object corresponding to the interface device in the immersive content, and identify an interaction event occurring to the simulated object in the immersive content. The processing device is configured to determine a vibration pattern according to the interaction event and the simulated object, and control the haptic feedback circuit to induce the haptic feedback according to the vibration pattern.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: July 20, 2021
    Assignee: HTC Corporation
    Inventor: Sheng-Yang Pan
  • Patent number: 11011433
    Abstract: A method includes forming a gate stack of a transistor. The formation of the gate stack includes forming a silicon oxide layer on a semiconductor region, depositing a hafnium oxide layer over the silicon oxide layer, depositing a lanthanum oxide layer over the hafnium oxide layer, and depositing a work-function layer over the lanthanum oxide layer. Source/drain regions are formed on opposite sides of the gate stack.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: May 18, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shahaji B. More, Zheng-Yang Pan, Shih-Chieh Chang, Chun-Chieh Wang
  • Publication number: 20210118740
    Abstract: A semiconductor device and method includes: forming a gate stack over a substrate; growing a source/drain region adjacent the gate stack, the source/drain region being n-type doped Si; growing a semiconductor cap layer over the source/drain region, the semiconductor cap layer having Ge impurities, the source/drain region free of the Ge impurities; depositing a metal layer over the semiconductor cap layer; annealing the metal layer and the semiconductor cap layer to form a silicide layer over the source/drain region, the silicide layer having the Ge impurities; and forming a metal contact electrically coupled to the silicide layer.
    Type: Application
    Filed: December 28, 2020
    Publication date: April 22, 2021
    Inventors: Shahaji B. More, Zheng-Yang Pan, Cheng-Han Lee, Shih-Chieh Chang
  • Patent number: 10979617
    Abstract: A control method suitable for a mobile device comprising a camera includes operations as follows: obtaining a description of a first wireless device adjacent to the mobile device through a wireless communication packet; capturing a first image of a physical environment by the camera; recognizing a first candidate object within the first image; matching the first candidate object with the description of the first wireless device; and in response to that the first candidate object matches with the description of the first wireless device and a first predetermined instruction is received, generating a first command according to the description of the first wireless device, wherein the first command is to be transmitted to the first wireless device over a wireless communication for manipulating the first wireless device.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: April 13, 2021
    Assignee: HTC Corporation
    Inventor: Sheng-Yang Pan
  • Publication number: 20210005425
    Abstract: Etching a refractory metal or other high surface binding energy material on a substrate can maintain or increase the smoothness of the metal/high EO surface, in some cases produce extreme smoothing. A substrate having an exposed refractory metal/high EO surface is provided. The refractory metal/high EO surface is exposed to a modification gas to modify the surface and form a modified refractory metal/high EO surface. The modified refractory metal/high EO surface is exposed to an energetic particle to preferentially remove the modified refractory metal/high EO surface relative to an underlying unmodified refractory metal/high EO surface such that the exposed refractory metal/high EO surface after removing the modified refractory metal/high EO surface is as smooth or smoother than the substrate surface before exposing the substrate surface to the modification gas.
    Type: Application
    Filed: March 15, 2019
    Publication date: January 7, 2021
    Inventors: Wenbing Yang, Tamal Mukherjee, Mohand Brouri, Samantha Tan, Yang Pan, Keren Jacobs Kanarik
  • Publication number: 20210005472
    Abstract: A method for etching features in a stack below a patterned mask in an etch chamber is provided. The stack is cooled with a coolant with a coolant temperature below ?20° C. An etch gas is flowed into the etch chamber. A plasma is generated from the etch gas. Features are selectively etched into the stack with respect to the patterned mask.
    Type: Application
    Filed: March 12, 2019
    Publication date: January 7, 2021
    Inventors: Keren J. KANARIK, Samantha SiamHwa TAN, Yang PAN, Jeffrey MARKS
  • Patent number: 10885253
    Abstract: A virtual fabrication environment for semiconductor device fabrication that determines a lowest lithography exposure dose range in which one or more defects are still reparable by deposition and etch operations is discussed. Further techniques for repairing line edge roughness caused by lithography are described.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: January 5, 2021
    Assignee: Coventor, Inc.
    Inventors: Daniel Sobieski, Rich Wise, Yang Pan, David M. Fried, Jiangjiang Gu
  • Patent number: 10879126
    Abstract: A semiconductor device and method includes: forming a gate stack over a substrate; growing a source/drain region adjacent the gate stack, the source/drain region being n-type doped Si; growing a semiconductor cap layer over the source/drain region, the semiconductor cap layer having Ge impurities, the source/drain region free of the Ge impurities; depositing a metal layer over the semiconductor cap layer; annealing the metal layer and the semiconductor cap layer to form a silicide layer over the source/drain region, the silicide layer having the Ge impurities; and forming a metal contact electrically coupled to the silicide layer.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shahaji B. More, Zheng-Yang Pan, Cheng-Han Lee, Shih-Chieh Chang