Patents by Inventor Yasuhisa Yamamoto
Yasuhisa Yamamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170302300Abstract: A communication unit includes the following elements. A first transmit circuit outputs a first signal or a second signal from a first input signal. A first amplifier amplifies the first signal and outputs a first amplified signal. A first signal generating circuit generates a third signal having a frequency higher than a frequency of the second signal, based on the second signal and a first reference signal. A first filter circuit receives the third signal and allows one of a frequency component representing a sum of the frequency of the second signal and a frequency of the first reference signal and a frequency component representing a difference therebetween to pass through the first filter circuit and attenuates the other one of the frequency components. A second amplifier amplifies the third signal output from the first filter circuit and outputs a second amplified signal.Type: ApplicationFiled: April 18, 2017Publication date: October 19, 2017Inventors: Satoshi TANAKA, Kazuo WATANABE, Tetsuaki ADACHI, Masahito NUMANAMI, Yasuhisa YAMAMOTO
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Publication number: 20170302301Abstract: A communication unit includes the following elements. A first transmit circuit outputs a first signal or a second signal from a first input signal. A first amplifier amplifies the first signal and outputs a first amplified signal. A first signal generating circuit generates a third signal having a frequency higher than a frequency of the second signal, based on the second signal and a first reference signal. A first filter circuit receives the third signal and allows one of a frequency component representing a sum of the frequency of the second signal and a frequency of the first reference signal and a frequency component representing a difference therebetween to pass through the first filter circuit and attenuates the other one of the frequency components. A second amplifier amplifies the third signal output from the first filter circuit and outputs a second amplified signal.Type: ApplicationFiled: April 18, 2017Publication date: October 19, 2017Inventors: Satoshi TANAKA, Kazuo WATANABE, Tetsuaki ADACHI, Masahito NUMANAMI, Yasuhisa YAMAMOTO
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Patent number: 8937741Abstract: A multi-function printer main body has a copy function. A remote terminal conducts various kinds of copy settings or instructions to start copy. An execution button is provided in the multi-function printer main body. When the execution button is operated in normal time, copy is executed with the default settings. When copy is executed by inputting copy settings on the remote terminal side, copy can be executed again with the copy settings used for the last time by operating the execution button until a predetermined period of time passes. Therefore, in a case of executing copy with the default settings or repeatedly executing copy with the same settings as the settings used for the last time, a user's work burden can be reduced because it is sufficient for the user to operate the execution button 38.Type: GrantFiled: May 28, 2013Date of Patent: January 20, 2015Assignee: Seiko Epson CorporationInventor: Yasuhisa Yamamoto
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Publication number: 20130321840Abstract: A multi-function printer main body has a copy function. A remote terminal conducts various kinds of copy settings or instructions to start copy. An execution button is provided in the multi-function printer main body. When the execution button is operated in normal time, copy is executed with the default settings. When copy is executed by inputting copy settings on the remote terminal side, copy can be executed again with the copy settings used for the last time by operating the execution button until a predetermined period of time passes. Therefore, in a case of executing copy with the default settings or repeatedly executing copy with the same settings as the settings used for the last time, a user's work burden can be reduced because it is sufficient for the user to operate the execution button 38.Type: ApplicationFiled: May 28, 2013Publication date: December 5, 2013Applicant: SEIKO EPSON CORPORATIONInventor: Yasuhisa YAMAMOTO
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Patent number: 8316329Abstract: Double patterning is achieved with a single reticle while maintaining the integrity of in-scribe patterns and without blading the reticle. In-scribe structures may or may not be double patterning. For example, elements such as electrical test structures might have features that are so closely spaced that double pattering is desired. However, elements such as optical alignment marks might not require double patterning. For those elements for which double patterning is not desired, a first sub-array of the reticle has a pattern for the element, whereas the corresponding location in a second sub-array has a blank. By the corresponding location, it is meant the location on the reticle that would be exposed to the same target region to which the element would be exposed if the reticle were used for double patterning. Thus, the blank prevents target region from being exposed more than once.Type: GrantFiled: December 21, 2010Date of Patent: November 20, 2012Assignee: Cadence Design Systems, Inc.Inventors: Rodney Rigby, James Frisby, Aaron Parr, Yasuhisa Yamamoto
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Patent number: 8117816Abstract: The present application of the invention aims at improving knot strength of a twisted yarn without compromising circularity, with respect to various yarns including a fishing line. For such purpose, the present application of the invention provides a yarn including a multifilament subjected to two twisting processes in different directions, and a coating resin that covers a surface of the multifilament; wherein the multifilament is subjected to a first twist in one direction, and then to a second twist in a direction opposite to that of the first twist, without being doubled with another yarn.Type: GrantFiled: February 16, 2006Date of Patent: February 21, 2012Assignee: Duel Co., Inc.Inventors: Yasuhisa Yamamoto, Eric Eun-Ha Choi
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Patent number: 8071278Abstract: Double patterning using a single reticle. A blading technique may be used to allow a single reticle to be used for double patterning. The reticle is placed into a lithographic apparatus and a first portion of the pattern is exposed onto a first photoresist overlaying a target region, while blading the second portion of the pattern. Then, a second portion of the pattern is exposed onto a second photoresist, while blading the first portion. Alternatively, each portion of the pattern may be exposed to the photoresist simultaneously, but to different target regions. Then shot coordinates are adjusted and the portions are exposed to a photoresist again to allow creation of the composite pattern in at least one of the target regions. During the double patterning process, the reticle may be kept in the lithographic apparatus.Type: GrantFiled: April 16, 2007Date of Patent: December 6, 2011Assignee: Cadence Design Systems, Inc.Inventor: Yasuhisa Yamamoto
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Patent number: 7879537Abstract: Double patterning is achieved with a single reticle while maintaining the integrity of in-scribe patterns and without blading the reticle. In-scribe structures may or may not be double patterning. For example, elements such as electrical test structures might have features that are so closely spaced that double pattering is desired. However, elements such as optical alignment marks might not require double patterning. For those elements for which double patterning is not desired, a first sub-array of the reticle has a pattern for the element, whereas the corresponding location in a second sub-array has a blank. By the corresponding location, it is meant the location on the reticle that would be exposed to the same target region to which the element would be exposed if the reticle were used for double patterning. Thus, the blank prevents target region from being exposed more than once.Type: GrantFiled: August 27, 2007Date of Patent: February 1, 2011Assignee: Cadence Design Systems, Inc.Inventors: Rodney Rigby, James Frisby, Aaron Parr, Yasuhisa Yamamoto
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Publication number: 20100289798Abstract: An image processing method includes: obtaining image portrayal information representing a relationship between coordinates of a rendered image obtained by performing rendering with a texture attached to a 3-dimensional model and coordinates of the texture and a relationship between colors of each pixel of the rendered image and colors of each pixel of the texture; and compressing the image portrayal information representing a relationship between coordinates of the rendered image and coordinates of the texture using a linear compression scheme.Type: ApplicationFiled: May 12, 2010Publication date: November 18, 2010Applicant: SEIKO EPSON CORPORATIONInventors: Yasuhiro Furuta, Yasuhisa Yamamoto
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Publication number: 20100229521Abstract: The present application of the invention aims at improving knot strength of a twisted yarn without compromising circularity, with respect to various yarns including a fishing line. For such purpose, the present application of the invention provides a yarn including a multifilament subjected to two twisting processes in different directions, and a coating resin that covers a surface of the multifilament; wherein the multifilament is subjected to a first twist in one direction, and then to a second twist in a direction opposite to that of the first twist, without being doubled with another yarn.Type: ApplicationFiled: February 16, 2006Publication date: September 16, 2010Inventors: Yasuhisa Yamamoto, Eric Eun-Ha Choi
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Publication number: 20100013845Abstract: An image display apparatus which includes an image memory for storing a synthetic image obtained by synthesizing a plurality of layer images and which displays the synthetic image stored in the image memory on a display unit.Type: ApplicationFiled: July 15, 2009Publication date: January 21, 2010Applicant: SEIKO EPSON CORPORATIONInventor: Yasuhisa Yamamoto
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Patent number: 7458652Abstract: If data, which is irrelevant to recording data, is stored in a lower address of head word data of the run length compressed recording data stored in a receiving buffer unit, the irrelevant byte data of the lower address of the word data including the head byte data is nullified by masking to be developed by a decode circuit. Otherwise, in regard to a bitmap area of a local memory which is a DMA transfer destination, transfer addresses are individually set by a development processing controller in a DECU per one word of the developed recording data stored in the line buffer in order that data of one line is arranged and stored in a vertical direction, or data of one line is stored in image 1 and image 2 in turn. Otherwise, in regard to the development processing controller, when the recording data developed by the decode circuit is stored in the line buffer, it is stored from a first byte in a state where a 0-th byte of the line buffer is vacant.Type: GrantFiled: April 19, 2006Date of Patent: December 2, 2008Assignee: Seiko Epson CorporationInventors: Masahiro Kimura, Yasunori Fukumitsu, Yasuhisa Yamamoto, Masahiro Igarashi
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Patent number: 7167932Abstract: Compressed recording data is DMA-transferred to a receiving buffer unit via a system bus one word each. It is DMA-transferred from the receiving buffer unit to a DECU via the system bus. It is developed based on hardware by a decode circuit in the DECU, and stored in a line buffer. It is DMA-transferred to a local memory via a local bus when it reaches predetermined bytes. The recording data stored in the local memory is DMA-transferred to the DECU via the local bus, DMA-transferred to a head controlling unit and DMA-transferred to a recording head.Type: GrantFiled: August 26, 2003Date of Patent: January 23, 2007Assignee: Seiko Epson CorporationInventors: Masahiro Kimura, Yasunori Fukumitsu, Yasuhisa Yamamoto, Masahiro Igarashi
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Publication number: 20060187248Abstract: If data, which is irrelevant to recording data, is stored in a lower address of head word data of the run length compressed recording data stored in a receiving buffer unit, the irrelevant byte data of the lower address of the word data including the head byte data is nullified by masking to be developed by a decode circuit. Otherwise, in regard to a bitmap area of a local memory which is a DMA transfer destination, transfer addresses are individually set by a development processing controller in a DECU per one word of the developed recording data stored in the line buffer in order that data of one line is arranged and stored in a vertical direction, or data of one line is stored in image 1 and image 2 in turn. Otherwise, in regard to the development processing controller, when the recording data developed by the decode circuit is stored in the line buffer, it is stored from a first byte in a state where a 0-th byte of the line buffer is vacant.Type: ApplicationFiled: April 19, 2006Publication date: August 24, 2006Applicant: Seiko Epson CorporationInventors: Masahiro Kimura, Yasunori Fukumitsu, Yasuhisa Yamamoto, Masahiro Igarashi
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Patent number: 7083244Abstract: If data, which is irrelevant to recording data, is stored in a lower address of head word data of the run length compressed recording data stored in a receiving buffer unit, the irrelevant byte data of the lower address of the word data including the head byte data is nullified by masking to be developed by a decode circuit. Otherwise, in regard to a bitmap area of a local memory which is a DMA transfer destination, transfer addresses are individually set by a development processing controller in a DECU per one word of the developed recording data stored in the line buffer in order that data of one line is arranged and stored in a vertical direction, or data of one line is stored in image 1 and image 2 in turn. Otherwise, in regard to the development processing controller, when the recording data developed by the decode circuit is stored in the line buffer, it is stored from a first byte in a state where a 0-th byte of the line buffer is vacant.Type: GrantFiled: August 26, 2003Date of Patent: August 1, 2006Assignee: Seiko Epson CorporationInventors: Masahiro Kimura, Yasunori Fukumitsu, Yasuhisa Yamamoto, Masahiro Igarashi
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Patent number: 6878429Abstract: A sealing member for sealing a slenderly extending developer outflow opening formed in a container accommodating a developer. The sealing member includes a first film strip formed from a longitudinally stretched plastic film, and a second film strip formed from a similarly longitudinally stretched plastic film. The first film strip and the second film strip are bonded to each other as required.Type: GrantFiled: June 25, 2002Date of Patent: April 12, 2005Assignee: Shirasaki CorporationInventors: Hirotaka Shirasaki, Yozo Okawa, Yasuhisa Yamamoto, Daisuke Wakabayashi
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Publication number: 20040143611Abstract: If data, which is irrelevant to recording data, is stored in a lower address of head word data of the run length compressed recording data stored in a receiving buffer unit, the irrelevant byte data of the lower address of the word data including the head byte data is nullified by masking to be developed by a decode circuit. Otherwise, in regard to a bitmap area of a local memory which is a DMA transfer destination, transfer addresses are individually set by a development processing controller in a DECU per one word of the developed recording data stored in the line buffer in order that data of one line is arranged and stored in a vertical direction, or data of one line is stored in image 1 and image 2 in turn. Otherwise, in regard to the development processing controller, when the recording data developed by the decode circuit is stored in the line buffer, it is stored from a first byte in a state where a 0-th byte of the line buffer is vacant.Type: ApplicationFiled: August 26, 2003Publication date: July 22, 2004Inventors: Masahiro Kimura, Yasunori Fukumitsu, Yasuhisa Yamamoto, Masahiro Igarashi
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Publication number: 20040083313Abstract: Compressed recording data is DMA-transferred to a receiving buffer unit via a system bus one word each. It is DMA-transferred from the receiving buffer unit to a DECU via the system bus. It is developed based on hardware by a decode circuit in the DECU, and stored in a line buffer. It is DMA-transferred to a local memory via a local bus when it reaches predetermined bytes. The recording data stored in the local memory is DMA-transferred to the DECU via the local bus, DMA-transferred to a head controlling unit and DMA-transferred to a recording head.Type: ApplicationFiled: August 26, 2003Publication date: April 29, 2004Inventors: Masahiro Kimura, Yasunori Fukumitsu, Yasuhisa Yamamoto, Masahiro Igarashi
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Publication number: 20030096080Abstract: A sealing member for sealing a slenderly extending developer outflow opening formed in a container accommodating a developer. The sealing member includes a first film strip formed from a longitudinally stretched plastic film, and a second film strip formed from a similarly longitudinally stretched plastic film. The first film strip and the second film strip are bonded to each other as required.Type: ApplicationFiled: June 25, 2002Publication date: May 22, 2003Inventors: Hirotaka Shirasaki, Yozo Okawa, Yasuhisa Yamamoto, Daisuke Wakabayashi