Patents by Inventor Yasuhito Yoshimizu

Yasuhito Yoshimizu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210265386
    Abstract: A semiconductor storage device includes a stacked body, a first columnar portion, a second columnar portion, and second insulating layers. The stacked body includes a plurality of conductive layers and a plurality of first insulating layers alternately stacked in a first direction. The first columnar portion being in a first region, and the second columnar portion being in a second region. The first columnar penetrates the stacked body in the first direction and includes a semiconductor layer. The second columnar portion penetrates the stacked body in the first direction and includes an insulating layer thereon. The second insulating layers are between the second columnar portion and either the conductive layers or the first insulating layers. The insulating layer on the second columnar portion. The second insulating layers are between the insulating layer on the second columnar portion and one of the conductive layers or the first insulating layers.
    Type: Application
    Filed: August 28, 2020
    Publication date: August 26, 2021
    Inventor: Yasuhito YOSHIMIZU
  • Publication number: 20210149568
    Abstract: According to one embodiment, a storage device includes a stage on which a semiconductor wafer can be mounted, wherein data is capable of being read from the semiconductor wafer or data is capable of being written to the semiconductor wafer. The storage device further includes a plurality of probe pins for reading or writing data, and a controller connected the probe pins. The semiconductor wafer includes electrodes connectable to the probe pins, a first memory area that can store user data, and a second memory area that can store identification information for identification of the semiconductor wafer and a check code for checking integrity of the identification information. The controller is capable of reading the identification information and the check code from the second memory area.
    Type: Application
    Filed: December 14, 2020
    Publication date: May 20, 2021
    Applicant: Kioxia Corporation
    Inventors: Yasuhito YOSHIMIZU, Takashi FUKUSHIMA, Tatsuro HITOMI, Arata INOUE, Masayuki MIURA, Shinichi KANNO, Toshio FUJISAWA, Keisuke NAKATSUKA, Tomoya SANUKI
  • Publication number: 20210090913
    Abstract: According to an embodiment, a substrate treatment apparatus includes a hair member including a noble metal, and a liquid chemical supply member to supply a liquid chemical. While a tip part of the hair member is contact with a predetermined surface of a metal, the liquid chemical is supplied onto the surface of the metal, and the metal is removed with etching.
    Type: Application
    Filed: November 17, 2020
    Publication date: March 25, 2021
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Yasuhito YOSHIMIZU, Yuya AKEBOSHI, Fuyuma ITO, Hakuba KITAGAWA
  • Publication number: 20210083001
    Abstract: According to one embodiment, a magnetic memory device includes: a plurality of first films and a plurality of second films stacked alternately; a first insulating layer passing through the plurality of first and second films; a second insulating layer passing through the plurality of first and second films and in contact with a surface of the first insulating layer; a first magnet including a first pillar portion provided between the second insulating layer and the plurality of first and second films, and a first terrace portion coupled to one end of the first pillar portion; a first interconnect layer coupled to the other end of the first pillar portion of the first magnet; and a first magnetoresistance effect element coupled to the first terrace portion of the first magnet.
    Type: Application
    Filed: August 28, 2020
    Publication date: March 18, 2021
    Applicant: Kioxia Corporation
    Inventor: Yasuhito YOSHIMIZU
  • Publication number: 20210082950
    Abstract: According to one embodiment, a semiconductor memory device includes: first and second interconnect layers; a plurality of third interconnect layers stacked between the first and second interconnect layers; a first insulating layer passing through the plurality of third interconnect layers, and including one end that is in contact with a first face of the first interconnect layer; a first memory pillar including a first semiconductor layer passing through the plurality of third interconnect layers and a charge storage layer provided between the plurality of third interconnect layers and the first semiconductor layer. A distance between a third face of the first interconnect layer opposite to the first face and the second interconnect layer in the first direction, differs at a position corresponding to the first insulating layer from at positions corresponding to the third interconnect layers.
    Type: Application
    Filed: March 13, 2020
    Publication date: March 18, 2021
    Inventor: Yasuhito YOSHIMIZU
  • Publication number: 20210074643
    Abstract: A semiconductor device according to one embodiment includes a substrate, a stacked body including conductive layers and insulating layers alternately stacked on the substrate, and first contact plugs individually connected to the conductive layers on an end of the stacked body. The semiconductor device includes, on the substrate, a lower layer three-dimensional structure including any of a lower layer inclined structure continuously inclined upward with respect to a flat surface of the substrate, a lower layer stepped structure inclined upward in a stepwise manner with respect to the flat surface, and a lower layer composite stepped structure in which planes parallel to the flat surface and slopes inclined upward with respect to the flat surface are alternately continuous. At least some of terrace regions being connection regions to the first contact plugs on top surfaces of the conductive layers are located on the lower layer three-dimensional structure.
    Type: Application
    Filed: August 27, 2020
    Publication date: March 11, 2021
    Applicant: Kioxia Corporation
    Inventors: Takashi WATANABE, Yasuhito YOSHIMIZU
  • Publication number: 20210074638
    Abstract: In one embodiment, a semiconductor device includes a substrate including two element regions that extend in a first direction parallel to a surface of the substrate and are adjacent to each other in a second direction crossing the first direction. The device further includes an interconnection layer provided above the substrate. The device further includes an insulator provided between the substrate and the interconnection layer. The device further includes a plug extending in the second direction and in a third direction crossing the first and second directions in the insulator, provided on each of the element regions, and electrically connected to the element regions and the interconnection layer.
    Type: Application
    Filed: September 9, 2020
    Publication date: March 11, 2021
    Applicant: Kioxia Corporation
    Inventors: Tomoya SANUKI, Keisuke NAKATSUKA, Yasuhito YOSHIMIZU
  • Publication number: 20210043640
    Abstract: According to one embodiment, a semiconductor memory device includes: a plurality of first insulating layers; a plurality of first interconnect layers stacked alternately with the first insulating layers; a plurality of second interconnect layers arranged adjacently to the first interconnect layers; and a separation region including a plurality of first portions provided between the first interconnect layers and the second interconnect layers, and a plurality of second portions protruding from an outer periphery of each of the first portions. The second portions are linked to each other. The first interconnect layers and the second interconnect layers are separated from each other by the first portions and the linked second portions.
    Type: Application
    Filed: August 6, 2020
    Publication date: February 11, 2021
    Applicant: Kioxia Corporation
    Inventors: Genki KAWAGUCHI, Yasuhito YOSHIMIZU, Yusuke SHIMA
  • Publication number: 20210043546
    Abstract: According to one embodiment, a stacked body includes a plurality of electrode layers stacked with an insulator interposed. A conductive via pierces the stacked body, and connects an upper layer interconnect and a lower layer interconnect. A insulating film is provided between the via and the stacked body. A distance along a diametral direction of the via between a side surface of the via and an end surface of one of the electrode layers opposing the side surface of the via is greater than a distance along the diametral direction between the side surface of the via and an end surface of the insulator opposing the side surface of the via.
    Type: Application
    Filed: October 26, 2020
    Publication date: February 11, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Yasuhito YOSHIMIZU, Yoshiro SHIMOJO, Shinya ARAI
  • Patent number: 10879087
    Abstract: According to an embodiment, a substrate treatment apparatus includes a hair member including a noble metal, and a liquid chemical supply member to supply a liquid chemical. While a tip part of the hair member is contact with a predetermined surface of a metal, the liquid chemical is supplied onto the surface of the metal, and the metal is removed with etching.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: December 29, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yasuhito Yoshimizu, Yuya Akeboshi, Fuyuma Ito, Hakuba Kitagawa
  • Patent number: 10854534
    Abstract: According to one embodiment, a stacked body includes a plurality of electrode layers stacked with an insulator interposed. A conductive via pierces the stacked body, and connects an upper layer interconnect and a lower layer interconnect. A insulating film is provided between the via and the stacked body. A distance along a diametral direction of the via between a side surface of the via and an end surface of one of the electrode layers opposing the side surface of the via is greater than a distance along the diametral direction between the side surface of the via and an end surface of the insulator opposing the side surface of the via.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: December 1, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Yasuhito Yoshimizu, Yoshiro Shimojo, Shinya Arai
  • Patent number: 10804221
    Abstract: In one embodiment, a substrate treatment apparatus includes a substrate holder configured to hold a substrate provided with a film. The apparatus further includes a film treatment module configured to treat the film in accordance with warpage of the substrate such that the film includes a first region having a first film quality or a first film thickness and a second region having a second film quality or a second film thickness different from the first film quality or the first film thickness.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: October 13, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Fuyuma Ito, Yasuhito Yoshimizu, Hakuba Kitagawa
  • Publication number: 20200303408
    Abstract: In one embodiment, a semiconductor device includes a first film including a plurality of electrode layers and a plurality of insulating layers provided alternately in a first direction, and a first semiconductor layer provided in the first film via a charge storage layer and extending in the first direction. The device further includes a first conductive member provided in the first film and extending in the first direction, and a second semiconductor layer provided on the first film to contact the first semiconductor layer. The second semiconductor layer includes a first surface on a side of the first film, and a second surface on an opposite side of the first surface. The second surface is an uneven face protruding towards the first direction.
    Type: Application
    Filed: September 13, 2019
    Publication date: September 24, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Yasuhito YOSHIMIZU, Yuji SETTA, Masaru KITO
  • Publication number: 20200294971
    Abstract: In one embodiment, a semiconductor device includes a first chip that includes a first interconnect layer, a first insulator provided on the first interconnect layer, a first metal portion provided on the first interconnect layer and provided in the first insulator and including at least one of palladium, platinum and gold, and a second interconnect layer provided on the first metal portion and provided in the first insulator. The device further includes a second chip that includes a second insulator provided on the first insulator, and a third interconnect layer provided in the second insulator and provided on the second interconnect layer.
    Type: Application
    Filed: September 5, 2019
    Publication date: September 17, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Yusuke TANAKA, Atsushi Hieno, Tsutomu Nakanishi, Yasuhito Yoshimizu, Masayoshi Tagami
  • Patent number: 10720321
    Abstract: According to one embodiment, a substrate treating method includes: providing a first liquid onto a pattern on a substrate; providing, after the first liquid is provided, a second liquid containing a first substance to form a film containing the first substance on the pattern; providing, after the second liquid is provided onto the pattern, a third liquid; turning the third liquid into gas; and turning, after the third liquid is turned into gas, the film into gas.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: July 21, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Yasuhito Yoshimizu, Fuyuma Ito, Naomi Yanai
  • Publication number: 20200211864
    Abstract: According to one embodiment, a substrate processing apparatus includes a table configured to place a substrate thereon and to connect the substrate to a positive electrode, an counter electrode located opposite to the table, having a plurality of holes, and connected to a negative electrode, and a holding unit located opposite to the table across the counter electrode and configured to supply a chemical liquid to the counter electrode while holding the counter electrode.
    Type: Application
    Filed: August 29, 2019
    Publication date: July 2, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Yasuhito YOSHIMIZU, Hakuba KITAGAWA, Takaumi MORITA
  • Publication number: 20200185221
    Abstract: According to an embodiment, the substrate treatment device includes a dilutor configured to dilute a first liquid containing a metal ion and exhibiting acidity. The device further includes a pH changer configured to change a pH of the first liquid before or after being diluted by the dilutor. The device further includes a substrate conditioner configured to treat the substrate using the first liquid, which is diluted by the dilutor and with the pH changed by the pH changer.
    Type: Application
    Filed: September 3, 2019
    Publication date: June 11, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Yasuhito YOSHIMIZU, Fuyuma ITO, Hakuba KITAGAWA, Yohei YAMAMOTO, Hisashi OKUCHI, Yuji YAMADA
  • Publication number: 20200091092
    Abstract: In one embodiment, a substrate treatment apparatus includes a substrate holder configured to hold a substrate provided with a film. The apparatus further includes a film treatment module configured to treat the film in accordance with warpage of the substrate such that the film includes a first region having a first film quality or a first film thickness and a second region having a second film quality or a second film thickness different from the first film quality or the first film thickness.
    Type: Application
    Filed: February 28, 2019
    Publication date: March 19, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Fuyuma Ito, Yasuhito Yoshimizu, Hakuba Kitagawa
  • Publication number: 20200075315
    Abstract: According to one embodiment, a substrate treating method includes: providing a first liquid onto a pattern on a substrate; providing, after the first liquid is provided, a second liquid containing a first substance to form a film containing the first substance on the pattern; providing, after the second liquid is provided onto the pattern, a third liquid; turning the third liquid into gas; and turning, after the third liquid is turned into gas, the film into gas.
    Type: Application
    Filed: March 8, 2019
    Publication date: March 5, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Yasuhito YOSHIMIZU, Fuyuma ITO, Naomi YANAI
  • Publication number: 20200075461
    Abstract: According to one embodiment, a stacked body includes a plurality of electrode layers stacked with an insulator interposed. A conductive via pierces the stacked body, and connects an upper layer interconnect and a lower layer interconnect. A insulating film is provided between the via and the stacked body. A distance along a diametral direction of the via between a side surface of the via and an end surface of one of the electrode layers opposing the side surface of the via is greater than a distance along the diametral direction between the side surface of the via and an end surface of the insulator opposing the side surface of the via.
    Type: Application
    Filed: November 8, 2019
    Publication date: March 5, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Yasuhito YOSHIMIZU, Yoshiro SHIMOJO, Shinya ARAI