Patents by Inventor Yasuhito Yoshimizu

Yasuhito Yoshimizu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10580784
    Abstract: A memory device includes first and second conductive layers, first and second semiconductor members, first and second charge storage members, first and second insulating members, and first and second insulating layers. The second conductive layer is distant from the first conductive layer. The first semiconductor member is positioned between the first and second conductive layers. The second semiconductor member is positioned between the first semiconductor member and the second conductive layer. The first insulating layer includes a first region positioned between the first semiconductor member and the first charge storage member and a second region positioned between the first semiconductor member and the second semiconductor member. The second insulating layer includes a third region positioned between the second semiconductor member and the second charge storage member and a fourth region positioned between the second region and the second semiconductor member.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: March 3, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Yasuhito Yoshimizu, Takaumi Morita
  • Publication number: 20200066751
    Abstract: A semiconductor storage device according to an embodiment comprises a substrate. A stack body having first conductive layers and first insulating layers alternately stacked in a first direction is provided on the substrate. A pillar part extends in the first direction in the stack body and has a memory film. An insulating member extends in the first direction at a position different from that of the pillar part in the stack body. A phosphorus-containing insulator is provided below the stack body and the insulating member.
    Type: Application
    Filed: March 13, 2019
    Publication date: February 27, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Yasuhito Yoshimizu, Tomohiko Sugita
  • Publication number: 20200066550
    Abstract: In one embodiment, a substrate treatment apparatus includes a supporter configured to support and rotate a substrate, and a liquid supplier configured to supply a liquid to the substrate. The apparatus further includes a wall provided separately from the supporter and at least partially surrounding the supporter, and a detector provided between the supporter and the wall and configured to detect a change in the liquid.
    Type: Application
    Filed: February 19, 2019
    Publication date: February 27, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Hakuba KITAGAWA, Yasuhito YOSHIMIZU, Fuyuma ITO, Hiroyuki TANIZAKI
  • Patent number: 10573662
    Abstract: A memory device includes first and second conductive layers, first and second semiconductor members, first and second charge storage members, first and second insulating members, and first and second insulating layers. The second conductive layer is distant from the first conductive layer. The first semiconductor member is positioned between the first and second conductive layers. The second semiconductor member is positioned between the first semiconductor member and the second conductive layer. The first insulating layer includes a first region positioned between the first semiconductor member and the first charge storage member and a second region positioned between the first semiconductor member and the second semiconductor member. The second insulating layer includes a third region positioned between the second semiconductor member and the second charge storage member and a fourth region positioned between the second region and the second semiconductor member.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: February 25, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Yasuhito Yoshimizu
  • Patent number: 10529588
    Abstract: In accordance with an embodiment, a substrate treatment method includes bringing a first metallic film on a substrate into contact with a first liquid, mixing a second liquid into the first liquid, and bringing the first metallic film or a second metallic film different from the first metallic film into contact with a liquid in which the first liquid and the second liquid are mixed together to etch the first or second metallic film. The first liquid includes an oxidizing agent, a complexing agent, and water (H2O) of a first content rate to etch the first metallic film. The second liquid includes water (H2O) at a second content rate higher than the first content rate after the etching has started.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: January 7, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Yuya Akeboshi, Hiroshi Tomita, Hisashi Okuchi, Yasuhito Yoshimizu, Hiroaki Yamada
  • Patent number: 10515873
    Abstract: According to one embodiment, a stacked body includes a plurality of electrode layers stacked with an insulator interposed. A conductive via pierces the stacked body, and connects an upper layer interconnect and a lower layer interconnect. A insulating film is provided between the via and the stacked body. A distance along a diametral direction of the via between a side surface of the via and an end surface of one of the electrode layers opposing the side surface of the via is greater than a distance along the diametral direction between the side surface of the via and an end surface of the insulator opposing the side surface of the via.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: December 24, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Yasuhito Yoshimizu, Yoshiro Shimojo, Shinya Arai
  • Patent number: 10482941
    Abstract: According to one embodiment, a magnetic memory device includes a first memory portion, a first conductive portion, a first interconnection, and a controller. The first memory portion includes a first magnetic portion including a first portion and a second portion, a first magnetic layer, and a first nonmagnetic layer provided between the second portion and the first magnetic layer. The first conductive portion is electrically connected to the first portion. The first interconnection is electrically connected to the first magnetic layer. The controller is electrically connected to the first conductive portion and the first interconnection. The controller applies a first pulse having a first pulse height and a first pulse length between the first conductive portion and the first interconnection in a first write operation and applies a second pulse having a second pulse height and a second pulse length in a first shift operation.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: November 19, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Takuya Shimada, Yasuaki Ootera, Tsuyoshi Kondo, Nobuyuki Umetsu, Michael Arnaud Quinsat, Masaki Kado, Susumu Hashimoto, Shiho Nakamura, Hideaki Aochi, Tomoya Sanuki, Shinji Miyano, Yoshihiro Ueda, Yuichi Ito, Yasuhito Yoshimizu
  • Patent number: 10446212
    Abstract: According to one embodiment, a magnetic memory device includes a first magnetic portion, a first electrode, a second electrode, a third electrode, a second magnetic portion, a first nonmagnetic portion, and a controller. The first magnetic portion includes an extension portion and a third portion. The extension portion includes a first portion and a second portion. The third portion is connected to the second portion. The first electrode is electrically connected to the first portion. At least a portion of the third portion is positioned between the second electrode and the third electrode. The second magnetic portion is provided between the second electrode and the at least a portion of the third portion. The first nonmagnetic portion is provided between the second magnetic portion and the at least a portion of the third portion. The controller is electrically connected to the first, second electrode, and third electrodes.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: October 15, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Susumu Hashimoto, Yasuaki Ootera, Tsuyoshi Kondo, Takuya Shimada, Michael Arnaud Quinsat, Masaki Kado, Nobuyuki Umetsu, Shiho Nakamura, Tomoya Sanuki, Yoshihiro Ueda, Shinji Miyano, Hideaki Aochi, Yasuhito Yoshimizu, Yuichi Ito
  • Patent number: 10446249
    Abstract: According to one embodiment, a magnetic memory device includes a first interconnect, a second interconnect, a first memory portion, and a controller. The first memory portion is provided between the first and second interconnects. The controller is electrically connected with the first and second interconnects. The first memory portion includes a first magnetic member, a first magnetic element, and a first non-linear element. The first magnetic element is provided between the first magnetic member and the second interconnect in a first current path between the first and second interconnects. The first non-linear element is provided between the first magnetic element and the second interconnect in the first current path. The controller is configured to supply a first shift current in the first current path in a first shift operation. The controller is configured to supply a first reading current in the first current path in a first reading operation.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: October 15, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Michael Arnaud Quinsat, Yasuaki Ootera, Tsuyoshi Kondo, Nobuyuki Umetsu, Takuya Shimada, Masaki Kado, Susumu Hashimoto, Shiho Nakamura, Hideaki Aochi, Tomoya Sanuki, Shinji Miyano, Yoshihiro Ueda, Yuichi Ito, Yasuhito Yoshimizu
  • Publication number: 20190287598
    Abstract: According to one embodiment, a magnetic memory device includes a first memory portion, a first conductive portion, a first interconnection, and a controller. The first memory portion includes a first magnetic portion including a first portion and a second portion, a first magnetic layer, and a first nonmagnetic layer provided between the second portion and the first magnetic layer. The first conductive portion is electrically connected to the first portion. The first interconnection is electrically connected to the first magnetic layer. The controller is electrically connected to the first conductive portion and the first interconnection. The controller applies a first pulse having a first pulse height and a first pulse length between the first conductive portion and the first interconnection in a first write operation and applies a second pulse having a second pulse height and a second pulse length in a first shift operation.
    Type: Application
    Filed: September 12, 2018
    Publication date: September 19, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Takuya SHIMADA, Yasuaki OOTERA, Tsuyoshi KONDO, Nobuyuki UMETSU, Michael Arnaud QUINSAT, Masaki KADO, Susumu HASHIMOTO, Shiho NAKAMURA, Hideaki AOCHI, Tomoya SANUKI, Shinji MIYANO, Yoshihiro UEDA, Yuichi ITO, Yasuhito YOSHIMIZU
  • Publication number: 20190287637
    Abstract: According to one embodiment, a magnetic memory device includes a first interconnect, a second interconnect, a first memory portion, and a controller. The first memory portion is provided between the first and second interconnects. The controller is electrically connected with the first and second interconnects. The first memory portion includes a first magnetic member, a first magnetic element, and a first non-linear element. The first magnetic element is provided between the first magnetic member and the second interconnect in a first current path between the first and second interconnects. The first non-linear element is provided between the first magnetic element and the second interconnect in the first current path. The controller is configured to supply a first shift current in the first current path in a first shift operation. The controller is configured to supply a first reading current in the first current path in a first reading operation.
    Type: Application
    Filed: September 4, 2018
    Publication date: September 19, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Michael Arnaud Quinsat, Yasuaki Ootera, Tsuyoshi Kondo, Nobuyuki Umetsu, Takuya Shimada, Masaki Kado, Susumu Hashimoto, Shiho Nakamura, Hideaki Aochi, Tomoya Sanuki, Shinji Myano, Yoshihiro Ueda, Yuichi Ito, Yasuhito Yoshimizu
  • Patent number: 10403381
    Abstract: According to one embodiment, a magnetic memory device includes a first magnetic member, a first electrode, a first magnetic layer, a first non-magnetic layer, a first conductive layer and a controller. The first magnetic member includes a first extending portion and a third magnetic portion. The first extending portion includes first and second magnetic portions. The third magnetic portion is connected with the second magnetic portion. The first electrode is electrically connected with the first magnetic portion. The first non-magnetic layer is provided between the first magnetic layer and at least a part of the third magnetic portion. The first conductive layer includes first and second conductive portions, and a third conductive portion being between the first conductive portion and the second conductive portion. The controller is electrically connected with the first electrode, the first magnetic layer, the first conductive portion and the second conductive portion.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: September 3, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Michael Arnaud Quinsat, Takuya Shimada, Susumu Hashimoto, Nobuyuki Umetsu, Yasuaki Ootera, Masaki Kado, Tsuyoshi Kondo, Shiho Nakamura, Tomoya Sanuki, Yoshihiro Ueda, Yuichi Ito, Shinji Miyano, Hideaki Aochi, Yasuhito Yoshimizu
  • Publication number: 20190259777
    Abstract: According to one embodiment, a semiconductor device includes a substrate, a stacked body, a second air gap, a first insulating film, a semiconductor film, and a stacked film. The stacked body is provided above the substrate and includes a plurality of electrode films stacked via a first air gap. The second air gap extends in a stacking direction of the stacked body. The second air gap separates the stacked body in a first direction crossing the stacking direction. The first insulating film is provided above the stacked body and covers an upper end of the second air gap. The stacked film is provided between a side surface of the electrode film and a side surface of the semiconductor film opposed to the side surface of the electrode film. The stacked film is in contact with the side surface of the electrode film and the side surface of the semiconductor film.
    Type: Application
    Filed: April 30, 2019
    Publication date: August 22, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Yasuhito YOSHIMIZU, Akifumi GAWASE, Kei WATANABE, Shinya ARAI
  • Publication number: 20190237479
    Abstract: A memory device includes first and second conductive layers, first and second semiconductor members, first and second charge storage members, first and second insulating members, and first and second insulating layers. The second conductive layer is distant from the first conductive layer. The first semiconductor member is positioned between the first and second conductive layers. The second semiconductor member is positioned between the first semiconductor member and the second conductive layer. The first insulating layer includes a first region positioned between the first semiconductor member and the first charge storage member and a second region positioned between the first semiconductor member and the second semiconductor member. The second insulating layer includes a third region positioned between the second semiconductor member and the second charge storage member and a fourth region positioned between the second region and the second semiconductor member.
    Type: Application
    Filed: April 11, 2019
    Publication date: August 1, 2019
    Applicant: Toshiba Memory Corporation
    Inventor: Yasuhito YOSHIMIZU
  • Patent number: 10354739
    Abstract: According to one embodiment, a magnetic memory device includes a first magnetic portion, a first magnetic layer, a first nonmagnetic layer, a second magnetic portion, a second magnetic layer, a second nonmagnetic layer, a first electrode, and a second electrode. The first magnetic portion includes a first magnetic part and a second magnetic part. The first nonmagnetic layer is provided between the first magnetic layer and the first magnetic part. The second magnetic portion includes a third magnetic part and a fourth magnetic part. The second nonmagnetic layer is provided between the second magnetic layer and the third magnetic part. The first electrode electrically is connected to the second magnetic part and the fourth magnetic part. The second electrode is electrically connected to the first magnetic part and the third magnetic part.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: July 16, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Yasuaki Ootera, Tsuyoshi Kondo, Nobuyuki Umetsu, Michael Arnaud Quinsat, Takuya Shimada, Masaki Kado, Susumu Hashimoto, Shiho Nakamura, Hideaki Aochi, Tomoya Sanuki, Shinji Miyano, Yoshihiro Ueda, Yuichi Ito, Yasuhito Yoshimizu
  • Patent number: 10319740
    Abstract: A memory device includes first and second conductive layers, first and second semiconductor members, first and second charge storage members, first and second insulating members, and first and second insulating layers. The second conductive layer is distant from the first conductive layer. The first semiconductor member is positioned between the first and second conductive layers. The second semiconductor member is positioned between the first semiconductor member and the second conductive layer. The first insulating layer includes a first region positioned between the first semiconductor member and the first charge storage member and a second region positioned between the first semiconductor member and the second semiconductor member. The second insulating layer includes a third region positioned between the second semiconductor member and the second charge storage member and a fourth region positioned between the second region and the second semiconductor member.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: June 11, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Yasuhito Yoshimizu
  • Patent number: 10319734
    Abstract: According to one embodiment, a semiconductor device includes a substrate, a stacked body, a second air gap, a first insulating film, a semiconductor film, and a stacked film. The stacked body is provided above the substrate and includes a plurality of electrode films stacked via a first air gap. The second air gap extends in a stacking direction of the stacked body. The second air gap separates the stacked body in a first direction crossing the stacking direction. The first insulating film is provided above the stacked body and covers an upper end of the second air gap. The stacked film is provided between a side surface of the electrode film and a side surface of the semiconductor film opposed to the side surface of the electrode film. The stacked film is in contact with the side surface of the electrode film and the side surface of the semiconductor film.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: June 11, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Yasuhito Yoshimizu, Akifumi Gawase, Kei Watanabe, Shinya Arai
  • Patent number: 10311932
    Abstract: According to one embodiment, a magnetic memory device includes a magnetic portion, a first magnetic layer, a first nonmagnetic layer, a first element portion, first to third interconnects, and a controller. In a first operation, the controller sets the first interconnect to a first potential, the second interconnect to a second potential, and the third interconnect to a third potential. An absolute value of a difference between the second potential and the third potential is greater than that between the first potential and the third potential. In a second operation, the controller sets the first interconnect to a fourth potential, the second interconnect to a fifth potential, and the third interconnect to a sixth potential. An absolute value of a difference between the fifth potential and the sixth potential is less than that between the fourth potential and the sixth potential.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: June 4, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Nobuyuki Umetsu, Tsuyoshi Kondo, Yasuaki Ootera, Takuya Shimada, Michael Arnaud Quinsat, Masaki Kado, Susumu Hashimoto, Shiho Nakamura, Tomoya Sanuki, Yoshihiro Ueda, Yuichi Ito, Shinji Miyano, Hideaki Aochi, Yasuhito Yoshimizu
  • Patent number: 10312255
    Abstract: According to one embodiment, the plurality of charge storage films are separated in a stacking direction with a second air gap interposed. The plurality of insulating films are provided on side surfaces of electrode layers opposing the charge storage films, on portions of surfaces of the electrode layers continuous from the side surfaces and opposing a first air gap between the electrode layers, and on corners of the electrode layers between the portions and the side surfaces. The plurality of insulating films are divided in the stacking direction with a third air gap interposed and without the charge storage films being interposed. The third air gap communicates with the first air gap and the second air gap between the first air gap and the second air gap.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: June 4, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Yasuhito Yoshimizu, Satoshi Wakatsuki, Yohei Sato, Keiichi Sawa
  • Patent number: 10304902
    Abstract: According to one embodiment, a magnetic memory device includes a first magnetic member, a first magnetic layer, and a first nonmagnetic layer. The first magnetic member includes a first extension portion and a third portion. The first extension portion extends along a first direction and includes a first portion and a second portion. The third portion is connected to the second portion. A direction from the first portion toward the second portion is aligned with the first direction. At least a portion of the third portion is tilted with respect to the first direction. The first nonmagnetic layer is provided between the first magnetic layer and the at least a portion of the third portion. The first nonmagnetic layer is provided along the at least a portion of the third portion and is tilted with respect to the first direction.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: May 28, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Masaki Kado, Tsuyoshi Kondo, Yasuaki Ootera, Takuya Shimada, Michael Arnaud Quinsat, Nobuyuki Umetsu, Susumu Hashimoto, Shiho Nakamura, Hideaki Aochi, Tomoya Sanuki, Shinji Miyano, Yoshihiro Ueda, Yuichi Ito, Yasuhito Yoshimizu