Patents by Inventor Yasuhito Yoshimizu

Yasuhito Yoshimizu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10276586
    Abstract: According to one embodiment, a semiconductor device includes a substrate and a semiconductor layer. The device further includes a first electrode layer that is provided on a side surface of the semiconductor layer with a first insulating film interposed therebetween. The device further includes a charge storage layer provided on a side surface of the first electrode layer with the second insulating film interposed therebetween.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: April 30, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Atsushi Murakoshi, Yasuhito Yoshimizu, Tomofumi Inoue, Tatsuya Kato, Yuta Watanabe, Fumitaka Arai
  • Patent number: 10249531
    Abstract: A method for forming a metal wiring according to embodiments includes forming a first insulating layer on a substrate; forming a catalyst adsorption layer by bringing a surface of the first insulating layer into contact with a solution containing a compound having a triazine skeleton, a first functional group of one of a silanol group and an alkoxysilyl group, and a second functional group of at least one selected from the group consisting of an amino group, a thiol group, a carboxyl group, and an azide group; forming a second insulating layer different from the first insulating layer on the catalyst adsorption layer; patterning the second insulating layer to form a mask pattern; etching the first insulating layer by a wet etching method; selectively forming a catalyst layer; and forming a metal layer on the catalyst layer by an electroless plating method.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: April 2, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Atsushi Hieno, Tsutomu Nakanishi, Yusuke Tanaka, Yasuhito Yoshimizu, Akihiko Happoya
  • Publication number: 20190088539
    Abstract: A method for forming a metal wiring according to embodiments includes forming a first insulating layer on a substrate; forming a catalyst adsorption layer by bringing a surface of the first insulating layer into contact with a solution containing a compound having a triazine skeleton, a first functional group of one of a silanol group and an alkoxysilyl group, and a second functional group of at least one selected from the group consisting of an amino group, a thiol group, a carboxyl group, and an azide group; forming a second insulating layer different from the first insulating layer on the catalyst adsorption layer; patterning the second insulating layer to form a mask pattern; etching the first insulating layer by a wet etching method; selectively forming a catalyst layer; and forming a metal layer on the catalyst layer by an electroless plating method.
    Type: Application
    Filed: February 9, 2018
    Publication date: March 21, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Atsushi Hieno, Tsutomu Nakanishi, Yusuke Tanaka, Yasuhito Yoshimizu, Akihiko Happoya
  • Publication number: 20190088345
    Abstract: According to one embodiment, a magnetic memory device includes a first magnetic member, a first electrode, a first magnetic layer, a first non-magnetic layer, a first conductive layer and a controller. The first magnetic member includes a first extending portion and a third magnetic portion. The first extending portion includes first and second magnetic portions. The third magnetic portion is connected with the second magnetic portion. The first electrode is electrically connected with the first magnetic portion. The first non-magnetic layer is provided between the first magnetic layer and at least a part of the third magnetic portion. The first conductive layer includes first and second conductive portions, and a third conductive portion being between the first conductive portion and the second conductive portion. The controller is electrically connected with the first electrode, the first magnetic layer, the first conductive portion and the second conductive portion.
    Type: Application
    Filed: March 12, 2018
    Publication date: March 21, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Michael Arnaud QUINSAT, Takuya SHIMADA, Susumu HASHIMOTO, Nobuyuki UMETSU, Yasuaki OOTERA, Masaki KADO, Tsuyoshi KONDO, Shiho NAKAMURA, Tomoya SANUKI, Yoshihiro UEDA, Yuichi ITO, Shinji MIYANO, Hideaki AOCHI, Yasuhito YOSHIMIZU
  • Publication number: 20190088346
    Abstract: According to one embodiment, a magnetic memory device includes a first magnetic portion, a first magnetic layer, a first nonmagnetic layer, a second magnetic portion, a second magnetic layer, a second nonmagnetic layer, a first electrode, and a second electrode. The first magnetic portion includes a first magnetic part and a second magnetic part. The first nonmagnetic layer is provided between the first magnetic layer and the first magnetic part. The second magnetic portion includes a third magnetic part and a fourth magnetic part. The second nonmagnetic layer is provided between the second magnetic layer and the third magnetic part. The first electrode electrically is connected to the second magnetic part and the fourth magnetic part. The second electrode is electrically connected to the first magnetic part and the third magnetic part.
    Type: Application
    Filed: March 13, 2018
    Publication date: March 21, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Yasuaki Ootera, Tsuyoshi Kondo, Nobuyuki Umetsu, Michael Arnaud Quinsat, Takuya Shimada, Masaki Kado, Susumu Hashimoto, Shiho Nakamura, Hideaki Aochi, Tomoya Sanuki, Shinji Miyano, Yoshihiro Ueda, Yuichi Ito, Yasuhito Yoshimizu
  • Publication number: 20190088305
    Abstract: According to one embodiment, a magnetic memory device includes a magnetic portion, a first magnetic layer, a first nonmagnetic layer, a first element portion, first to third interconnects, and a controller. In a first operation, the controller sets the first interconnect to a first potential, the second interconnect to a second potential, and the third interconnect to a third potential. An absolute value of a difference between the second potential and the third potential is greater than that between the first potential and the third potential. In a second operation, the controller sets the first interconnect to a fourth potential, the second interconnect to a fifth potential, and the third interconnect to a sixth potential. An absolute value of a difference between the fifth potential and the sixth potential is less than that between the fourth potential and the sixth potential.
    Type: Application
    Filed: March 12, 2018
    Publication date: March 21, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Nobuyuki UMETSU, Tsuyoshi KONDO, Yasuaki OOTERA, Takuya SHIMADA, Michael Arnaud QUINSAT, Masaki KADO, Susumu HASHIMOTO, Shiho NAKAMURA, Tomoya SANUKI, Yoshihiro UEDA, Yuichi ITO, Shinji MIYANO, Hideeaki AOCHI, Yasuhito YOSHIMIZU
  • Publication number: 20190088712
    Abstract: According to one embodiment, a magnetic memory device includes a first magnetic member, a first magnetic layer, and a first nonmagnetic layer. The first magnetic member includes a first extension portion and a third portion. The first extension portion extends along a first direction and includes a first portion and a second portion. The third portion is connected to the second portion. A direction from the first portion toward the second portion is aligned with the first direction. At least a portion of the third portion is tilted with respect to the first direction. The first nonmagnetic layer is provided between the first magnetic layer and the at least a portion of the third portion. The first nonmagnetic layer is provided along the at least a portion of the third portion and is tilted with respect to the first direction.
    Type: Application
    Filed: March 9, 2018
    Publication date: March 21, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Masaki KADO, Tsuyoshi KONDO, Yasuaki OOTERA, Takuya SHIMADA, Michael Arnaud QUINSAT, Nobuyuki UMETSU, Susumu HASHIMOTO, Shiho NAKAMURA, Hideaki AOCHI, Tomoya SANUKI, Shinji MIYANO, Yoshihiro UEDA, Yuichi ITO, Yasuhito YOSHIMIZU
  • Publication number: 20190088304
    Abstract: According to one embodiment, a magnetic memory device includes a first magnetic portion, a first electrode, a second electrode, a third electrode, a second magnetic portion, a first nonmagnetic portion, and a controller. The first magnetic portion includes an extension portion and a third portion. The extension portion includes a first portion and a second portion. The third portion is connected to the second portion. The first electrode is electrically connected to the first portion. At least a portion of the third portion is positioned between the second electrode and the third electrode. The second magnetic portion is provided between the second electrode and the at least a portion of the third portion. The first nonmagnetic portion is provided between the second magnetic portion and the at least a portion of the third portion. The controller is electrically connected to the first, second electrode, and third electrodes.
    Type: Application
    Filed: March 12, 2018
    Publication date: March 21, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Susumu HASHIMOTO, Yasuaki Ootera, Tsuyoshi Kondo, Takuya Shimada, Michael Arnaud Quinsat, Masaki Kado, Nobuyuki Umetsu, Shiho Nakamura, Tomoya Sanuki, Yoshihiro Ueda, Shinji Miyano, Hideaki Aochi, Yasuhito Yoshimizu, Yuichi Ito
  • Publication number: 20190067311
    Abstract: A memory device includes first and second conductive layers, first and second semiconductor members, first and second charge storage members, first and second insulating members, and first and second insulating layers. The second conductive layer is distant from the first conductive layer. The first semiconductor member is positioned between the first and second conductive layers. The second semiconductor member is positioned between the first semiconductor member and the second conductive layer. The first insulating layer includes a first region positioned between the first semiconductor member and the first charge storage member and a second region positioned between the first semiconductor member and the second semiconductor member. The second insulating layer includes a third region positioned between the second semiconductor member and the second charge storage member and a fourth region positioned between the second region and the second semiconductor member.
    Type: Application
    Filed: August 7, 2018
    Publication date: February 28, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Yasuhito YOSHIMIZU, Takaumi MORITA
  • Publication number: 20190067319
    Abstract: A memory device includes first and second conductive layers, first and second semiconductor members, first and second charge storage members, first and second insulating members, and first and second insulating layers. The second conductive layer is distant from the first conductive layer. The first semiconductor member is positioned between the first and second conductive layers. The second semiconductor member is positioned between the first semiconductor member and the second conductive layer. The first insulating layer includes a first region positioned between the first semiconductor member and the first charge storage member and a second region positioned between the first semiconductor member and the second semiconductor member. The second insulating layer includes a third region positioned between the second semiconductor member and the second charge storage member and a fourth region positioned between the second region and the second semiconductor member.
    Type: Application
    Filed: March 12, 2018
    Publication date: February 28, 2019
    Applicant: Toshiba Memory Corporation
    Inventor: Yasuhito Yoshimizu
  • Publication number: 20190035636
    Abstract: A plasma treatment apparatus includes a discharge device generating plasma under atmospheric pressure, and a nonmetallic tube capable of advancing the plasma generated in the discharge device. The discharge device includes a discharge body with an internal space, and the plasma being generated in the internal space. The nonmetallic tube is connected to the discharge body, and includes a material different from a material of the discharge body. The plasma is released from the nonmetallic tube to an environment under atmospheric pressure.
    Type: Application
    Filed: July 6, 2018
    Publication date: January 31, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Yasuhito Yoshimizu, Hiroyuki Yasui, Yuya Akeboshi, Fuyuma Ito
  • Patent number: 10192882
    Abstract: According to one embodiment, a semiconductor device includes a stacked body, a columnar portion, and a first air gap. The stacked body includes a plurality of conductive layers stacked with an insulator interposed. The columnar portion extends through the stacked body in a stacking direction of the stacked body. The first air gap extends through the stacked body in the stacking direction. The insulator includes an insulating layer provided at a periphery of a side surface of the columnar portion, and a second air gap communicating with the first air gap and being provided between the insulating layer and the first air gap. The insulating layer has a protrusion at an end adjacent to the second air gap.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: January 29, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Yasuhito Yoshimizu
  • Patent number: 10147612
    Abstract: A metal pattern forming method according to an embodiment includes forming a metal film on a surface of a substrate by an electroless plating method, the substrate including a first layer including a protrusion and a recess, and a film thickness of the metal film being a half or more of a width of the recess; and performing wet etching, the metal film in the recess removed by the wet etching and the metal film on the protrusion remained after the wet etching.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: December 4, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsutomu Nakanishi, Yusuke Tanaka, Atsushi Hieno, Yasuhito Yoshimizu, Akihiko Happoya
  • Publication number: 20180301349
    Abstract: In accordance with an embodiment, a substrate treatment method includes bringing a first metallic film on a substrate into contact with a first liquid, mixing a second liquid into the first liquid, and bringing the first metallic film or a second metallic film different from the first metallic film into contact with a liquid in which the first liquid and the second liquid are mixed together to etch the first or second metallic film. The first liquid includes an oxidizing agent, a complexing agent, and water (H2O) of a first content rate to etch the first metallic film. The second liquid includes water (H2O) at a second content rate higher than the first content rate after the etching has started.
    Type: Application
    Filed: June 20, 2018
    Publication date: October 18, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Yuya AKEBOSHI, Hiroshi Tomita, Hisashi Okuchi, Yasuhito Yoshimizu, Hiroaki Yamada
  • Patent number: 10096613
    Abstract: According to one embodiment, columnar portions extend through an insulating layer and through a stacked body under the insulating layer. The columnar portions are of an insulating material different from the insulating layer. Contact portions include a first contact portion disposed inside a first terrace portion and a second contact portion disposed inside a second terrace portion. The columnar portions including a first columnar portion disposed inside the first terrace portion and a second columnar portion disposed inside the second terrace portion. A shortest distance between the first contact portion and the first columnar portion, and a shortest distance between the second contact portion and the second columnar portion are substantially equal to each other.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: October 9, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Atsushi Takahashi, Yasuhito Yoshimizu
  • Publication number: 20180277390
    Abstract: A metal pattern forming method according to an embodiment includes forming a metal film on a surface of a substrate by an electroless plating method, the substrate including a first layer including a protrusion and a recess, and a film thickness of the metal film being a half or more of a width of the recess; and performing wet etching, the metal film in the recess removed by the wet etching and the metal film on the protrusion remained after the wet etching.
    Type: Application
    Filed: August 28, 2017
    Publication date: September 27, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tsutomu NAKANISHI, Yusuke Tanaka, Atsushi Hieno, Yasuhito Yoshimizu, Akihiko Happoya
  • Publication number: 20180274102
    Abstract: A method of forming a metal pattern includes forming a catalyst adsorption layer by bringing a surface of a substrate into contact with a solution, the substrate having a base region and a plurality of protrusions provided on the base region, the base region includes a first material, the protrusions includes a second material different from the first material, the first and the second material being exposed on the surface, and the solution containing a compound having a triazine skeleton, a first functional group of any one of a silanol group and an alkoxysilyl group, and a second functional group of at least one selected from the group consisting of an amino group, a thiol group, and an azido group, forming a catalyst layer on the catalyst adsorption layer, forming a metal film on the catalyst layer by an electroless plating method, and removing the metal film on the protrusions.
    Type: Application
    Filed: September 7, 2017
    Publication date: September 27, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yusuke TANAKA, Atsushi HIENO, Tsutomu NAKANISHI, Yasuhito YOSHIMIZU, Akihiko HAPPOYA
  • Publication number: 20180269082
    Abstract: According to an embodiment, a substrate treatment apparatus includes a hair member including a noble metal, and a liquid chemical supply member to supply a liquid chemical. While a tip part of the hair member is contact with a predetermined surface of a metal, the liquid chemical is supplied onto the surface of the metal, and the metal is removed with etching.
    Type: Application
    Filed: March 14, 2018
    Publication date: September 20, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Yasuhito Yoshimizu, Yuya Akeboshi, Fuyuma Ito, Hakuba Kitagawa
  • Publication number: 20180265989
    Abstract: According to an embodiment, a substrate treatment apparatus includes a noble metal-containing member having a concave-convex surface including a noble metal, and a liquid chemical supply member to supply a liquid chemical. While convex portions of the concave-convex surface are contact with a predetermined surface of a metal, the liquid chemical is supplied onto the surface of the metal to remove the metal with etching.
    Type: Application
    Filed: September 11, 2017
    Publication date: September 20, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Yasuhito YOSHIMIZU, Yuya AKEBOSHI, Fuyuma ITO, Hakuba KITAGAWA
  • Publication number: 20180261529
    Abstract: According to one embodiment, a stacked body includes a plurality of electrode layers stacked with an insulator interposed. A conductive via pierces the stacked body, and connects an upper layer interconnect and a lower layer interconnect. A insulating film is provided between the via and the stacked body. A distance along a diametral direction of the via between a side surface of the via and an end surface of one of the electrode layers opposing the side surface of the via is greater than a distance along the diametral direction between the side surface of the via and an end surface of the insulator opposing the side surface of the via.
    Type: Application
    Filed: September 7, 2017
    Publication date: September 13, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Yasuhito YOSHIMIZU, Yoshiro Shimojo, Shinya Arai