Patents by Inventor Yasushi Matsubara
Yasushi Matsubara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10685694Abstract: Methods, systems, and devices for cell bottom node reset in a memory array are described. The memory array may include a plurality of ferroelectric memory cells having a cell bottom node and a cell plate opposite the cell bottom node. A zero voltage may be applied to a plurality of digit lines in the memory array. A plurality of word lines may be activated to electrically coupled the plurality of digit lines to cell bottom node of each of the ferroelectric memory cells. Accordingly, the cell bottom node of each of the ferroelectric memory cells may be reset to the zero voltage.Type: GrantFiled: April 17, 2019Date of Patent: June 16, 2020Assignee: Micron Technology, Inc.Inventors: Kiyotake Sakurai, Yasushi Matsubara
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Publication number: 20200185020Abstract: Methods and apparatuses for erasing data on a plurality of ferroelectric memory cells in a memory cell array in a memory apparatus are disclosed. An example apparatus includes: a memory cell array including a first plurality of word lines; a digit line; and a plurality of ferroelectric memory cells; a control circuit that provides a section select signal and a word line select signal to select a second plurality of word lines among the first plurality of word lines responsive to an address; and an address decoder that activates the second plurality of word lines. Each ferroelectric memory cell includes: a ferroelectric capacitor having a first terminal coupled to a cell plate node and a second terminal coupled to a selection circuit that couples the digit line to the second terminal responsive to a signal on a corresponding word line of the second plurality of word lines.Type: ApplicationFiled: February 18, 2020Publication date: June 11, 2020Applicant: Micron Technology, Inc.Inventors: Kiyotake Sakurai, Yasushi Matsubara
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Patent number: 10679687Abstract: A memory cell comprises first, second, third, and fourth transistors individually comprising a transistor gate. First and second ferroelectric capacitors individually have one capacitor electrode elevationally between the transistor gates of the first, second, third, and fourth transistors. Other memory cells are disclosed, as are arrays of memory cells.Type: GrantFiled: July 31, 2018Date of Patent: June 9, 2020Assignee: Micron Technology, Inc.Inventor: Yasushi Matsubara
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Patent number: 10607678Abstract: Methods and apparatuses for erasing data on a plurality of ferroelectric memory cells in a memory cell array in a memory apparatus are disclosed. An example apparatus includes: a memory cell array including a first plurality of word lines; a digit line; and a plurality of ferroelectric memory cells; a control circuit that provides a section select signal and a word line select signal to select a second plurality of word lines among the first plurality of word lines responsive to an address; and an address decoder that activates the second plurality of word lines. Each ferroelectric memory cell includes: a ferroelectric capacitor having a first terminal coupled to a cell plate node and a second terminal coupled to a selection circuit that couples the digit line to the second terminal responsive to a signal on a corresponding word line of the second plurality of word lines.Type: GrantFiled: February 6, 2019Date of Patent: March 31, 2020Assignee: Micron Technology, Inc.Inventors: Kiyotake Sakurai, Yasushi Matsubara
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Publication number: 20200051659Abstract: Methods, systems, and devices related to access schemes for access line faults in a memory device are described. In one example, a method may include isolating a first word line of a section of a memory device from a voltage source (e.g., a deselection voltage source) during a first portion of a period when the first word line is deselected, and coupling the first word line with the voltage source during a second portion of the period when the first word line is deselected based on determining that an access operation is performed during the second portion of the period when the word line is deselected. In some examples, the method may include identifying that the first word line is associated with a fault, such as a short circuit fault with a digit line of the memory device.Type: ApplicationFiled: August 13, 2018Publication date: February 13, 2020Inventor: Yasushi Matsubara
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Patent number: 10553594Abstract: Apparatuses and methods for reading memory cells are described. An example method includes sharing a first voltage to increase a voltage of a first sense line coupled to a first capacitor plate of a ferroelectric capacitor of a memory cell, sharing a second voltage to decrease a voltage of a second sense line coupled to a second capacitor plate of the ferroelectric capacitor of the memory cell, sharing a third voltage to increase the voltage of the second sense line, and sharing a fourth voltage to decrease the voltage of the first sense line. A voltage difference between the first sense line and the second sense line that results from the voltage sharing is amplified, wherein the voltage difference is based at least in part on a polarity of the ferroelectric capacitor.Type: GrantFiled: September 21, 2018Date of Patent: February 4, 2020Assignee: Micron Technology, Inc.Inventor: Yasushi Matsubara
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Publication number: 20190355677Abstract: Apparatuses and methods for gate power to circuits of semiconductor devices are described. An example apparatus includes a substrate, a first wiring and a second wiring, and a plurality of transistors. The first wiring may be supplied with a power voltage, and the first wiring is formed over the substrate and is elongating in a first direction. The second wiring may be formed between the substrate and the first wiring, and vertically overlapping the first wiring with the second wiring elongating in the first direction. The plurality of transistors are vertically coupled between the first wiring and the second wiring.Type: ApplicationFiled: August 5, 2019Publication date: November 21, 2019Applicant: MICRON TECHNOLOGY, INC.Inventor: Yasushi Matsubara
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Publication number: 20190325934Abstract: Methods, systems, and devices for protecting stored data in a memory device are described. In one example, a memory device may include a set of memory cells coupled with a digit line and a plate line. A method of operating the memory device may include performing an access operation on a selected memory cell of the set of memory cells, and performing an equalization operation on a non-selected memory cell of the plurality of memory cells based on performing the access operation. The equalization operation may include applying an equal voltage to opposite terminals of the non-selected memory cell via the digit line and the plate line, which may allow built-up charge, such as leakage charge resulting from the access operation, to dissipate. Such an equalization operation may reduce a likelihood of memory loss in non-selected memory cells after access operations.Type: ApplicationFiled: April 20, 2018Publication date: October 24, 2019Inventor: Yasushi Matsubara
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Publication number: 20190311757Abstract: Methods, systems, and devices for cell bottom node reset in a memory array are described. The memory array may include a plurality of ferroelectric memory cells having a cell bottom node and a cell plate opposite the cell bottom node. A zero voltage may be applied to a plurality of digit lines in the memory array. A plurality of word lines may be activated to electrically coupled the plurality of digit lines to cell bottom node of each of the ferroelectric memory cells. Accordingly, the cell bottom node of each of the ferroelectric memory cells may be reset to the zero voltage.Type: ApplicationFiled: April 17, 2019Publication date: October 10, 2019Inventors: Kiyotake Sakurai, Yasushi Matsubara
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Publication number: 20190287602Abstract: Methods and apparatuses for erasing data on a plurality of ferroelectric memory cells in a memory cell array in a memory apparatus are disclosed. An example apparatus includes: a memory cell array including a first plurality of word lines; a digit line; and a plurality of ferroelectric memory cells; a control circuit that provides a section select signal and a word line select signal to select a second plurality of word lines among the first plurality of word lines responsive to an address; and an address decoder that activates the second plurality of word lines. Each ferroelectric memory cell includes: a ferroelectric capacitor having a first terminal coupled to a cell plate node and a second terminal coupled to a selection circuit that couples the digit line to the second terminal responsive to a signal on a corresponding word line of the second plurality of word lines.Type: ApplicationFiled: February 6, 2019Publication date: September 19, 2019Applicant: Micron Technology, Inc.Inventors: Kiyotake Sakurai, Yasushi Matsubara
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Patent number: 10373921Abstract: Apparatuses and methods for gate power to circuits of semiconductor devices are described. An example apparatus includes a substrate, a first wiring and a second wiring, and a plurality of transistors. The first wiring may be supplied with a power voltage, and the first wiring is formed over the substrate and is elongating in a first direction. The second wiring may be formed between the substrate and the first wiring, and vertically overlapping the first wiring with the second wiring elongating in the first direction. The plurality of transistors are vertically coupled between the first wiring and the second wiring.Type: GrantFiled: June 20, 2017Date of Patent: August 6, 2019Assignee: Micron Technology, Inc.Inventor: Yasushi Matsubara
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Patent number: 10311933Abstract: Methods, systems, and devices for cell bottom node reset in a memory array are described. The memory array may include a plurality of ferroelectric memory cells having a cell bottom node and a cell plate opposite the cell bottom node. A zero voltage may be applied to a plurality of digit lines in the memory array. A plurality of word lines may be activated to electrically coupled the plurality of digit lines to cell bottom node of each of the ferroelectric memory cells. Accordingly, the cell bottom node of each of the ferroelectric memory cells may be reset to the zero voltage.Type: GrantFiled: August 3, 2018Date of Patent: June 4, 2019Assignee: Micron Technology, Inc.Inventors: Kiyotake Sakurai, Yasushi Matsubara
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Patent number: 10229727Abstract: Methods and apparatuses for erasing data on a plurality of ferroelectric memory cells in a memory cell array in a memory apparatus are disclosed. An example apparatus includes: a memory cell array including a first plurality of word lines; a digit line; and a plurality of ferroelectric memory cells; a control circuit that provides a section select signal and a word line select signal to select a second plurality of word lines among the first plurality of word lines responsive to an address; and an address decoder that activates the second plurality of word lines. Each ferroelectric memory cell includes: a ferroelectric capacitor having a first terminal coupled to a cell plate node and a second terminal coupled to a selection circuit that couples the digit line to the second terminal responsive to a signal on a corresponding word line of the second plurality of word lines.Type: GrantFiled: March 13, 2018Date of Patent: March 12, 2019Assignee: Micron Technology, Inc.Inventors: Kiyotake Sakurai, Yasushi Matsubara
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Publication number: 20190066751Abstract: A memory cell comprises first, second, third, and fourth transistors individually comprising a transistor gate. First and second ferroelectric capacitors individually have one capacitor electrode elevationally between the transistor gates of the first, second, third, and fourth transistors. Other memory cells are disclosed, as are arrays of memory cells.Type: ApplicationFiled: July 31, 2018Publication date: February 28, 2019Applicant: Micron Technology, Inc.Inventor: Yasushi Matsubara
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Publication number: 20190051657Abstract: Apparatuses and methods for reading memory cells are described. An example method includes sharing a first voltage to increase a voltage of a first sense line coupled to a first capacitor plate of a ferroelectric capacitor of a memory cell, sharing a second voltage to decrease a voltage of a second sense line coupled to a second capacitor plate of the ferroelectric capacitor of the memory cell, sharing a third voltage to increase the voltage of the second sense line, and sharing a fourth voltage to decrease the voltage of the first sense line. A voltage difference between the first sense line and the second sense line that results from the voltage sharing is amplified, wherein the voltage difference is based at least in part on a polarity of the ferroelectric capacitor.Type: ApplicationFiled: September 21, 2018Publication date: February 14, 2019Applicant: MICRON TECHNOLOGY, INC.Inventor: Yasushi Matsubara
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Publication number: 20190051343Abstract: Methods, systems, and devices for cell bottom node reset in a memory array are described. The memory array may include a plurality of ferroelectric memory cells having a cell bottom node and a cell plate opposite the cell bottom node. A zero voltage may be applied to a plurality of digit lines in the memory array. A plurality of word lines may be activated to electrically coupled the plurality of digit lines to cell bottom node of each of the ferroelectric memory cells. Accordingly, the cell bottom node of each of the ferroelectric memory cells may be reset to the zero voltage.Type: ApplicationFiled: August 3, 2018Publication date: February 14, 2019Inventors: Kiyotake Sakurai, Yasushi Matsubara
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Publication number: 20180366422Abstract: Apparatuses and methods for gate power to circuits of semiconductor devices are described. An example apparatus includes a substrate, a first wiring and a second wiring, and a plurality of transistors. The first wiring may be supplied with a power voltage, and the first wiring is formed over the substrate and is elongating in a first direction. The second wiring may be formed between the substrate and the first wiring, and vertically overlapping the first wiring with the second wiring elongating in the first direction. The plurality of transistors are vertically coupled between the first wiring and the second wiring.Type: ApplicationFiled: June 20, 2017Publication date: December 20, 2018Applicant: MICRON TECHNOLOGY, INC.Inventor: YASUSHI MATSUBARA
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Patent number: 10083973Abstract: Apparatuses and methods for reading memory cells are described. An example method includes sharing a first voltage to increase a voltage of a first sense line coupled to a first capacitor plate of a ferroelectric capacitor of a memory cell, sharing a second voltage to decrease a voltage of a second sense line coupled to a second capacitor plate of the ferroelectric capacitor of the memory cell, sharing a third voltage to increase the voltage of the second sense line, and sharing a fourth voltage to decrease the voltage of the first sense line. A voltage difference between the first sense line and the second sense line that results from the voltage sharing is amplified, wherein the voltage difference is based at least in part on a polarity of the ferroelectric capacitor.Type: GrantFiled: August 9, 2017Date of Patent: September 25, 2018Assignee: Micron Technology, Inc.Inventor: Yasushi Matsubara
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Patent number: 10056129Abstract: Methods, systems, and devices for cell bottom node reset in a memory array are described. The memory array may include a plurality of ferroelectric memory cells having a cell bottom node and a cell plate opposite the cell bottom node. A zero voltage may be applied to a plurality of digit lines in the memory array. A plurality of word lines may be activated to electrically coupled the plurality of digit lines to cell bottom node of each of the ferroelectric memory cells. Accordingly, the cell bottom node of each of the ferroelectric memory cells may be reset to the zero voltage.Type: GrantFiled: August 10, 2017Date of Patent: August 21, 2018Assignee: MICRON TECHNOLOGY, INC.Inventors: Kiyotake Sakurai, Yasushi Matsubara
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Patent number: 9420271Abstract: An information processing apparatus has upper and lower LCDs different in width and an inputter such as a touch panel, or the like. A computer of the information processing apparatus displays, out of information being made up of plurality of pages, information of a predetermined page on the upper and lower LCDs so as to be fit into the width of the lower LCD, and displays, when there is a previous or next page previous or next to the predetermined page, a part of the previous or next page at blank potions on both sides of the upper LCD. Then, in response to an input from the inputter, the information of the page displayed on the upper and lower LCDs is switched to the information corresponding to the previous or next page displayed at the blank potions on the upper LCD.Type: GrantFiled: December 28, 2010Date of Patent: August 16, 2016Assignees: Nintendo Co., Ltd., HAL Laboratory, Inc.Inventors: Yasushi Matsubara, Yumi Todo, Shinichi Kawaji