Abstract: Disclosed herein is a semiconductor device that includes: a measurement circuit which measures propagation time of an internal clock signal; a delay adjustment circuit which adjusts the propagation time of the internal clock signal on the basis of a result of measurement by the measurement circuit; and a data output circuit which outputs a data signal in synchronization with the internal clock signal.

Abstract: For example, to include plural data input/output terminals and a strobe terminal that are electrically connected in common by a test probe, a command address terminal that is connected to a test probe, and an output control circuit that performs a selecting operation of data output circuits based on a signal that is supplied to the command address terminal. According to the present invention, it is possible to perform a test that uses non-compressed actual data while allocating plural data input/output terminals to one determination circuit within a tester. With this configuration, it is possible to test a large number of semiconductor devices in parallel by using a limited number of determination circuits within the tester.

Abstract: An information processing apparatus has upper and lower LCDs different in width and an inputter such as a touch panel, or the like. A computer of the information processing apparatus displays, out of information being made up of plurality of pages, information of a predetermined page on the upper and lower LCDs so as to be fit into the width of the lower LCD, and displays, when there is a previous or next page previous or next to the predetermined page, a part of the previous or next page at blank potions on both sides of the upper LCD. Then, in response to an input from the inputter, the information of the page displayed on the upper and lower LCDs is switched to the information corresponding to the previous or next page displayed at the blank potions on the upper LCD.

Abstract: First, a plurality of selection objects having at least one part thereof displayed on a display area of a display device are moved relative to the display area, based on an output signal outputted from an input device. Then, when an end-located selection object among the moved plurality of selection objects reaches a predetermined position of the display area, an object that is different from the plurality of selection objects is displayed on the display area. The object moves relative to the display area based on an output signal outputted from the input device.

Abstract: For example, to include plural data input/output terminals and a strobe terminal that are electrically connected in common by a test probe, a command address terminal that is connected to a test probe, and an output control circuit that performs a selecting operation of data output circuits based on a signal that is supplied to the command address terminal. According to the present invention, it is possible to perform a test that uses non-compressed actual data while allocating plural data input/output terminals to one determination circuit within a tester. With this configuration, it is possible to test a large number of semiconductor devices in parallel by using a limited number of determination circuits within the tester.

Abstract: When a predetermined code is set to a mode register, a switching signal generating circuit is activated, and a switching signal TCLKE becomes at a high level. When the switching signal TCLKE becomes at a high level, input data supplied from a data input and output terminal DQ is used as an internal clock ICLK. Accordingly, during a test in a wafer state, a clock signal can be received from the data input and output terminal DQ, even when a clock terminal, an address terminal, and a command terminal are connected in common to plural semiconductor memory devices. Therefore, a code for artificially performing a fine adjustment of a reference voltage can be individually supplied for each chip.

Abstract: A plurality of series circuits each consisting of a current-carrying element and an element to be measured are provided between a power supply potential VDD and a ground potential VSS. The current-carrying elements are supplied with a test signal commonly, and corresponding selection signals, respectively. After a mode is set so that power consumption of a main circuit unit included in a semiconductor device is substantially zero or almost constant, the elements to be measured are energized sequentially and, in this state, a power supply current that flows through the semiconductor device is measured sequentially. Accordingly, it is possible to accurately know the power consumption of the element to be measured and it is also possible to know the characteristics of the element to be measured based thereon.

Abstract: A power-on reset circuit includes a detection-voltage producing circuit that produces a detection voltage proportional to a power-supply voltage, and a power-on determining circuit that activates a power-on reset signal when a detection voltage is less than the power-on determining voltage and inactivates the power-on reset signal when the detection voltage is equal to or greater than the power-on determining voltage. In the detection-voltage producing circuit, a fuse element used for adjusting a proportional constant between a power-supply voltage and the detection voltage is arranged. Thereby, the power-on determining voltage becomes adjustable. Accordingly, the power-on determining voltage can be made closer to a design value when there is a deviation from the design value in the power-on determining voltage after the semiconductor device is manufactured.

Abstract: Disclosed is a semiconductor device having an output circuit that may be used to advantage in case the semiconductor device may possibly be used under different power supply voltages. The semiconductor device includes a signal terminal having at least the function of an output terminal, a power supply terminal, and an output circuit having first and second output buffer circuits. The first and second output buffer circuits are supplied with a supply power voltage from the power supply terminal and receive an inner output signal to drive the signal terminal. The semiconductor device also includes a power supply voltage discrimination circuit that discriminates the potential level of the power supply voltage to control the operation of the output circuit based on the result of discrimination. A first output buffer circuit is activated and a second output buffer circuit is deactivated in case the power supply voltage discrimination circuit has decided that the power supply voltage is at a first potential.

Abstract: A semiconductor device includes a plurality of bonding pads as bonding option, and a test circuit for performing an operation test using particular bonding pads and testing interconnects connecting internal circuits to the remaining bonding pads which are not used in the operation test.

Abstract: A potential level of a word line when it is inactive is made different between during a self-refresh operation and during other than the self-refresh operation. The potential level is set to a ground potential GND during the self-refresh operation and set to a negative potential during other than the self-refresh operation.

Abstract: A semiconductor memory device includes a sense amplifier SA, a pair of bit lines BLT, BLB, a transfer switch SW provided between the sense amplifier SA and the pair of bit lines BLT, BLB, a precharge circuit PC that precharges the sense amplifier SA and the pair of bit lines BLT, BLB at the same potential, and a control circuit CTL. The control circuit CTL sets the transfer switch SW in the off state in the state before data is written or read, and turns on the transfer switch SW when writing or reading data via the pair of bit lines BLT, BLB. With this arrangement, a defective current flowing to the sense amplifier SA can be decreased, even when a word line WL and a bit line BL are shortcircuited.

Abstract: A semiconductor memory device comprises a memory cell array having a hierarchical word line structure including main word lines and sub-word lines; a main word driver for driving a non-selected main word line to high and for driving and activating a selected main word line to low; and a sub-word driver having a PMOS transistor whose gate is connected to the main word line for selectively activating the sub-word line corresponding to the selected main word line. The memory cell array is divided into a plurality of areas which is controlled such that a high level of each main word line is set to a first boost voltage in a predetermined area including the selected main word line, and a high level of each main word line is set to a second boost voltage lower than the first boost voltage in the other area.

Abstract: A semiconductor device employs two electric fuses (31, 32) connected in parallel to each other. First terminals of the electric fuses (31, 32) are connected to a junction of first and second P-channel transistors (21, 22), which are connected in series between a high potential application line (111) and a ground, and connected to a third P-channel transistor (23). Second terminals of the electric fuses (31, 32) are connected to a low potential application line (121). When an extra-high voltage is applied between the first and second terminals of the electric fuses (31, 32), a breakdown connection is produced in at least one of the electric fuses (31, 32). Thus, 1-bit information is written into the semiconductor device.

Abstract: When a predetermined code is set to a mode register, a switching signal generating circuit is activated, and a switching signal TCLKE becomes at a high level. When the switching signal TCLKE becomes at a high level, input data supplied from a data input and output terminal DQ is used as an internal clock ICLK. Accordingly, during a test in a wafer state, a clock signal can be received from the data input and output terminal DQ, even when a clock terminal, an address terminal, and a command terminal are connected in common to plural semiconductor memory devices. Therefore, a code for artificially performing a fine adjustment of a reference voltage can be individually supplied for each chip.

Abstract: When a predetermined code is set to a mode register, a switching signal generating circuit is activated, and a switching signal TCLKE becomes at a high level. When the switching signal TCLKE becomes at a high level, input data supplied from a data input and output terminal DQ is used as an internal clock ICLK. Accordingly, during a test in a wafer state, a clock signal can be received from the data input and output terminal DQ, even when a clock terminal, an address terminal, and a command terminal are connected in common to plural semiconductor memory devices. Therefore, a code for artificially performing a fine adjustment of a reference voltage can be individually supplied for each chip.

Abstract: A semiconductor device includes a plurality of bonding pads as bonding option, and a test circuit for performing an operation test using particular bonding pads and testing interconnects connecting internal circuits to the remaining bonding pads which are not used in the operation test.

Abstract: A word line driving circuit has a main word driver for producing first and second main word driver output signals and a subsidiary word driver for driving a word line. The subsidiary word driver has a load transistor supplied with the first main word driver output signal and a driver transistor supplied with the second word driver output signal. The subsidiary word driver has a state putting circuit for putting the word line into one of a high level, a low level, and a high impedance state.

Abstract: A reference potential generating circuit has a current mirror amplifier (CM11) supplied with an input reference potential and a feedback level, an output transistor (QP11) supplied with an output of the current mirror amplifier as an input and producing an output reference potential as an output, a monitoring portion (R11 and R12) for generating the feedback level from the output of the output transistor, a first switch (QN11) for controlling supply of a power supply potential (VSS}) to the current mirror amplifier, a second switch (QN12) for controlling supply of the power supply potential (VSS) to the monitoring portion, and an output switch (TSW12) for controlling connection of the output of the output transistor to a next stage. The first and the second switches and the output switch are simultaneously turned off. When a first predetermined period elapses after the first and the second switches and the output switch are turned off, the first and the second switches are turned on.

Abstract: A potential level of a word line when it is inactive is made different between during a self-refresh operation and during other than the self-refresh operation. The potential level is set to a ground potential GND during the self-refresh operation and set to a negative potential during other than the self-refresh operation.