Abstract: A semiconductor memory device includes a sense amplifier SA, a pair of bit lines BLT, BLB, a transfer switch SW provided between the sense amplifier SA and the pair of bit lines BLT, BLB, a precharge circuit PC that precharges the sense amplifier SA and the pair of bit lines BLT, BLB at the same potential, and a control circuit CTL. The control circuit CTL sets the transfer switch SW in the off state in the state before data is written or read, and turns on the transfer switch SW when writing or reading data via the pair of bit lines BLT, BLB. With this arrangement, a defective current flowing to the sense amplifier SA can be decreased, even when a word line WL and a bit line BL are shortcircuited.

Abstract: A semiconductor memory device comprises a memory cell array having a hierarchical word line structure including main word lines and sub-word lines; a main word driver for driving a non-selected main word line to high and for driving and activating a selected main word line to low; and a sub-word driver having a PMOS transistor whose gate is connected to the main word line for selectively activating the sub-word line corresponding to the selected main word line. The memory cell array is divided into a plurality of areas which is controlled such that a high level of each main word line is set to a first boost voltage in a predetermined area including the selected main word line, and a high level of each main word line is set to a second boost voltage lower than the first boost voltage in the other area.

Abstract: A plurality of series circuits each consisting of a current-carrying element and an element to be measured are provided between a power supply potential VDD and a ground potential VSS. The current-carrying elements are supplied with a test signal commonly, and corresponding selection signals, respectively. After a mode is set so that power consumption of a main circuit unit included in a semiconductor device is substantially zero or almost constant, the elements to be measured are energized sequentially and, in this state, a power supply current that flows through the semiconductor device is measured sequentially. Accordingly, it is possible to accurately know the power consumption of the element to be measured and it is also possible to know the characteristics of the element to be measured based thereon.

Abstract: When a predetermined code is set to a mode register, a switching signal generating circuit is activated, and a switching signal TCLKE becomes at a high level. When the switching signal TCLKE becomes at a high level, input data supplied from a data input and output terminal DQ is used as an internal clock ICLK. Accordingly, during a test in a wafer state, a clock signal can be received from the data input and output terminal DQ, even when a clock terminal, an address terminal, and a command terminal are connected in common to plural semiconductor memory devices. Therefore, a code for artificially performing a fine adjustment of a reference voltage can be individually supplied for each chip.

Abstract: A reference potential generating circuit has a current mirror amplifier (CM11) supplied with an input reference potential and a feedback level, an output transistor (QP11) supplied with an output of the current mirror amplifier as an input and producing an output reference potential as an output, a monitoring portion (R11 and R12) for generating the feedback level from the output of the output transistor, a first switch (QN11) for controlling supply of a power supply potential (VSS}) to the current mirror amplifier, a second switch (QN12) for controlling supply of the power supply potential (VSS) to the monitoring portion, and an output switch (TSW12) for controlling connection of the output of the output transistor to a next stage. The first and the second switches and the output switch are simultaneously turned off. When a first predetermined period elapses after the first and the second switches and the output switch are turned off, the first and the second switches are turned on.

Abstract: A word line driving circuit has a main word driver for producing first and second main word driver output signals and a subsidiary word driver for driving a word line. The subsidiary word driver has a load transistor supplied with the first main word driver output signal and a driver transistor supplied with the second word driver output signal. The subsidiary word driver has a state putting circuit for putting the word line into one of a high level, a low level, and a high impedance state.

Abstract: A redundancy replacement judging circuit includes a redundancy replacement judging circuit chain and a pseudo redundancy replacement judging circuit chain substantially equal in delay time to the redundancy replacement judging circuit chain. In response to an output of the pseudo redundancy replacement judging circuit chain, the redundancy replacement judging circuit outputs a redundancy judgment result of the redundancy replacement judging circuit chain. A semiconductor memory device includes the redundancy replacement judging circuit.

Abstract: A semiconductor device employs two electric fuses (31, 32) connected in parallel to each other. First terminals of the electric fuses (31, 32) are connected to a junction of first and second P-channel transistors (21, 22), which are connected in series between a high potential application line (111) and a ground, and connected to a third P-channel transistor (23). Second terminals of the electric fuses (31, 32) are connected to a low potential application line (121). When an extra-high voltage is applied between the first and second terminals of the electric fuses (31, 32), a breakdown connection is produced in at least one of the electric fuses (31, 32). Thus, 1-bit information is written into the semiconductor device.

Abstract: A redundancy replacement judging circuit includes a redundancy replacement judging circuit chain and a pseudo redundancy replacement judging circuit chain substantially equal in delay time to the redundancy replacement judging circuit chain. In response to an output of the pseudo redundancy replacement judging circuit chain, the redundancy replacement judging circuit outputs a redundancy judgment result of the redundancy replacement judging circuit chain. A semiconductor memory device includes the redundancy replacement judging circuit.

Abstract: A semiconductor memory device which can reduce the frequency of a CBR (column before row) refresh operation comprises a memory cell array having a plurality of memory cells, and a CBR refresh unit responsive to m receptions of CBR refresh commands for performing a refresh operation once for the memory cell array.

Abstract: A semiconductor memory device which can reduce the frequency of a CBR (column before row) refresh operation comprises a memory cell array having a plurality of memory cells, and a CBR refresh unit responsive to m receptions of CBR refresh commands for performing a refresh operation once for the memory cell array.

Abstract: A semiconductor memory device according to the invention comprises a first memory cell region, a second memory cell region, and a sense-amplifier row region disposed between the first and second memory cell regions, wherein the sense-amplifier row region has therein a plurality of transistor rows constituting a plurality of sense-amplifiers, at least one power-supply side sense-amplifier driver transistor disposed on the side f the first memory cell region of the plurality of transistor rows, and at least one ground side sense-amplifier driver transistor disposed on the side of the second memory cell region of the plurality of transistor rows.

Abstract: A synchronous type dynamic random access memory (SDRAM) includes a memory cell array section having an address decoder section and a sense amplifier section, a power down signal generating section, a control signal generating section and an accessing section. The power down signal generating section generates a first power down signal and a second power down signal based on a clock enable signal, an external clock signal, a signal specific to the SDRAM and a write burst signal. The first power down signal is inactive during a predetermined time period synchronous with the specific signal, and the second power down signal is inactive during the predetermined time period and during a time period during which the write burst signal is supplied. The control signal generating section generates a control signal based on a command signal when the first power down signal is inactive.

Abstract: According to one embodiment (100), a synchronous semiconductor memory may include a first initial circuit (102), second initial circuit (104) and third initial circuit (106). The first initial circuit (102) can receive an external clock signal CLK and compare the external clock signal CLK to a reference voltage VREF. The comparison result can be amplified and output as a signal .phi.1. The second initial circuit (104) can receive a clock control signal CKE and compare the clock control signal CKE to a reference voltage VREF. The comparison result can be amplified and output as a signal .phi.2. The third initial circuit (106) can receive the external clock signal CLK, and is activated by a control signal .phi.7 that can correspond to the clock enable signal CKE. The third initial circuit (106) can compare the external clock signal CLK to a reference voltage VREF, and amplify and output the comparison result .phi.8. The embodiment (100) can further include a first control circuit (108) that can receive the .

Abstract: In a synchronous DRAM including a register having an input gate and an output gate, for holding read-out data between the input gate and the output gate by opening the input gate, and for transferring or outputting the held data by opening the output gate. An input gate control circuit for controlling an open/close of the input gate is supplied with a output switch feedback signal in the form of a one-shot pulse generated by an output gate control circuit for controlling an open/close of the output gate, in synchronism with an output gate switch signal, so that only after the data held in the register has been outputted to an external of the register, the next data to be succeedingly transferred from the read/write bus to the register is actually latched in the register.

Abstract: In a semiconductor memory including a plurality of synchronous DRAMs controlled by one common memory controller, each of the synchronous DRAMs has first and second terminals for receiving a reference clock supplied from the memory controller. A signal line for this reference clock is laid out in such a manner that the signal line is connected from the memory controller firstly to the first terminal of the most remote synchronous DRAM, and then, to respective first terminals of the remaining synchronous DRAMs, in order, towards the nearest synchronous DRAM and further, to the second terminal of the nearest synchronous DRAM, and then, to respective second terminals of the remaining synchronous DRAMs, in order, towards the most remote synchronous DRAM.

Abstract: A semiconductor memory device disclosed which has an optimized read time in the reading operation. It is realized that both the wiring delay of a control signal bus 903 and a wiring delay of a data signal bus 412 are set equivalently. For example, an amplifier circuit 419 is received a read-out data through the data signal bus 412 and amplifies the read-out data in response to a enable signal 510. In this case, the enable signal 510 is generated by an amplifier control circuit 904 in response to a delay control signal which is through the control bus 903. Since the enable signal 510 which activates the amplifier circuit 419 is generated at a most preferred timing, thereby the data reading-out speed can be increased up to its limit speed.

Abstract: In a DRAM device including a plurality of main row decoders and a plurality of sub row decoders, each of the main row decoders is connected to only one main word line. Each of the sub row decoders is connected to one main word line and a plurality of sub word lines. One or more of the sub word lines are activated in accordance with the activated main word line and the sub row decoders.

Abstract: A signal receiver for an interface of an MPU or a memory has a differential amplifier for receiving an input signal from an input/output line for the IPU and the memory, an inverter for receiving the output of the differential amplifier, and a feed-back section for providing the signal receiver with a transfer characteristic having a hysteresis with respect to the input signal of tile signal receiver. The feed-back section includes a feed-back signal path and a feed-back current path formed between a supply line and the output of the differential amplifier. The output signal of the gate is feed-backed to the feed-back current path as a control signal for making the feed-back current path active or inactive to shift tile voltage level of the output of the differential amplifier. The gate is not operated by a transient oscillation of the input signal so that unnecessary power consumption due to tile transient oscillation of the input of tile signal receiver is avoided.

Abstract: A semiconductor circuit device includes a differential amplifier circuit having a first parasitic capacitor formed between the semiconductor substrate and a first resistor and a second parasitic capacitor formed between the semiconductor substrate and a second resistor. Each of the first and the second resistors is implemented by a wiring pattern over the substrate so that the first and the second parasitic capacitors are equivalent to each other.