Patents by Inventor Yasuyuki Kimura

Yasuyuki Kimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7450921
    Abstract: The invention provides a communication semiconductor integrated circuit (RF IC) that, when a transmission oscillator is incorporated into a semiconductor chip, secures the oscillation operation over a wide frequency range, prevents a deterioration of a transmission spectrum, and thereby enhances the accuracy of an oscillation frequency. The integrated circuit corrects a dispersion of the KV characteristic of the transmission oscillator by calibrating a current Icp of the charge pump inside the phase control loop. More in concrete, the integrated circuit measures a KV value Kv of the transmission oscillator, and calibrates the current Icp of the charge pump so that Kv·Icp falls into a predetermined value.
    Type: Grant
    Filed: January 11, 2007
    Date of Patent: November 11, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Satoshi Arayashiki, Hirotaka Oosawa, Noriyuki Kurakami, Akira Okasaka, Yasuyuki Kimura, Toshiya Uozumi, Hirokazu Miyagawa, Satoshi Tanaka
  • Publication number: 20080271806
    Abstract: Glass cloth which is formed of a warp yarn and a weft yarn of the same glass yarn, wherein a ratio of warp yarn width to weft yarn width is not less than and not more than 1.20 and a ratio of an elongation rate in a length direction when a load in a range of 25 N to 100 N per 25 mm width of the glass cloth is added in a warp yarn direction, to an elongation rate in a width direction when said load is added in a weft yarn direction is not less than 0.80 and not more than 1.20.
    Type: Application
    Filed: April 10, 2008
    Publication date: November 6, 2008
    Inventors: Yoshinobu Fujimura, Yasuyuki Kimura
  • Patent number: 7433653
    Abstract: A transmitter adopting a polar loop system including a phase control loop for controlling the phase of a carrier signal outputted from a transmitting oscillator and an amplitude control loop for controlling the amplitude of a transmitting output signal outputted from a power amplification circuit, and designed to be capable of performing transmission using a GMSK modulation mode and transmission using an 8-PSK modulation mode. In the transmitter, the phase control loop is shared as a phase control loop for use in the GMSK modulation mode and a phase control loop for use in the 8-PSK modulation mode. A component similar to any one of components constituting a loop filter is provided in parallel therewith so that the component can be connected or disconnected in accordance with the modulation mode, for example, by use of a switching element.
    Type: Grant
    Filed: June 18, 2007
    Date of Patent: October 7, 2008
    Assignees: Renesas Technology Corp., TTPCOM Limited
    Inventors: Ryoichi Takano, Kazuhiko Hikasa, Yasuyuki Kimura, Hiroshi Hagisawa, Patrick Wurm, Robert Astle Henshaw, David Freeborough
  • Publication number: 20080137072
    Abstract: A sheet recognizing device and method for precisely checking the authentication of a sheet by performing recognition of color and watermark of a sheet and detecting the subtle characteristic of a hue ink printed on one side of the sheet.
    Type: Application
    Filed: November 11, 2005
    Publication date: June 12, 2008
    Inventors: Eiji Itako, Yasuyuki Kimura, Futoshi Houjo, Satoru Tsurumaki, Seiji Takamatsu
  • Publication number: 20070273415
    Abstract: A semiconductor integrated circuit having a built-in PLL circuit which has two charge pump circuits for charging and discharging capacitive elements of a loop filter in response to signals generated by a phase comparator circuit. One of the two charge pump circuits has current sources which generate current values smaller than those generated by current sources of the other charge pump circuit. The loop filter has a first capacitive element connected to a charge/discharge node, and a second capacitive element connected to the charge/discharge node through a resistive element. The first capacitive element is charged and discharged by the one charge pump circuit, while the second capacitive element is charged and discharged by the other charge pump circuit. A charging current source of the one charge pump circuit operates simultaneously with a discharging current source of the other charge pump circuit, i.e., the charge pump circuits operate in opposite phase.
    Type: Application
    Filed: April 4, 2007
    Publication date: November 29, 2007
    Inventors: Yasuyuki Kimura, Satoshi Shimizu, Masakatsu Yokota, Ken Suyama, Aleksander Dec
  • Publication number: 20070249297
    Abstract: A transmitter adopting a polar loop system including a phase control loop for controlling the phase of a carrier signal outputted from a transmitting oscillator and an amplitude control loop for controlling the amplitude of a transmitting output signal outputted from a power amplification circuit, and designed to be capable of performing transmission using a GMSK modulation mode and transmission using an 8-PSK modulation mode. In the transmitter, the phase control loop is shared as a phase control loop for use in the GMSK modulation mode and a phase control loop for use in the 8-PSK modulation mode. A component similar to any one of components constituting a loop filter is provided in parallel therewith so that the component can be connected or disconnected in accordance with the modulation mode, for example, by use of a switching element.
    Type: Application
    Filed: June 18, 2007
    Publication date: October 25, 2007
    Inventors: Ryoichi Takano, Kazuhiko Hikasa, Yasuyuki Kimura, Hiroshi Hagisawa, Patrick Wurm, Robert Henshaw, David Freeborough
  • Publication number: 20070244589
    Abstract: A demand prediction apparatus connected to an order reception record storage unit for storing an order reception record of a product and an association information storage unit for storing association information associating products with each other, first acquires identification information of a product for which demand prediction is to be performed. The demand prediction apparatus specifies a product associated with the product having the acquired identification information based on the association information stored in the association information storage unit, and acquires an order reception record of the specified product from the order reception record storage unit. The demand prediction apparatus derives a demand prediction function that is fitted to the order reception record, by using the acquired order reception record.
    Type: Application
    Filed: April 18, 2007
    Publication date: October 18, 2007
    Inventors: Takenori OKU, Makiko Watanabe, Yasuyuki Kimura, Fumihiro Nagano, Seiji Adachi
  • Patent number: 7269402
    Abstract: A semiconductor integrated circuit device for communication is provided with a PLL circuit or the like formed therein, the PLL circuit which is capable of realizing the compensation of fluctuation due to temperature change, the inhibition of increase in the chip area and the ensurement of the performance margin, and which controls a VCO having multiple oscillation frequency bands. In the case where automatic calibration is performed by switching a switch to a side of a DC voltage source in the PLL circuit using a VCO having multiple oscillation bands, a tuning voltage (Vtune) of an RFVCO is fixed to a voltage value of a DC voltage source. However, since a temperature characteristic of canceling a VCO oscillation frequency is given to the DC voltage source, it is possible to minimize the influence on the band selection when a calibration table comes to no optimum one.
    Type: Grant
    Filed: July 25, 2006
    Date of Patent: September 11, 2007
    Assignees: Renesas Technology Corp., TTP Com Limited
    Inventors: Toshiya Uozumi, Satoshi Tanaka, Masumi Kasahara, Hirotaka Oosawa, Yasuyuki Kimura, Robert Astle Henshaw
  • Patent number: 7263340
    Abstract: A semiconductor integrated circuit device for communication is provided with a PLL circuit or the like formed therein, the PLL circuit which is capable of realizing the compensation of fluctuation due to temperature change, the inhibition of increase in the chip area and the ensurement of the performance margin, and which controls a VCO having multiple oscillation frequency bands. In the case where automatic calibration is performed by switching a switch to a side of a DC voltage source in the PLL circuit using a VCO having multiple oscillation bands, a tuning voltage (Vtune) of an RFVCO is fixed to a voltage value of a DC voltage source. However, since a temperature characteristic of canceling a VCO oscillation frequency is given to the DC voltage source, it is possible to minimize the influence on the band selection when a calibration table comes to no optimum one.
    Type: Grant
    Filed: July 25, 2006
    Date of Patent: August 28, 2007
    Assignees: Renesas Technology Corporation, TTP Com Limited
    Inventors: Toshiya Uozumi, Satoshi Tanaka, Masumi Kasahara, Hirotaka Oosawa, Yasuyuki Kimura, Robert Astle Henshaw
  • Publication number: 20070188203
    Abstract: A semiconductor integrated circuit having a built-in PLL circuit which has two charge pump circuits for charging and discharging capacitive elements of a loop filter in response to signals generated by a phase comparator circuit. One of the two charge pump circuits has current sources which generate current values smaller than those generated by current sources of the other charge pump circuit. The loop filter has a first capacitive element connected to a charge/discharge node, and a second capacitive element connected to the charge/discharge node through a resistive element. The first capacitive element is charged and discharged by the one charge pump circuit, while the second capacitive element is charged and discharged by the other charge pump circuit. A charging current source of the one charge pump circuit operates simultaneously with a discharging current source of the other charge pump circuit, i.e., the charge pump circuits operate in opposite phase.
    Type: Application
    Filed: March 30, 2007
    Publication date: August 16, 2007
    Inventors: Yasuyuki Kimura, Satoshi Shimizu, Masakatsu Yokota, Ken Suyama, Aleksander Dec
  • Publication number: 20070190879
    Abstract: A double glass cloth for a printed wiring board, characterized in that it is a glass cloth composed of warps and wefts and has a double structure comprising a face side structure and a back side structure, wherein said face side structure and said back side structure are bound with a woven structure into one piece.
    Type: Application
    Filed: February 8, 2005
    Publication date: August 16, 2007
    Inventors: Yoshinori Gondoh, Makoto Someya, Yasuyuki Kimura
  • Patent number: 7248842
    Abstract: A transmitter adopting a polar loop system including a phase control loop for controlling the phase of a carrier signal outputted from a transmitting oscillator and an amplitude control loop for controlling the amplitude of a transmitting output signal outputted from a power amplification circuit, and designed to be capable of performing transmission using a GMSK modulation mode and transmission using an 8-PSK modulation mode. In the transmitter, the phase control loop is shared as a phase control loop for use in the GMSK modulation mode and a phase control loop for use in the 8-PSK modulation mode. A component similar to any one of components constituting a loop filter is provided in parallel therewith so that the component can be connected or disconnected in accordance with the modulation mode, for example, by use of a switching element.
    Type: Grant
    Filed: May 30, 2006
    Date of Patent: July 24, 2007
    Assignees: Renesas Technology Corp., Tipcom Limited
    Inventors: Ryoichi Takano, Kazuhiko Hikasa, Yasuyuki Kimura, Hiroshi Hagisawa, Patrick Wurm, Robert Astle Henshaw, David Freeborough
  • Publication number: 20070164828
    Abstract: In a communication semiconductor integrated circuit device using offset PLL architectures and including an oscillator circuit and a frequency divider circuit generating an intermediate frequency signal, the oscillator circuit includes an oscillator, a programmable frequency divider which frequency-divides the oscillation signal in accordance with frequency division information, a phase comparator detecting a phase difference between an output signal of the programmable frequency divider and a reference signal, and a frequency control unit for outputting a signal indicative of the phase difference and controlling the oscillation frequency of the oscillator, wherein a frequency division ratio generator circuit generates an integer part I and a fraction part F/G based on band information concerning the use frequency band and mode information along with channel information and for producing the frequency division ratio information to thereby give it to the programmable frequency divider.
    Type: Application
    Filed: March 26, 2007
    Publication date: July 19, 2007
    Inventors: Toshiya Uozumi, Yasuyuki Kimura, Hirotaka Osawa, Satoru Yamamoto, Robert Henshaw
  • Publication number: 20070161360
    Abstract: In a communication semiconductor integrated circuit device using offset PLL architectures and including an oscillator circuit and a frequency divider circuit generating an intermediate frequency signal, the oscillator circuit includes an oscillator, a programmable frequency divider which frequency-divides the oscillation signal in accordance with frequency division information, a phase comparator detecting a phase difference between an output signal of the programmable frequency divider and a reference signal, and a frequency control unit for outputting a signal indicative of the phase difference and controlling the oscillation frequency of the oscillator, wherein a frequency division ratio generator circuit generates an integer part I and a fraction part F/G based on band information concerning the use frequency band and mode information along with channel information and for producing the frequency division ratio information to thereby give it to the programmable frequency divider.
    Type: Application
    Filed: March 26, 2007
    Publication date: July 12, 2007
    Inventors: Toshiya Uozumi, Yasuyuki Kimura, Hirotaka Osawa, Satoru Yamamoto, Robert Henshaw
  • Publication number: 20070111675
    Abstract: The invention provides a communication semiconductor integrated circuit (RF IC) that, when a transmission oscillator is incorporated into a semiconductor chip, secures the oscillation operation over a wide frequency range, prevents a deterioration of a transmission spectrum, and thereby enhances the accuracy of an oscillation frequency. The integrated circuit corrects a dispersion of the KV characteristic of the transmission oscillator by calibrating a current Icp of the charge pump inside the phase control loop. More in concrete, the integrated circuit measures a KV value Kv of the transmission oscillator, and calibrates the current Icp of the charge pump so that Kv·Icp falls into a predetermined value.
    Type: Application
    Filed: January 11, 2007
    Publication date: May 17, 2007
    Inventors: Satoshi Arayashiki, Hirotaka Oosawa, Noriyuki Kurakami, Akira Okasaka, Yasuyuki Kimura, Toshiya Uozumi, Hirokazu Miyagawa, Satoshi Tanaka
  • Publication number: 20070104098
    Abstract: An RF signal processing integrated circuit has a first operation mode in which the operation setting of a time slot is executed using one time slot as one setting unit and a second operation mode in which the operation setting of a time slot is executed using plural time slots as one setting unit. In which mode the circuit is set is determined according to bit information contained in an instruction for the initialization, the mode setting, or the time slot setting. It is thus possible to enhance the degree of freedom in the operation setting of a time slot in a mobile communication terminal capable of making communications with the base station by a communication method employing the time-division multiple access (TDMA) method.
    Type: Application
    Filed: November 2, 2006
    Publication date: May 10, 2007
    Inventors: Yasuyuki Kimura, Yasuo Shima, Noriyuki Kurakami
  • Patent number: 7212047
    Abstract: A semiconductor integrated circuit having a built-in PLL circuit which has two charge pump circuits for charging and discharging capacitive elements of a loop filter in response to signals generated by a phase comparator circuit. One of the two charge pump circuits has current sources which generate current values smaller than those generated by current sources of the other charge pump circuit. The loop filter has a first capacitive element connected to a charge/discharge node, and a second capacitive element connected to the charge/discharge node through a resistive element. The first capacitive element is charged and discharged by the one charge pump circuit, while the second capacitive element is charged and discharged by the other charge pump circuit. A charging current source of the one charge pump circuit operates simultaneously with a discharging current source of the other charge pump circuit, i.e., the charge pump circuits operate in opposite phase.
    Type: Grant
    Filed: October 4, 2005
    Date of Patent: May 1, 2007
    Assignees: Renesas Technology Corp., Epoch Microelectronics, Inc.
    Inventors: Yasuyuki Kimura, Satoshi Shimizu, Masakatsu Yokota, Ken Suyama, Aleksander Dec
  • Patent number: 7205850
    Abstract: In a communication semiconductor integrated circuit device using offset PLL architectures and including an oscillator circuit and a frequency divider circuit generating an intermediate frequency signal, the oscillator circuit includes an oscillator, a programmable frequency divider which frequency-divides the oscillation signal in accordance with frequency division information, a phase comparator detecting a phase difference between an output signal of the programmable frequency divider and a reference signal, and a frequency control unit for outputting a signal indicative of the phase difference and controlling the oscillation frequency of the oscillator, wherein a frequency division ratio generator circuit generates an integer part I and a fraction part F/G based on band information concerning the use frequency band and mode information along with channel information and for producing the frequency division ratio information to thereby give it to the programmable frequency divider.
    Type: Grant
    Filed: July 15, 2005
    Date of Patent: April 17, 2007
    Assignees: Renesas Technology Corp., TTPCom Limited
    Inventors: Toshiya Uozumi, Yasuyuki Kimura, Hirotaka Osawa, Satoru Yamamoto, Robert Astel Henshaw
  • Patent number: 7187911
    Abstract: The invention provides a communication semiconductor integrated circuit (RF IC) that, when a transmission oscillator is incorporated into a semiconductor chip, secures the oscillation operation over a wide frequency range, prevents a deterioration of a transmission spectrum, and thereby enhances the accuracy of an oscillation frequency. The integrated circuit corrects a dispersion of the KV characteristic of the transmission oscillator by calibrating a current Icp of the charge pump inside the phase control loop. More in concrete, the integrated circuit measures a KV value Kv of the transmission oscillator, and calibrates the current Icp of the charge pump so that Kv·Icp falls into a predetermined value.
    Type: Grant
    Filed: June 8, 2004
    Date of Patent: March 6, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Satoshi Arayashiki, Hirotaka Oosawa, Noriyuki Kurakami, Akira Okasaka, Yasuyuki Kimura, Toshiya Uozumi, Hirokazu Miyagawa, Satoshi Tanaka
  • Publication number: 20060263101
    Abstract: A sheet paper identification apparatus and method for stably identifying a sheet paper while preventing erroneous identification caused by dust adhered to an imaging section and caused by fluctuation in illumination brightness. An imaging section (7) images the interior of the imaging section (7) before a sheet paper is fed to capture image data on an image showing no sheet paper. When a sheet paper is fed into the imaging section (7), the imaging section (7) images the sheet paper and captures image data on an image showing a sheet paper. An image data analyzing section (8) creates a density histogram of the image showing no sheet paper from the image data on the image showing no sheet paper and detects dust adhered to the imaging section (7) on the basis of the density histogram. If the amount of particles exceeds a reference value, the image data analyzing section (8) sends a report about the abnormality of the imaging section (7) to a control section (2).
    Type: Application
    Filed: April 23, 2004
    Publication date: November 23, 2006
    Inventors: Seiji Takamatsu, Satoru Tsurumarki, Yasuyuki Kimura