Patents by Inventor Yi-Cheng CHIU

Yi-Cheng CHIU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11424359
    Abstract: A high-voltage semiconductor device structure is provided. The high-voltage semiconductor device structure includes a semiconductor substrate, a source ring in the semiconductor substrate, and a drain region in the semiconductor substrate. The high-voltage semiconductor device structure also includes a doped ring surrounding sides and a bottom of the source ring and a well region surrounding sides and bottoms of the drain region and the doped ring. The well region has a conductivity type opposite to that of the doped ring. The high-voltage semiconductor device structure further includes a conductor electrically connected to the drain region and extending over and across a periphery of the well region. In addition, the high-voltage semiconductor device structure includes a shielding element ring between the conductor and the semiconductor substrate. The shielding element ring extends over and across the periphery of the well region.
    Type: Grant
    Filed: January 6, 2021
    Date of Patent: August 23, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Chou Lin, Yi-Cheng Chiu, Karthick Murukesan, Yi-Min Chen, Shiuan-Jeng Lin, Wen-Chih Chiang, Chen-Chien Chang, Chih-Yuan Chan, Kuo-Ming Wu, Chun-Lin Tsai
  • Publication number: 20220231133
    Abstract: A method for manufacturing a device may include providing an ultra-high voltage (UHV) component that includes a source region and a drain region, and forming an oxide layer on a top surface of the UHV component. The method may include connecting a low voltage terminal to the source region of the UHV component, and connecting a high voltage terminal to the drain region of the UHV component. The method may include forming a shielding structure on a surface of the oxide layer provided above the drain region of the UHV component, forming a high voltage interconnection that connects to the shielding structure and to the high voltage terminal, and forming a metal routing that connects the shielding structure and the low voltage terminal.
    Type: Application
    Filed: January 15, 2021
    Publication date: July 21, 2022
    Inventors: Yi-Cheng CHIU, Tian Sheng LIN, Hung-Chou LIN, Yi-Min CHEN, Chiu-Hua CHUNG
  • Publication number: 20220137723
    Abstract: A force sensor device includes a first structure component, an optical sensor, and a flexible structure component. The optical sensor is disposed on the first structure component. The flexible structure component has a convex portion, and the flexible structure component is assembled with the first structure component to form a chamber in which the optical sensor is disposed. The optical sensor senses light ray transmitted from the flexible structure component to at least one pixel unit to generate at least one differential image and then detects a user's control force applied for the flexible structure component according to the at least one differential image. Differential image is temporal differential image, generated from successive pixel values of a single pixel unit, or is spatial differential image, generated based on temporal differential images of at least two neighboring pixel units.
    Type: Application
    Filed: January 16, 2022
    Publication date: May 5, 2022
    Applicant: PixArt Imaging Inc.
    Inventors: Tien-Chung Yang, Yi-Cheng Chiu, Cheng-Chih Chang, Jui-Te Chiu, Yi-Chung Chen
  • Patent number: 11317042
    Abstract: An image sensor apparatus includes a pixel array having pixel units each including an image sensor cell and a processing circuit. The processing circuit includes a bias transistor, second floating diffusion node, first switch unit, signal transfer capacitor, reset transfer capacitor, second switch unit, and third switch unit. Bias transistor is coupled between first and second floating diffusion nodes and has control terminal coupled to bias voltage. First switch unit is coupled between first and second floating diffusion nodes. Second switch unit is coupled between second floating diffusion node and signal transfer capacitor. Third switch unit is coupled between second floating diffusion node and reset transfer capacitor. Signal transfer capacitor is selectively coupled to second floating diffusion node. Reset transfer capacitor is selectively coupled to second floating diffusion node.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: April 26, 2022
    Assignee: PixArt Imaging Inc.
    Inventors: Kuan Tang, Yi-Cheng Chiu, Jui-Te Chiu
  • Patent number: 11287316
    Abstract: There is provided a circuit to improve the sensing efficiency of pixels that uses the induction effect of a capacitor to duplicate a voltage deviation caused by additional electrons and uses a circuit to cancel out the voltage deviation during reading pixel data thereby improving the sensing efficiency.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: March 29, 2022
    Assignee: PIXART IMAGING INC.
    Inventors: Kuan Tang, Yi-Cheng Chiu, Chia-Chi Kuo, Jui-Te Chiu, Han-Chi Liu
  • Publication number: 20220070402
    Abstract: There is provided a pixel circuit capable of outputting time difference data or image data, and including a first temporal circuit and a second temporal circuit. The first temporal circuit is used to store detected light energy of a first interval and a second interval as the time difference data. The second temporal circuit is used to store detected light energy of the second interval as the image data. The pixel circuit is used to output a pulse width signal corresponding to the time difference data or the image data in different operating modes.
    Type: Application
    Filed: August 6, 2021
    Publication date: March 3, 2022
    Inventors: Ren-Chieh LIU, Yi-Cheng CHIU
  • Publication number: 20220070395
    Abstract: An image sensor apparatus includes a pixel array having pixel units each including an image sensor cell and a processing circuit. The processing circuit includes a bias transistor, second floating diffusion node, first switch unit, signal transfer capacitor, reset transfer capacitor, second switch unit, and third switch unit. Bias transistor is coupled between first and second floating diffusion nodes and has control terminal coupled to bias voltage. First switch unit is coupled between first and second floating diffusion nodes. Second switch unit is coupled between second floating diffusion node and signal transfer capacitor. Third switch unit is coupled between second floating diffusion node and reset transfer capacitor. Signal transfer capacitor is selectively coupled to second floating diffusion node. Reset transfer capacitor is selectively coupled to second floating diffusion node.
    Type: Application
    Filed: February 24, 2021
    Publication date: March 3, 2022
    Inventors: Kuan Tang, Yi-Cheng Chiu, Jui-Te Chiu
  • Publication number: 20220070399
    Abstract: An image sensor apparatus includes a pixel array having pixel units each including an image sensor cell and a processing circuit. The processing circuit includes a bias transistor, second floating diffusion node, first switch unit, signal transfer capacitor, reset transfer capacitor, second switch unit, and third switch unit. Bias transistor is coupled between first and second floating diffusion nodes and has control terminal coupled to bias voltage. First switch unit is coupled between first and second floating diffusion nodes. Second switch unit is coupled between second floating diffusion node and signal transfer capacitor. Third switch unit is coupled between second floating diffusion node and reset transfer capacitor. Signal transfer capacitor is selectively coupled to second floating diffusion node. Reset transfer capacitor is selectively coupled to second floating diffusion node.
    Type: Application
    Filed: August 25, 2020
    Publication date: March 3, 2022
    Inventors: Kuan Tang, Yi-Cheng Chiu, Jui-Te Chiu
  • Publication number: 20220069123
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has a source region and a drain region in a substrate, a gate structure and a metallic line. The source region surrounds the drain region in the substrate. The gate structure is disposed on the substrate, and disposed between the source region and the drain region. The gate structure surrounds the drain region. The metallic line is located above the source and drain regions and the gate structure and electrically connected to the drain region or the source region. The source region includes a doped region having a break region located between two opposite ends of the doped region. The metallic line extends from the drain region, across the gate structure and across the break region and beyond the source region.
    Type: Application
    Filed: March 4, 2021
    Publication date: March 3, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Cheng Chiu, Tien-Sheng Lin, Sheng-Fu Hsu, Chen-Yi Lee, Chiu-Hua Chung
  • Publication number: 20220070401
    Abstract: There is provided a pixel circuit capable of outputting time difference data and image data, and including an image circuit and a difference circuit. The image circuit is used to record and output detected light energy of a first interval as the image data. The difference circuit is used to record and output a variation of detected light energy between the first interval and a second interval as the time difference data. The pixel circuit selects to output at least one of the time difference data and the image data.
    Type: Application
    Filed: August 13, 2021
    Publication date: March 3, 2022
    Inventors: Ren-Chieh LIU, Yi-Cheng CHIU
  • Patent number: 11265506
    Abstract: An image sensor apparatus includes a pixel array having pixel units each including an image sensor cell and a processing circuit. The processing circuit includes a bias transistor, second floating diffusion node, first switch unit, signal transfer capacitor, reset transfer capacitor, second switch unit, and third switch unit. Bias transistor is coupled between first and second floating diffusion nodes and has control terminal coupled to bias voltage. First switch unit is coupled between first and second floating diffusion nodes. Second switch unit is coupled between second floating diffusion node and signal transfer capacitor. Third switch unit is coupled between second floating diffusion node and reset transfer capacitor. Signal transfer capacitor is selectively coupled to second floating diffusion node. Reset transfer capacitor is selectively coupled to second floating diffusion node.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: March 1, 2022
    Assignee: PixArt Imaging Inc.
    Inventors: Kuan Tang, Yi-Cheng Chiu, Jui-Te Chiu
  • Publication number: 20220058410
    Abstract: There is provided a neural signal detection circuit capable of outputting time difference data or neural data, and including a first temporal circuit and a second temporal circuit. The first temporal circuit is used to store detected voltage energy of a first interval and a second interval as the time difference data. The second temporal circuit is used to store detected voltage energy of the second interval as the neural data. The neural signal detection circuit is used to output the time difference data or the neural data in different operating modes.
    Type: Application
    Filed: November 2, 2021
    Publication date: February 24, 2022
    Inventors: SEN-HUANG HUANG, REN-CHIEH LIU, YI-HSIEN KO, HAN-CHI LIU, YI-CHENG CHIU
  • Publication number: 20220028967
    Abstract: A capacitor structure for a power semiconductor device includes a semiconductor substrate, an isolation insulating layer having a ring-shape and including an outer periphery and an inner periphery defining an opening region, a first electrode disposed on the isolation insulating layer, a dielectric layer disposed on the first electrode, and a second electrode disposed on the dielectric layer.
    Type: Application
    Filed: October 11, 2021
    Publication date: January 27, 2022
    Inventors: Hong-Yang CHEN, Tian Sheng LIN, Yi-Cheng CHIU, Hung-Chou LIN, Yi-Min CHEN, Kuo-Ming WU, Chiu-Hua CHUNG
  • Publication number: 20210404870
    Abstract: There is provided a circuit to improve the sensing efficiency of pixels that uses the induction effect of a capacitor to duplicate a voltage deviation caused by additional electrons and uses a circuit to cancel out the voltage deviation during reading pixel data thereby improving the sensing efficiency.
    Type: Application
    Filed: September 14, 2021
    Publication date: December 30, 2021
    Inventors: Kuan TANG, Yi-Cheng CHIU, Chia-Chi KUO, Jui-Te CHIU, Han-Chi LIU
  • Publication number: 20210404872
    Abstract: There is provided a circuit to improve the sensing efficiency of pixels that uses the induction effect of a capacitor to duplicate a voltage deviation caused by additional electrons and uses a circuit to cancel out the voltage deviation during reading pixel data thereby improving the sensing efficiency.
    Type: Application
    Filed: September 14, 2021
    Publication date: December 30, 2021
    Inventors: KUAN TANG, YI-CHENG CHIU, CHIA-CHI KUO, JUI-TE CHIU, HAN-CHI LIU
  • Publication number: 20210404871
    Abstract: There is provided a circuit to improve the sensing efficiency of pixels that uses the induction effect of a capacitor to duplicate a voltage deviation caused by additional electrons and uses a circuit to cancel out the voltage deviation during reading pixel data thereby improving the sensing efficiency.
    Type: Application
    Filed: September 14, 2021
    Publication date: December 30, 2021
    Inventors: KUAN TANG, YI-CHENG CHIU, CHIA-CHI KUO, JUI-TE CHIU, HAN-CHI LIU
  • Publication number: 20210399087
    Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a high voltage metal-oxide-semiconductor (HVMOS) device is integrated with a high voltage junction termination (HVJT) device. In some embodiments, a first drift well and a second drift well are in a substrate. The first and second drift wells border in a ring-shaped pattern and have a first doping type. A peripheral well is in the substrate and has a second doping type opposite the first doping type. The peripheral well surrounds and separates the first and second drift wells. A body well is in the substrate and has the second doping type. Further, the body well overlies the first drift well and is spaced from the peripheral well by the first drift well. A gate electrode overlies a junction between the first drift well and the body well.
    Type: Application
    Filed: August 31, 2021
    Publication date: December 23, 2021
    Inventors: Karthick Murukesan, Wen-Chih Chiang, Chun Lin Tsai, Ker-Hsiao Huo, Kuo-Ming Wu, Po-Chih Chen, Ru-Yi Su, Shiuan-Jeng Lin, Yi-Min Chen, Hung-Chou Lin, Yi-Cheng Chiu
  • Patent number: 11145709
    Abstract: A capacitor structure for a power semiconductor device includes a semiconductor substrate, an isolation insulating layer having a ring-shape and including an outer periphery and an inner periphery defining an opening region, a first electrode disposed on the isolation insulating layer, a dielectric layer disposed on the first electrode, and a second electrode disposed on the dielectric layer.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: October 12, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hong-Yang Chen, Tian Sheng Lin, Yi-Cheng Chiu, Hung-Chou Lin, Yi-Min Chen, Kuo-Ming Wu, Chiu-Hua Chung
  • Patent number: 11145713
    Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a high voltage metal-oxide-semiconductor (HVMOS) device is integrated with a high voltage junction termination (HVJT) device. In some embodiments, a first drift well and a second drift well are in a substrate. The first and second drift wells border in a ring-shaped pattern and have a first doping type. A peripheral well is in the substrate and has a second doping type opposite the first doping type. The peripheral well surrounds and separates the first and second drift wells. A body well is in the substrate and has the second doping type. Further, the body well overlies the first drift well and is spaced from the peripheral well by the first drift well. A gate electrode overlies a junction between the first drift well and the body well.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: October 12, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Karthick Murukesan, Wen-Chih Chiang, Chun Lin Tsai, Ker-Hsiao Huo, Kuo-Ming Wu, Po-Chih Chen, Ru-Yi Su, Shiuan-Jeng Lin, Yi-Min Chen, Hung-Chou Lin, Yi-Cheng Chiu
  • Publication number: 20210159334
    Abstract: A high-voltage semiconductor device structure is provided. The high-voltage semiconductor device structure includes a semiconductor substrate, a source ring in the semiconductor substrate, and a drain region in the semiconductor substrate. The high-voltage semiconductor device structure also includes a doped ring surrounding sides and a bottom of the source ring and a well region surrounding sides and bottoms of the drain region and the doped ring. The well region has a conductivity type opposite to that of the doped ring. The high-voltage semiconductor device structure further includes a conductor electrically connected to the drain region and extending over and across a periphery of the well region. In addition, the high-voltage semiconductor device structure includes a shielding element ring between the conductor and the semiconductor substrate. The shielding element ring extends over and across the periphery of the well region.
    Type: Application
    Filed: January 6, 2021
    Publication date: May 27, 2021
    Inventors: Hung-Chou Lin, Yi-Cheng Chiu, Karthick Murukesan, Yi-Min Chen, Shiuan-Jeng Lin, Wen-Chih Chiang, Chen-Chien Chang, Chih-Yuan Chan, Kuo-Ming Wu, Chun Lin Tsai