Patents by Inventor Yi Feng
Yi Feng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240153950Abstract: A semiconductor device includes a first to sixth regions, a first gate, a first metal contact and a second metal contact. The second region is disposed opposite to the first region with respect to the first gate. The first metal contact couples the first region to the second region. The fourth region is disposed opposite to the third region with respect to the first gate. The second metal contact is coupling the third region to the fourth region. The fifth region is disposed between the first gate and the second region, and is disconnected from the first metal contact and the second metal contact. The sixth region is disposed between the first gate and the first region, and is disconnected from the first metal contact and the second metal contact.Type: ApplicationFiled: January 16, 2024Publication date: May 9, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Feng CHANG, Po-Lin PENG, Jam-Wem LEE
-
Publication number: 20240154015Abstract: A method includes forming a first fin and a second fin protruding from a frontside of a substrate, forming a gate stack over the first and second fins, forming a dielectric feature dividing the gate stack into a first segment engaging the first fin and a second segment engaging the second fin, and growing a first epitaxial feature on the first fin and a second epitaxial feature on the second fin. The dielectric feature is disposed between the first and second epitaxial features. The method also includes performing an etching process on a backside of the substrate to form a backside trench, and forming a backside via in the backside trench. The backside trench exposes the dielectric feature and the first and second epitaxial features. The backside via straddles the dielectric feature and is in electrical connection with the first and second epitaxial features.Type: ApplicationFiled: March 22, 2023Publication date: May 9, 2024Inventors: Jui-Lin CHEN, Hsin-Wen SU, Chih-Ching WANG, Chen-Ming LEE, Chung-I YANG, Yi-Feng TING, Jon-Hsu HO, Lien-Jung HUNG, Ping-Wei WANG
-
Patent number: 11977762Abstract: A Logical Unit Number (LUN) division method and device includes checking and adjusting a connection manner and numbers of Serial Attached Small Computer System Interface (SCSI) (SAS) connections of storage enclosures and a controller, so as to make a maximum output bandwidth of each storage enclosure consistent (Si); querying controller port identifiers and storage enclosure identifiers (S2); creating a Mdisk array, and adding the corresponding controller port identifier and the corresponding storage enclosure identifier for each Mdisk (S3); logically dividing a storage space in the Mdisk array to create a volume, and dividing the volume into LUNs, whereby Mdisks that form the LUNs are made to come from different storage enclosures and different controller ports (S4); and mapping the LUNs to a host (S5).Type: GrantFiled: January 7, 2021Date of Patent: May 7, 2024Assignee: INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD.Inventor: Yi Feng
-
Publication number: 20240146685Abstract: System and techniques for capability discovery in an information centric network (ICN) are described herein. An ICN node receives a discovery packet that includes a discovery type corresponding to an indication of a node capability requested by a source node of the discovery packet. First capability data, from an intermediate node, is extracted from the discovery packet. The first capability data is stored locally by ICN node. Second capability data from the ICN node is added to the discovery packet to create an expanded discovery packet. The expanded discovery packet is then communicated by the ICN node.Type: ApplicationFiled: December 23, 2021Publication date: May 2, 2024Inventors: Yi Zhang, Srikathyayani Srikanteswara, Hao Feng, Nageen Himayat, Gabriel Arrobo
-
Patent number: 11972951Abstract: The present disclosure relates to a method for fabricating a semiconductor structure. The method includes providing a substrate with a gate structure, an insulating structure over the gate structure, and a S/D region; depositing a titanium silicide layer over the S/D region with a first chemical vapor deposition (CVD) process. The first CVD process includes a first hydrogen gas flow. The method also includes depositing a titanium nitride layer over the insulating structure with a second CVD process. The second CVD process includes a second hydrogen gas flow. The first and second CVD processes are performed in a single reaction chamber and a flow rate of the first hydrogen gas flow is higher than a flow rate of the second hydrogen gas flow.Type: GrantFiled: April 4, 2022Date of Patent: April 30, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Wei Chang, Kao-Feng Lin, Min-Hsiu Hung, Yi-Hsiang Chao, Huang-Yi Huang, Yu-Ting Lin
-
Patent number: 11966677Abstract: A method is disclosed. The method includes computing a time delay for each path of a plurality of paths of a circuit design and determining a commonality score based on a number of segments that are common between the plurality of paths of the circuit design. The method further includes determining a criticality score based on the time delay for each path of the plurality of paths of the circuit design. The method further includes generating a graphical representation of the plurality of paths, wherein a first dimension of the graphical representation corresponds to the commonality score and wherein a second dimension of the graphical representation corresponds to the criticality score. The method further includes providing the graphical representation of the plurality of paths in a graphical user interface (GUI) to represent the plurality of paths in the circuit design.Type: GrantFiled: August 31, 2021Date of Patent: April 23, 2024Assignee: SYNOPSYS, INC.Inventors: Melvyn Goveas, Ribhu Mittal, Wen-Chi Feng, Yanhua Yi
-
Patent number: 11966352Abstract: An information handling system with modular riser components for receiving expansion cards having various requirements. The system includes a riser body assembly having a common support structure for receiving expansion cards. The common support structure may be coupled to different expansion structures to provide support of expansion cards having requirements that would not be met by the common support structure alone.Type: GrantFiled: October 8, 2020Date of Patent: April 23, 2024Assignee: Dell Products L.P.Inventors: Yu-Feng Lin, Hao-Cheng Ku, Yi-Wei Lu
-
Patent number: 11963868Abstract: A double-sided aspheric diffractive multifocal lens and methods of manufacturing and design of such lenses in the field of ophthalmology. The lens can include an optic comprising an aspheric anterior surface and an aspheric posterior surface. On one of the two surfaces a plurality of concentric diffractive multifocal zones can be designed. The other surface can include a toric component. The double-sided aspheric surface design results in improvement of the modulation transfer function (MTF) of the lens-eye combination by aberration reduction and vision contrast enhancement as compared to one-sided aspheric lens. The surface having a plurality of concentric diffractive multifocal zones produces a near focus, an intermediate focus, and a distance focus.Type: GrantFiled: May 27, 2021Date of Patent: April 23, 2024Assignee: AST Products, Inc.Inventors: Yi-Feng Chiu, Chuan-Hui Yang, Wen-Chu Tseng
-
Publication number: 20240122547Abstract: A human-body-signal collection device (10). The human-body-signal collection device (10) includes a reference electrode (210), a first electrode (220) and a second electrode (230), an adjusting and generating device (30), a first collection device (40), and a first feedback device (50). The first electrode (220) outputs the first signal. The second electrode (230) outputs the second signal. The adjusting and generating device (30) is connected to the reference electrode (210) to output a reference signal to the reference electrode (210). The first collection device (40) collects the first signal and the second signal, and generates a first potential-difference signal based on the first signal and the second signal. The first feedback device (50) is connected to the first collection device (40) and the adjusting and generating device respectively.Type: ApplicationFiled: August 30, 2021Publication date: April 18, 2024Inventors: ZHUO-BIAO HE, JUN TIAN, YI-FENG CHEN, DUN ALEX LI
-
Publication number: 20240126314Abstract: A low dropout regulator includes output terminal circuit and amplifier. The output terminal circuit is configured to generate output voltage according to input voltage and is configured to generate feedback voltage according to the output voltage. The amplifier is configured to generate control voltage to the output terminal circuit according to reference voltage and the feedback voltage, so as to adjust the output voltage, wherein the amplifier includes input stage circuit, current mirror circuit and filter circuit. The input stage circuit is configured to receive the reference voltage and the feedback voltage to generate a differential output. The filter circuit is configured to filter the input voltage to generate dependent current related to noise of the input voltage on the current mirror circuit, wherein the current mirror circuit is configured to output the control voltage according to the differential output and the dependent current.Type: ApplicationFiled: March 9, 2023Publication date: April 18, 2024Inventors: Yi FENG, Hsueh-Yu KAO
-
Publication number: 20240124827Abstract: The present invention provides a device for enrichment culture and gravity-type isolation of marine microorganisms in a high-pressure environment. The device includes an enrichment and multistage purification unit and a gravity-type isolation and culture unit. Under a high-pressure and low-temperature environment constructed to be consistent with a marine environment, the enrichment and multistage purification unit is used for realizing a process of enrichment and multistage purification of the marine microorganisms, obtaining a marine microorganism enrichment bacteria liquid and injecting the marine microorganism enrichment bacteria liquid into the gravity-type isolation and culture unit. The gravity-type isolation and culture unit is used for carrying out automatic streaking by means of gravity in the high-pressure environment to achieve solid isolation and culture of the marine microorganisms, such that culturability of the marine microorganisms is effectively improved.Type: ApplicationFiled: March 30, 2022Publication date: April 18, 2024Applicants: GUANGDONG LABORATORY OF SOUTHERN OCEAN SCIENCE AND ENGINEERING (GUANGZHOU), GUANGDONG UNIVERSITY OF TECHNOLOGYInventors: Jingchun FENG, Si ZHANG, Zhifeng YANG, Yi WANG, Yanpeng CAI, Song ZHONG
-
Patent number: 11961546Abstract: A reference circuit for generating a reference current includes a plurality of resistive elements including at least one magnetic tunnel junction (MTJ). A control circuit is coupled to a first terminal of the at least one MTJ and is configured to selectively flow current through the at least one MTJ in the forward and inverse direction to generate a reference current.Type: GrantFiled: August 2, 2021Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Fu Lee, Hon-Jarn Lin, Po-Hao Lee, Ku-Feng Lin, Yi-Chun Shih, Yu-Der Chih
-
Patent number: 11961609Abstract: The disclosure provides a three-dimensional (3D) image classification method and apparatus, a device, and a storage medium. The method includes: obtaining a 3D image, the 3D image including first-dimensional image information, second-dimensional image information, and third-dimensional image information; extracting a first image feature corresponding to planar image information from the 3D image; extracting a second image feature corresponding to the third-dimensional image information from the 3D image; fusing the first image feature and the second image feature, to obtain a fused image feature corresponding to the 3D image; and determining a classification result corresponding to the 3D image according to the fused image feature corresponding to the 3D image.Type: GrantFiled: July 23, 2021Date of Patent: April 16, 2024Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITEDInventors: Yi Fan Hu, Ye Feng Zheng
-
Publication number: 20240120316Abstract: The present disclosure relates to a semiconductor package, a semiconductor bonding structure and a method of fabricating the same. The semiconductor package includes a first chip, a second chip and a conductive structure, wherein the conductive structure is disposed at a side of the second chip and over a second upper surface of the first interconnection structure to electrically connect to the first interconnection structure. The semiconductor bonding structure includes a first substrate, a plurality of first interconnection structures, a plurality of chips and a plurality of conductive structures, wherein the conductive structures are respectively disposed at a side of each of the chips and over a second upper surface of each first interconnection structure, to electrically connect to each first interconnection.Type: ApplicationFiled: November 17, 2022Publication date: April 11, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Kai-Kuang Ho, Yu-Jie Lin, Yi-Feng Hsu
-
Publication number: 20240120306Abstract: A semiconductor package includes a die stack including a first semiconductor die having a first interconnect structure, and a second semiconductor die having a second interconnect structure direct bonding to the first interconnect structure of the first semiconductor die. The second interconnect structure includes connecting pads disposed in a peripheral region around the first semiconductor die. First connecting elements are disposed on the connecting pads, respectively. A substrate includes second connecting elements on a mounting surface of the substrate. The first connecting elements are electrically connected to the second connecting elements through an anisotropic conductive structure.Type: ApplicationFiled: November 4, 2022Publication date: April 11, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Kai-Kuang Ho, Yu-Jie Lin, Yi-Feng Hsu
-
Patent number: 11955460Abstract: In accordance with some embodiments, a package-on-package (PoP) structure includes a first semiconductor package having a first side and a second side opposing the first side, a second semiconductor package having a first side and a second side opposing the first side, and a plurality of inter-package connector coupled between the first side of the first semiconductor package and the first side of the second semiconductor package. The PoP structure further includes a first molding material on the second side of the first semiconductor package. The second side of the second semiconductor package is substantially free of the first molding material.Type: GrantFiled: October 5, 2020Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Da Tsai, Meng-Tse Chen, Sheng-Feng Weng, Sheng-Hsiang Chiu, Wei-Hung Lin, Ming-Da Cheng, Ching-Hua Hsieh, Chung-Shi Liu
-
Patent number: 11953114Abstract: An air valve with a SMA wire for switching is located in an air chamber in which at least two air holes are formed. The air valve comprises a base, an air piston, a driving component, and the SMA wire. The base is provided with two supporting blocks, and two conduction components near one of the two supporting blocks. The air piston determines a ventilation state of one of the two air holes. The air piston comprises a rod body on the two supporting blocks and with a first triggering part, and a spring sleeved on the rod body. The driving component is sleeved on the rod body and with a second triggering part matched with the first triggering part. The SMA wire is connected with the two conduction components and the driving component, and is turned by the supporting block opposite to the two conduction components.Type: GrantFiled: August 1, 2022Date of Patent: April 9, 2024Assignee: TANGTRING SEATING TECHNOLOGY INC.Inventors: Jian Zeng, Jun Xie, Qing-Yi Feng
-
Patent number: 11953774Abstract: A display substrate includes: a base substrate (100); a plurality of sub-pixels (R, G, B) located on the base substrate (100), every two rows of sub-pixels (R, G, B) constituting a pixel group; a plurality of first gate lines (Gate1) located at first row gaps between the pixel groups, two first gate lines (Gate1) being arranged at each first row gap; and a plurality of photosensors (101), the orthographic projection of each row of photosensors (101) on the base substrate (100) completely covering a second row gap in the pixel group and partially overlapping with the orthographic projections of the sub-pixels (R, G, B), thereby avoiding the bright and dark difference between adjacent rows and ensuring the aperture ratio.Type: GrantFiled: June 8, 2021Date of Patent: April 9, 2024Assignees: Beijing BOE Display Technology Co., Ltd., BOE Technology Group Co., Ltd.Inventors: Xinlan Yang, Wenkai Mu, Yi Liu, Jun Fan, Bo Feng, Yang Wang, Zhan Wei, Tengfei Ding, Shijun Wang, Chengfu Xu
-
Publication number: 20240113032Abstract: Interconnect structure packages (e.g., through silicon vias (TSV) packages, through interlayer via (TIV) packages) may be pre-manufactured as opposed to forming TIVs directly on a carrier substrate during a manufacturing process for a semiconductor die package at backend packaging facility. The interconnect structure packages may be placed onto a carrier substrate during manufacturing of a semiconductor device package, and a semiconductor die package may be placed on the carrier substrate adjacent to the interconnect structure packages. A molding compound layer may be formed around and in between the interconnect structure packages and the semiconductor die package.Type: ApplicationFiled: April 25, 2023Publication date: April 4, 2024Inventors: Kai-Fung CHANG, Chin-Wei LIANG, Sheng-Feng WENG, Ming-Yu YEN, Cheyu LIU, Hung-Chih CHEN, Yi-Yang LEI, Ching-Hua HSIEH
-
Patent number: D1025064Type: GrantFiled: July 21, 2021Date of Patent: April 30, 2024Assignee: Logitech Europe S.A.Inventors: Yi-Hsuan Lin, Blaithin Crampton, Marcel Twohig, Anish Shakthi Ovia Selvan, Anatoliy Polyanker, Jingyan Ma, Ming Feng Hsieh, Olivia Hildebrand