Abstract: A vinyl-containing copolymer is copolymerized from (a) first compound, (b) second compound, and (c) third compound. (a) First compound is an aromatic compound having a single vinyl group. (b) Second compound is polybutadiene or polybutadiene-styrene having side vinyl groups. (c) Third compound is an acrylate compound. The vinyl-containing copolymer includes 0.003 mol/g to 0.010 mol/g of benzene ring, 0.0005 mol/g to 0.008 mol/g of vinyl group, and 1.2*10?5 mol/g to 2.4*10?4 mol/g of ester group.

Abstract: Germanium-based sensors are disclosed herein. An exemplary germanium-based sensor includes a germanium photodiode and a junction field effect transistor (JFET) formed from a germanium layer disposed on and/or in a silicon substrate. A doped silicon layer, which can be formed by in-situ doping epitaxially grown silicon, is disposed between the germanium layer and the silicon substrate. In embodiments where the germanium layer is on the silicon substrate, the doped silicon layer is disposed between the germanium layer and an oxide layer. The JFET has a doped polysilicon gate, and in some embodiments, a gate diffusion region is disposed in the germanium layer under the doped polysilicon gate. In some embodiments, a pinned photodiode passivation layer is disposed in the germanium layer. In some embodiments, a pair of doped regions in the germanium layer is configured as an e-lens of the germanium-based sensor.

Abstract: A method for detecting an interior condition of a vehicle is provided to use a camera device and a radar device to acquire images and point cloud datasets with respect to an interior space of the vehicle. A computing device generates a synthesized image based on the images and the point cloud datasets, obtains a skeleton feature dataset and a facial feature dataset with respect to a living object in the synthesized image, and determines the interior condition of the vehicle based on the skeleton feature dataset and the facial feature dataset.

Abstract: Methods, systems, and devices for wireless communications are described. A network entity may transmit a set of spatially multiplexed synchronization signals in a same symbol period. The set of spatially multiplexed synchronization signals may indicate a parameter, such as a cell identifier, for the network entity. The network entity may select a sequence for each synchronization signal of the set. A user equipment (UE) may monitor for the set of spatially multiplexed synchronization signals during the same symbol period. The UE may differentiate each synchronization signal based on a respective sequence used to transmit each synchronization signal. The UE may determine that the set of spatially multiplexed synchronization signals were transmitted by the network entity using multiple antenna ports. The UE may determine the parameter for the network entity based on receiving the set of spatially multiplexed synchronization signals.

Abstract: An electronic device may have a phased antenna array. An antenna in the array may include a rectangular patch element with diagonal axes. The antenna may have first and second antenna feeds coupled to the patch element along the diagonal axes. The antenna may be rotated at a forty-five degree angle relative to other antennas in the array. The antenna may have one or two layers of parasitic elements overlapping the patch element. For example, the antenna may have a layer of coplanar parasitic patches separated by a gap. The antenna may also have an additional parasitic patch that is located farther from the patch element than the layer of coplanar parasitic patches. The additional parasitic patch may overlap the patch element and the gap in the coplanar parasitic patches. The antenna may exhibit a relatively small footprint and minimal mutual coupling with other antennas in the array.

Abstract: A display substrate, a manufacturing method thereof, and a display device are provided. A pixel region is provided with a light emission function layer on a base substrate of the display substrate, and a separation region is provided with at least one first barrier structure. The first barrier structure includes a stopper pattern and a first separation component. A side surface of the first separation component has a recess, and a portion of the light emission function layer extending to the separation region is disconnected on the side of the first separation component. The separation region is provided with an inorganic layer structure on the base substrate. The inorganic layer structure includes multiple stacked inorganic film layers, the stopper pattern is located between two adjacent inorganic film layers and the first separation component is located on a side of the inorganic layer structure away from the base substrate.

Abstract: A method for manufacturing a package structure includes providing a carrier board; providing at least one die having a top surface, a bottom surface, and a side surface on the carrier board; and forming a protective layer to cover at least a portion of the side surface of the die. The die includes a substrate, a semiconductor layer, a gate structure, a source structure and a drain structure, at least one dielectric layer, and at least one pad. The semiconductor layer is disposed on the substrate. The gate structure is disposed on the semiconductor layer. The source and the drain structures are disposed on opposite sides of the gate structure. The dielectric layer covers the gate, source, and drain structures. The pad is disposed on the dielectric layer and penetrates through the dielectric layer to electrically contact with the gate, source or drain structure.

Abstract: A targeted seed implanting robot suitable for clinical treatment of a human patient in the lithotomy position includes a rack, and further includes a position and posture adjusting mechanism, a contact force feedback friction wheel type targeted seed implanting mechanism, and a sine elastic amplification moment compensation mechanism; and the specific use steps are as follows: S1, driving; S2, meshing; S3, swing; S4, transverse movement; S5, compensation moment; S6, linear motion; S7, rotary motion; S8, detection; and S9, transmission of information.

Abstract: An electronic device, including a first substrate, a partition wall structure, a pressurizing component, a second substrate, a shell, and multiple first conductive parts, is provided. The first substrate has a through hole, and a first surface and a second surface that are opposite to each other. The partition wall structure is disposed on the first surface and surrounds to form a first chamber. The pressurizing component is disposed on the partition wall structure and covers the first chamber. The pressurizing component includes at least a mass and a vibration membrane. The shell is disposed on the second substrate and jointly forms a second chamber with the second substrate. The first chamber is formed in the second chamber. The multiple first conductive parts are disposed between the first substrate and the second substrate. There is a gap between any two adjacent first conductive parts.

Abstract: Method and apparatus for deriving a motion vector at a video decoder. A block-based motion vector may be produced at the video decoder by utilizing motion estimation among available pixels relative to blocks in one or more reference frames. The available pixels could be, for example, spatially neighboring blocks in the sequential scan coding order of a current frame, blocks in a previously decoded frame, or blocks in a downsampled frame in a lower pyramid when layered coding has been used.

Abstract: An electronic device may be provided with a phased antenna array on an antenna module. The array may include low band antennas and high band antennas that radiate at frequencies greater than 10 GHz. The module may include antenna layers, transmission line layers, and ground traces that separate the antenna layers from the transmission line layers. The low band antennas and the high band antennas may have radiators patterned onto the antenna layers. The radiators may be fed by transmission lines on the transmission line layers. The antenna layers may have a dielectric permittivity that is greater than the dielectric permittivity of the transmission line layers. This may serve to reduce the lateral footprint of the low band and high band antennas, which allows the antennas to be interleaved along a common linear axis in the phased antenna array, thereby minimizing the lateral footprint of the antenna module.

Abstract: A display panel, comprising a first insulating structural layer, a first crack detection line, a second insulating structural layer and a second crack detection line which are sequentially arranged on a substrate, wherein the first crack detection line and the second crack detection line are both located in a peripheral area and are arranged around a display area, one end of the first crack detection line is configured to receive a detection signal, and the other end of the first crack detection line is configured to output a first output signal, and one end of the second crack detection line is configured to receive a detection signal and the other end of the second crack detection line is configured to output a second output signal.

Abstract: A mechanical arm calibration system and a mechanical arm calibration method are provided. The method includes: locating a position of an end point of a mechanical arm in a three-dimensional space to calculate an actual motion trajectory of the end point when the mechanical arm is operating; retrieving link parameters of the mechanical arm, randomly generating sets of particles including compensation amounts for the link parameters through particle swarm optimization (PSO), importing the compensation amounts of each of the sets of particles into forward kinematics after addition of the corresponding link parameters, to calculate an adaptive motion trajectory of the end point; calculating position errors between the adaptive motion trajectory and the actual motion trajectory of each of the sets of particles for a fitness value of the PSO to estimate a group best position; and updating the link parameters by the compensation amounts corresponding to the group best position.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having a first semiconductor material. A second semiconductor material is disposed on the first semiconductor material. The second semiconductor material is a group IV semiconductor or a group III-V compound semiconductor. A passivation layer is disposed on the second semiconductor material. The passivation layer includes the first semiconductor material. A first doped region and a second doped region extend through the passivation layer and into the second semiconductor material.

Abstract: An electrochemical device is disclosed. The electrochemical device includes a first transparent conductive layer, an electrochromic layer overlying the first transparent conductive layer, a counter electrode layer overlying the electrochromic layer, a second transparent conductive layer, and a switching speed parameter of not greater than 0.68 s/mm at 23° C.

Abstract: The present disclosure provides a semiconductor structure, including a substrate including a first material, wherein the first material generates electrical signals from radiation within a first range of wavelengths, an image sensor element including a second material, wherein the second material generates electrical signals from radiation within a second range of wavelengths, the second range is different from first range, a transparent layer proximal to a light receiving surface of the image sensor element, wherein the transparent layer is transparent to radiation within the second range of wavelength, and an interconnect structure connected to a signal transmitting surface of the image sensor element.

Abstract: A method for manufacturing a semiconductor structure includes providing a substrate; forming mutually parallel first trenches extending along a first direction in the substrate and first isolation structures filling the first trenches; forming mutually parallel second trenches extending along a second direction in the substrate and in the first isolation structures, the first and second trenches dividing the substrate to form active pillars, and a depth of the second trenches being less than that of the first trenches; forming second isolation structures alternately arranged with the first isolation structures along the second direction at bottoms of the second trenches, top surfaces of the second isolation structures being lower than bottom surfaces of the second trenches located in the first isolation structures; forming bit line structures on the second isolation structures; and forming word line structures above the bit line structures.

Abstract: An electronic device may have a phased antenna array. An antenna in the array may include a rectangular patch element with diagonal axes. The antenna may have first and second antenna feeds coupled to the patch element along the diagonal axes. The antenna may be rotated at a forty-five degree angle relative to other antennas in the array. The antenna may have one or two layers of parasitic elements overlapping the patch element. For example, the antenna may have a layer of coplanar parasitic patches separated by a gap. The antenna may also have an additional parasitic patch that is located farther from the patch element than the layer of coplanar parasitic patches. The additional parasitic patch may overlap the patch element and the gap in the coplanar parasitic patches. The antenna may exhibit a relatively small footprint and minimal mutual coupling with other antennas in the array.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The method of manufacturing a semiconductor structure includes: providing a base including a first region and a second region, where a plurality of active pillars are arranged at intervals in the base located in the first region; forming a first dielectric layer on the base, where the first dielectric layer covers the plurality of active pillars; forming a first mask layer with a first mask pattern on the first dielectric layer; forming a second mask layer with a second mask pattern on the first mask layer; forming a third mask layer with a third mask opening, where the third mask opening is used to expose the first region; and removing part of the first dielectric layer by using the first mask layer, the second mask layer, and the third mask layer as a mask.

Abstract: Embodiments herein relate generally to the field of footwear, and more particularly to components of performance footwear, such as midsoles, and in particular related to a high performance composite foam for a midsole, the composite foam comprising: a pelletized expanded thermoplastic elastomer; and a polyurethane (PU) matrix, wherein the pelletized expanded thermoplastic elastomer is mixed within the PU matrix. Midsoles made from a high performance composite foam and footwear including such midsoles. A method of making a high performance midsole is also provided.