Abstract: Provided is a low-molecular-weight holothurian glycosarninoglycan, with the constituent units thereof being a glucuronic acid group, an N-acetaminogalactose group and a fucose group, and a sulfate ester group or acetyl ester group thereof. Glucuronic acid and N-acetaminogalactose are interconnected via ?(1-3) and ?(1-4) glucosidic bonds to form a backbone of a disaccharide repeating structural unit, and a fucose group is connected to the backbone as a side chain. On a molar ratio basis, the ratio of the glucuronic acid group:the N-acetaminogalactose group:the fucose group is 1:(0.8-1.2):(0.6-1.2). In the structure of the low-molecular-weight holothurian glycosaminoglycan, 10-30% of glucuronic acid groups are modified, on the 2-position, with a sulfate ester group, and the rest are hydroxyl groups; and a proportion of 10-30% of fucose groups is modified, on the 2-position, with an acetyl ester group, and the rest are hydroxyl or sulfate ester groups.

Abstract: Embodiments of the present disclosure provide a method, device and computer program product for backing up data. The method comprises obtaining a data attribute of specific data to be backed up from a client to a server, a resource utilization rate at the client, and a network condition between the client and the server. The method further comprises setting, based on the data attribute, the resource utilization rate and the network condition, a plurality of parameters for performing stream backup, wherein the plurality of parameters at least comprises a concurrent number of stream transmission and a concurrent number of data parsing. The method further comprises parsing, according to the set plurality of parameters, the specific data and backing up the specific data from the client to the server.

Abstract: According to various embodiments, there is provided a memory cell. The memory cell may include a transistor, a dielectric member, an electrode and a contact member. The dielectric member may be disposed over the transistor. The electrode may be disposed over the dielectric member. The contact member has a first end and a second end opposite to the first end. The first end is disposed towards the transistor, and the second end is disposed towards the dielectric member. The contact member has a side surface extending from the first end to the second end. The second end may have a recessed end surface that has a section that slopes towards the side surface so as to form a tip with the side surface at the second end. The dielectric member may be disposed over the second end of the contact member and may include at least a portion disposed over the tip.

Abstract: Embodiments of the present disclosure relate to a method for data backup. The method includes obtaining an attribute value associated with a backup task to be run, the backup task being used for backing up data on a client terminal to a server through a network, the attribute value including a value of at least one of an attribute of the client terminal, an attribute of the server, and an attribute of the network; determining, based on the attribute value, the number of threads to be used to perform the backup task on the client terminal; and causing the client terminal to perform the backup task using the number of threads to back up the data.

Abstract: Germanium-based sensors are disclosed herein. An exemplary germanium-based sensor includes a germanium photodiode and a junction field effect transistor (JFET) formed from a germanium layer disposed in a silicon substrate, in some embodiments, or on a silicon substrate, in some embodiments. A doped silicon layer, which can be formed by in-situ doping epitaxially grown silicon, is disposed between the germanium layer and the silicon substrate. In embodiments where the germanium layer is on the silicon substrate, the doped silicon layer is disposed between the germanium layer and an oxide layer. The JFET has a doped polysilicon gate, and in some embodiments, a gate diffusion region is disposed in the germanium layer under the doped polysilicon gate. In some embodiments, a pinned photodiode passivation layer is disposed in the germanium layer. In some embodiments, a pair of doped regions in the germanium layer is configured as an e-lens of the germanium-based sensor.

Abstract: A semiconductor image sensor includes a first substrate including a first front side and a first back side, a second substrate including a second front side and a second back side, a third substrate including a third front side and a third back side, a first interconnect structure, and a second interconnect structure. The first substrate includes a layer and a first light-sensing element in the layer. The layer includes a first semiconductor material, and the first light-sensing element includes a second semiconductor material. The second substrate is bonded to the first substrate with the second front side facing the first back side. The third substrate is bonded to the first substrate with the third front side facing the first front side. The first interconnect structure and the second interconnect structure are disposed between the first front side and the third front side.

Abstract: The present disclosure relates to noninvasive methods for detecting liver fibrosis. Disclosed herein are noninvasive liver fibrosis detection methods that use Doppler Ultrasound devices and a physics-based machine learning method. Further disclosed herein are methods for detecting liver fibrosis in a subject by detecting and measuring the presence of a shift in the frequency of blood flow in the hepatic vein as compared to the frequency of blood flow in the portal vein.

Abstract: Systems and methods for fused multi-modal electron microscopy are provided to generate quantitatively accurate 2D maps or 3D volumes with pixel/voxel values that directly reflect a sample's chemistry. Techniques are provided for combining annular dark field detector (ADF), annular bright field (ABF) and/or pixelated detector image data and energy dispersive X-rays (EDX) data and/or electron energy loss spectroscopy (EELS) data for a sample and generating chemical 2D and 3D maps by applying minimization optimization process.

Abstract: Disclosed are a Piper laetispicum extract and a preparation method therefor and a use thereof. The Piper laetispicum extract includes any one or more of sesamin, (2E,6E)-N-isobutyl-7-(3,4-methylenedioxyphenyl)heptadienamide, (2E,4E)-N-isobutyldodecane-2,4-dieneamide, (2E,4E)-N-isobutyl-15-phenylpentadeca-2,4-dieneamide, (2E,4E,14Z)—N-isobutyleicosane-2,4,14-trienamide, and (2E,4E)-N-isobutyl-13-phenyltrideca-2,4-dieneamide. The Piper laetispicum extract can prevent depression.

Abstract: A semiconductor structure and a method for manufacturing a semiconductor structure are provided. The method for manufacturing the semiconductor structure includes: a substrate is provided: a plurality of semiconductor channels arrayed in a first direction and a second direction are formed on the substrate: a plurality of bit lines extending in the first direction are formed, in which the bit lines is located in the substrate: and a plurality of word lines extending in the second direction are formed, in which two word lines adjacent to each other in the first direction are spaced apart from each other in a direction perpendicular to a surface of the substrate: and a sidewall conductive layer is formed, in which the sidewall conductive layer is located above one of the two word lines adjacent to each other, and is arranged in the same layer as the other of the two word lines.

Abstract: A semiconductor structure includes a plurality memory group provided in rows, each of the memory groups includes a plurality of memories arranged at intervals along a row direction, and for two adjacent ones of the memory groups, the memories in one memory group and the memories in another memory group are staggered.

Abstract: A test structure includes a plurality of word lines and a plurality of bit lines. A vertical gate-all-around (VGAA) transistor is formed at the intersection of each word line and each bit line. The test structure includes a first area and a second area. The second area is arranged outside the first area, the word lines in the first area and the word lines in the second area are disconnected, and the bit lines in the first area and the bit lines in the second area are disconnected. The plurality of VGAA transistors located in the first area form a test array, and a VGAA transistor located in the middle of the test array is a device to be tested.

Abstract: A voice information processing method and an electronic device are provided. The voice information processing method may include: a first device (1100) obtains first voice information, and when the first voice information includes a wakeup keyword, the first device (1100) sends a voice assistant wakeup instruction to a second device (1200), such that the second device (1200) launches a voice assistant; then the first device (1100) obtains second voice information and sends the second voice information to the second device (1200), the second device (1200) determines a voice triggered event corresponding to the second voice information by using the voice assistant, and feeds target information associated with performance of the voice triggered event back to the first device (1100), such that the first device (1100) performs the voice triggered event based on the target information. The method can reduce the computing burden of the first device (1100).

Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes: a substrate, multiple active pillars located in the substrate, and multiple word lines. The multiple active pillars are arranged in an array in a first direction and a second direction. The first direction and the second direction are both directions parallel to a top surface of the substrate, and the first direction and the second direction intersect. The multiple word lines are spaced apart in the first direction. Each of the word lines extends in the second direction and continuously surrounds and covers a portion of a side wall of each of the multiple active pillars arranged in the second direction. Any two adjacent word lines are at least partially staggered in a direction perpendicular to the top surface of the substrate.

Abstract: According to various embodiments, there is provided a memory cell. The memory cell may include a transistor, a dielectric member, an electrode and a contact member. The dielectric member may be disposed over the transistor. The electrode may be disposed over the dielectric member. The contact member has a first end and a second end opposite to the first end. The first end is disposed towards the transistor, and the second end is disposed towards the dielectric member. The contact member has a side surface extending from the first end to the second end. The second end may have a recessed end surface that has a section that slopes towards the side surface so as to form a tip with the side surface at the second end. The dielectric member may be disposed over the second end of the contact member and may include at least a portion disposed over the tip.

Abstract: Technologies are disclosed for improving the efficiency of real-time audio processing, and specifically for improving the efficiency of continuously modifying a real-time audio signal. Efficiency is improved by reducing memory bandwidth requirements and by reducing the amount of processing used to modify the real-time audio signal. In some configurations, memory bandwidth requirements are reduced by selectively transferring active samples in the frequency domain—e.g. avoiding the transfer samples with amplitudes of zero or near-zero. This has particular importance when the specialized hardware retrieves samples from main memory in real-time. In some configurations, the amount of processing needed to modify the audio signal is reduced by omitting operations that do not meaningfully affect the output audio signal. For example, a multiplication of samples may be avoided when at least one of the samples has an amplitude of zero or near-zero.

Abstract: An electronic device may have an antenna embedded in a substrate. The substrate may have first layers, second layers on the first layers, and third layers on the second layers. The antenna may include a first patch on the first layers that radiates in a first band, a second patch on the second antenna layers that radiates in a second band, and a parasitic patch on the third layers. A short path may couple ground to a location on the first patch that allows the first patch to form a ground extension in the second band for the second patch without affecting performance of the first patch in the first band. The first layers may have a higher dielectric permittivity than the second and third layers to minimize the thickness of the substrate without requiring a separate dielectric loading layer over the substrate.

Abstract: An electronic device may be provided with a phased antenna array on an antenna module. The array may include low band antennas and high band antennas that radiate at frequencies greater than 10 GHz. The module may include antenna layers, transmission line layers, and ground traces that separate the antenna layers from the transmission line layers. The low band antennas and the high band antennas may have radiators patterned onto the antenna layers. The radiators may be fed by transmission lines on the transmission line layers. The antenna layers may have a dielectric permittivity that is greater than the dielectric permittivity of the transmission line layers. This may serve to reduce the lateral footprint of the low band and high band antennas, which allows the antennas to be interleaved along a common linear axis in the phased antenna array, thereby minimizing the lateral footprint of the antenna module.

Abstract: An electronic device may have a cover layer and an antenna. A dielectric adapter may have a first surface coupled to the antenna and a second surface pressed against the cover layer. The cover layer may have a three-dimensional curvature. The second surface may have a curvature that matches the curvature of the cover layer. Biasing structures may exert a biasing force that presses the antenna against the dielectric adapter and that presses the dielectric adapter against the cover layer. The biasing force may be oriented in a direction normal to the cover layer at each point across dielectric adapter. This may serve to ensure that a uniform and reliable impedance transition is provided between the antenna and free space through the cover layer over time, thereby maximizing the efficiency of the antenna.

Abstract: The present disclosure generally relates to memory devices and methods of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices. The present disclosure provides a memory device including an opening in a dielectric structure, the opening having a sidewall, a first electrode on the sidewall of the opening, a spacer layer on the first electrode, a resistive layer on the first electrode and upon an upper surface of the spacer layer, and a second electrode on the resistive layer.