Abstract: An image processing method includes performing horizontal division and vertical division on a longitude-latitude map or a sphere map of a to-be-processed image to obtain sub-areas of the longitude-latitude map or the sphere map, where a division location of the horizontal division is a preset latitude, a division location of the vertical division is determined by a latitude, there are at least two types of vertical division intervals in an area formed by adjacent division locations of the horizontal division, and a vertical division interval is a distance between adjacent division locations of the vertical division, and encoding images of the sub-areas.

Abstract: Semiconductor devices and methods of forming the same include forming slanted dielectric structures from a first dielectric material on a substrate, with gaps between adjacent slanted dielectric structures. A first semiconductor layer is grown from the substrate, using a first semiconductor material, including a lower portion that fills the gaps and an upper portion above the first dielectric material. The lower portion of the first semiconductor layer is replaced with additional dielectric material.

Abstract: Embodiments of the invention are directed to a method of forming a semiconductor device. In a non-limiting example, the method includes forming a first channel region over a substrate, forming a second channel region over the first channel region, and forming a merged source or drain (S/D) region over the substrate and adjacent to the first channel region and the second channel region. The merged S/D region is communicatively coupled to the first channel region and the second channel region. A wrap-around S/D contact is formed such that it is on a top surface, sidewalls, and a bottom surface of the merged S/D region.

Abstract: This application provides a video processing method and apparatus. The method includes: adding, by a server, perception attribute information of an object and spatial location information of the object to a video bitstream or a video file, and encapsulating the video bitstream or the video file, where the perception attribute information is used to indicate a property presented when the object is perceived by a user; and obtaining, by a terminal device, the video bitstream or the video file that carries the perception attribute information of the object and the spatial location information of the object, and performing perception rendering on a perception attribute of the object based on behavior of the user, the perception attribute information of the object and the spatial location information of the object.

Abstract: A mobile station receives a downlink control structure in a first carrier, where the downlink control structure indicates that control information for the mobile station is on a second, different carrier. The mobile station decodes the control information in the second carrier, where the control information specifies resource allocation of a wireless link for the mobile station. More specifically, according to some implementations, the control channel in the first carrier specifies the resource allocation for an extended control channel in the second carrier, where the extended control channel specifies the resource allocation for traffic data of a wireless link for the mobile station.

Abstract: Semiconductor devices and methods of forming the same include forming slanted dielectric structures from a first dielectric material on a substrate, with gaps between adjacent slanted dielectric structures. A first semiconductor layer is grown from the substrate, using a first semiconductor material, including a lower portion that fills the gaps and an upper portion above the first dielectric material. The lower portion of the first semiconductor layer is replaced with additional dielectric material.

Abstract: An image processing method includes determining, based on a coordinate position of a to-be-interpolated sample in a target image, a first coordinate position of the to-be-interpolated sample in a source image, determining m reference samples based on the first coordinate position, determining an interpolation weight of each of the m reference samples for the to-be-interpolated sample based on a spherical distance between a coordinate position of each of the m reference samples and the first coordinate position, and determining a pixel value of the to-be-interpolated sample based on a pixel value corresponding to each of the m reference samples and the interpolation weight of each of the m reference samples for the to-be-interpolated sample to obtain the target image.

Abstract: A method for fabricating an electronic fuse includes forming a recess within a film material to define opposed contact segments and a central fuse segment interconnecting the contact segments and altering the material of the central fuse segment of the film material to increase electrical resistance characteristics of the central fuse segment. The central fuse segment may include defects such as voids created by directing a laser at the central fuse segment as a component of a laser annealing process. Alternatively, and or additionally, the central fuse segment may include dopants implementing via an ion implantation process to increase resistance characteristics of the central fuse segment.

Abstract: In some implementations, a method in a user equipment (UE) for supporting group communication service includes receiving, from a base station, a group communication on a Physical Downlink Shared Channel (PDSCH). The UE determines a first Hybrid Automatic Repeat reQuest (HARQ) information that corresponds to the group communication on the PDSCH. The UE transmits the first HARQ information. In some implementations, the UE determines a group Channel State Information (CSI) for a group communication that is transmitted by a base station on a PDSCH. The UE determines a unicast CSI for a unicast communication that is transmitted by the base station on the PDSCH. The UE transmits the group CSI. The UE transmits the unicast CSI.

Abstract: Disclosed herein is a jig for assembly of a battery module, the jig including a housing having a first accommodation portion configured to accommodate a battery cell and a second accommodation portion disposed so as to be spaced apart from the first accommodation portion, the second accommodation portion being configured to accommodate a circuit board in the state of being spaced apart from the battery cell, wherein the battery cell is accommodated in the first accommodation portion, and the circuit board is accommodated in the second accommodation portion, whereby the orientation of the circuit board with respect to the battery cell may be maintained.

Abstract: A method of forming a semiconductor structure includes forming a nanosheet stack over a substrate, the nanosheet stack including alternating sacrificial and channel layers, the channel layers providing nanosheet channels for nanosheet field-effect transistors. The method also includes forming vertical fins in the nanosheet stack and a portion of the substrate, and forming indents in sidewalls of the sacrificial layers at sidewalls of the vertical fins. The method further includes forming nanosheet extension regions in portions of the channel layers which extend from the indented sidewalls of the sacrificial layers to the sidewalls of the vertical fins, the nanosheet extension regions increasing in thickness from the indented sidewalls of the sacrificial layers to the sidewalls of the vertical fins. The method further includes forming inner spacers using a conformal deposition process that forms air gaps in spaces between the nanosheet extension regions and the indented sidewalls of the sacrificial layers.

Abstract: Semiconductor devices and methods are provided to fabricate fin field-effect transistor (FinFET) devices having uniform fin height profiles. For example, uniformity of fin height profiles for FinFET devices is obtained by implementing a gate oxide removal process which is designed to prevent etching of an isolation layer (e.g., a shallow trench isolation layer) formed of an oxide material during removal of, e.g., sacrificial gate oxide layers of dummy gate structures during a replacement metal gate process.

Abstract: A method and structure of forming air gaps with a sidewall image transfer process such as self-aligned double patterning to reduce capacitances. Different materials can be provided in the mandrel and non-mandrel regions to enlarge a process window for metal line end formation.

Abstract: A method of forming a semiconductor structure includes forming a fin over a substrate, forming a bottom source/drain over the substrate surrounding a first portion of sidewalls of the fin, and forming a bottom spacer over the bottom source/drain and surrounding a second portion of the sidewalls of the fin. The method also includes forming a T-shaped gate stack over the bottom spacer and surrounding a third portion of the sidewalls of the fin, forming a top spacer over the T-shaped gate stack and surrounding a fourth portion of the sidewalls of the fin, and forming a top source/drain over the top spacer and surrounding a fifth portion of the sidewalls and a top surface of the fin. The T-shaped gate stack includes a gate dielectric, a gate conductor, and a gate metal extending outward from a portion of sidewalls of the gate conductor between the bottom and top spacers.

Abstract: The present invention provides for an improved application of signal strength weightings in a SDMA sectorized cellular network. The improved signal strength weightings application is conducted through the improved selection of weightings from a new codebook subset or by the selection of weightings from a larger codebook subset. In a further embodiment, an antenna beam index or bit map can be used to select the best beam(s) in a SDMA sectorized cellular network. In another embodiment, a field or factor in an uplink or downlink transmission packet can designate which directional transmission beam is best suited for the transmission or when the directional transmission beam should be activated.

Abstract: Devices and methods are provided for fabricating field-effect transistors having source/drain extension contacts to provide reduced parasitic resistance in electrical paths between source/drain layers and active channel layers surrounded by gate structures of the field-effect transistor devices. For example, in a nanosheet field-effect transistor device having embedded gate sidewall spacers which are disposed between end portions of active nanosheet channel layers and serve to insulate source/drain layers from a metal gate structure, epitaxial source/drain extension contacts are disposed between the embedded gate sidewall spacers and active nanosheet channel layers, and on sidewall surfaces of the active nanosheet channel layers. Epitaxial source/drain layers are grown starting on exposed surfaces of the epitaxial source/drain extension contacts.

Abstract: Semiconductor devices and methods of forming the same include forming a doped drain structure having a first conductivity type on sidewalls of an intrinsic channel layer. An opening is etched in a middle of the channel layer. A doped source structure is formed having a second conductivity type in the opening of the channel layer.

Abstract: A semiconductor structure includes a decoupling capacitor on a semiconductor substrate. The decoupling capacitor includes a multilayer stack structure having one or more active regions on a top surface thereof. The semiconductor structure further includes one or more semiconductor devices on the one or more active regions on the decoupling capacitor.

Abstract: Methods, systems and apparatus are provided for camping, assisted serving cell addition or removal, and discontinuous reception (DRX) in networks having a macro cell and at least one assisted serving cell. In other aspects, enhancements to Layer 1 channels and uplink timing alignments are provided in networks having a macro cell and at least one assisted serving cell. In further aspects, assisted serving cell Layer 2 architecture and transport channels are provided in networks having a macro cell and at least one assisted serving cell. In further aspects, collaborated HARQ solutions are provided in networks having a macro cell and at least one assisted serving cell.

Abstract: Described herein is a system with a first network element and a second network element. The first network element contains a processor configured to synchronize with the second network element; and maintain synchronization with the second network element. The first network element is a small cell eNB and the second network element is one of the following: a macro cell enhanced node-B (eNB); or a small cell eNB.