Patents by Inventor Yoshifumi Yoshida

Yoshifumi Yoshida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050062890
    Abstract: A video signal processing device is provided comprising an input level detecting circuit for detecting an amplitude of a video signal to be processed and an analog/digital converter for performing analog/digital conversion of the video signal using as a reference voltage a voltage in accordance with the amplitude of the video signal detected by the input level detecting circuit.
    Type: Application
    Filed: September 17, 2004
    Publication date: March 24, 2005
    Inventor: Yoshifumi Yoshida
  • Publication number: 20050043461
    Abstract: A flame-retardancy-imparting material containing ammonium nitrate and aluminum hydroxide, having a content of the ammonium nitrate of 0.05 to 0.2 parts by weight per one part by weight of the aluminum hydroxide, is provided. The ammonium nitrate has a grain form with an average grain size of 0.01 to 100 ?m, and the aluminum hydroxide has a grain form with an average grain size of 0.1 to 100 ?m. The ammonium nitrate is surface-treated with silica, and the aluminum hydroxide is surface-treated with a fatty-acid-base treatment agent. Addition of the ammonium nitrate and aluminum hydroxide in combination is successful in obtaining a sufficient flame retardancy even under a small amount of addition.
    Type: Application
    Filed: September 7, 2004
    Publication date: February 24, 2005
    Inventors: Yoshifumi Yoshida, Tatsuaki Oda
  • Publication number: 20050001269
    Abstract: A memory cell which is formed on a fully depleted SOI or other semiconductor thin film and which operates at low voltage without needing a conventional large capacitor is provided as well as a memory cell array. The semiconductor thin film is sandwiched between first and second semiconductor regions which face each other across the semiconductor thin film and which have a first conductivity type. A third semiconductor region having the opposite conductivity type is provided in an extended portion of the semiconductor thin film. From the third semiconductor region, carriers of the opposite conductivity type are supplied to and accumulated in the semiconductor thin film portion to change the gate threshold voltage of a first conductivity type channel that is induced by a first conductive gate voltage in the semiconductor thin film between the first and second semiconductor regions through an insulating film.
    Type: Application
    Filed: June 28, 2004
    Publication date: January 6, 2005
    Inventors: Yutaka Hayashi, Hisashi Hasegawa, Yoshifumi Yoshida, Jun Osanai
  • Publication number: 20040191967
    Abstract: Conventionally, when an electric potential of a supporting substrate is fixed, there arises a problem in that impact ions are generated even in the vicinity of embedded insulating film in the proximity of a drain due to generation of a parasitic transistor using the supporting substrate as a gate so as to be likely to cause a parasitic bipolar operation.
    Type: Application
    Filed: January 28, 2004
    Publication date: September 30, 2004
    Applicant: SEIKO INSTRUMENTS INC.
    Inventors: Miwa Wake, Yoshifumi Yoshida
  • Patent number: 6740551
    Abstract: A semiconductor integrated circuit is provided in which a change in timing of a circuit or variation in a driving ability do not occur even if the potential of a support substrate is fixed.
    Type: Grant
    Filed: September 6, 2002
    Date of Patent: May 25, 2004
    Assignee: Seiko Instruments Inc.
    Inventors: Yoshifumi Yoshida, Miwa Wake
  • Patent number: 6740561
    Abstract: There is provided a semiconductor device in which improvement of drive capacity and miniaturization are made. A P-type transistor is composed of a surface channel type transistor so that a channel length is easily reduced. Thus, improvement of drive capacity and miniaturization are promoted. Further, since a gate insulating film is nitrided, reliability of the gate insulating film is improved and passing of boron contained in a p-type polycrystalline silicon gate electrode toward a channel region can be prevented. A step of forming the gate insulating film, a step of nitriding the gate insulating film, a step of performing thermal treatment using an inert gas, a step of forming a gate electrode on the gate insulating film, and a step of introducing a p-type impurity into the gate electrode are performed. Thus, a surface channel P-type transistor and a buried channel N-type transistor are constructed.
    Type: Grant
    Filed: March 7, 2002
    Date of Patent: May 25, 2004
    Assignee: Seiko Instruments Inc.
    Inventors: Yoshifumi Yoshida, Jun Osanai
  • Publication number: 20040090806
    Abstract: A power source inverter circuit is provided which, when a feeding unit generates enough electric power, puts a load circuit into operation while storing electric power in a storage unit and, when the power feeding unit stops generating power, efficiently uses up the electric power stored in the storage unit.
    Type: Application
    Filed: June 12, 2003
    Publication date: May 13, 2004
    Inventors: Yoshifumi Yoshida, Fumiyasu Utsunomiya
  • Patent number: 6713325
    Abstract: Conventionally, when an electric potential of a supporting substrate is fixed, there arises a problem in that impact ions are generated even in the vicinity of embedded insulating film in the proximity of a drain due to generation of a parasitic transistor using the supporting substrate as a gate so as to be likely to cause a parasitic bipolar operation.
    Type: Grant
    Filed: October 9, 2002
    Date of Patent: March 30, 2004
    Assignee: Seiko Instruments Inc.
    Inventors: Miwa Wake, Yoshifumi Yoshida
  • Patent number: 6677644
    Abstract: An integrated circuit formed on a SOI substrate has a low withstand voltage MOS transistors formed in the SOI substrate and comprising source and drain regions formed in the semiconductor film of the SOI substrate, a gate insulating film formed over the semiconductor film between the source and drain regions, and a gate electrode formed over the gate insulating film. High withstand voltage MOS transistors are formed in the SOI substrate and comprise openings formed in the semiconductor film to expose the insulating film, a gate electrode formed of a portion of the semiconductor film between the openings, a gate oxide film comprised of the insulating film on the supporting substrate under the gate electrode, and a polysilicon film formed on the gate electrode so as to come in contact with a sidewall of the gate electrode and the insulating film at a bottom surface of the openings.
    Type: Grant
    Filed: June 28, 2001
    Date of Patent: January 13, 2004
    Assignee: Seiko Instruments Inc.
    Inventor: Yoshifumi Yoshida
  • Publication number: 20030218193
    Abstract: The gate threshold voltage is electronically controlled in an insulated gate transistor formed in a semiconductor thin film, such as fully depleted SOI, that is depleted of carriers between first and second principal surfaces. A third semiconductor region of the opposite conductivity type is placed such that it is in contact with the semiconductor thin film. The amount of carriers in the semiconductor thin film is controlled by supplying the semiconductor thin film with carriers of the opposite conductivity type from the third semiconductor region, or by drawing carriers of the opposite conductivity type from the semiconductor thin film into the third semiconductor region.
    Type: Application
    Filed: April 9, 2003
    Publication date: November 27, 2003
    Inventors: Yutaka Hayashi, Hisashi Hasegawa, Yoshifumi Yoshida, Jun Osanai
  • Publication number: 20030213994
    Abstract: A memory cell which is formed on a fully depleted SOI or other semiconductor thin film and which operates at low voltage without needing a conventional large capacitor is provided as well as a memory cell array. The semiconductor thin film is sandwiched between first and second semiconductor regions which face each other across the semiconductor thin film and which have a first conductivity type. A third semiconductor region having the opposite conductivity type is provided in an extended portion of the semiconductor thin film. From the third semiconductor region, carriers of the opposite conductivity type are supplied to and accumulated in the semiconductor thin film portion to change the gate threshold voltage of a first conductivity type channel that is induced by a first conductive gate voltage in the semiconductor thin film between the first and second semiconductor regions through an insulating film.
    Type: Application
    Filed: April 9, 2003
    Publication date: November 20, 2003
    Inventors: Yutaka Hayashi, Hisashi Hasegawa, Yoshifumi Yoshida, Jun Osanai
  • Publication number: 20030176990
    Abstract: A measurement data collection apparatus includes at least a collection/analysis processing device having a measuring instrument interface for converting measurement data input from a measuring instrument into data of a form corresponding to measurement contents, and a measurement data collection interface for converting the data of the form corresponding to the measurement contents into measurement data of a predetermined form. The apparatus can process the results obtained from the measurement as electronic data irrespective of the measurement contents or a kind of the measuring instrument and can perform form printing or data processing such as arithmetic operations.
    Type: Application
    Filed: November 1, 2002
    Publication date: September 18, 2003
    Inventors: Koichi Kojima, Yoshifumi Yoshida, Yuya Ichikawa, Atsushi Hirai, Hideo Torii
  • Publication number: 20030176939
    Abstract: A manufacturing system has an inspection data collecting apparatus that is capable of carrying out, upon receipt of a signal containing measurement data in different formats according to the type of inspection or a measuring instrument, processing in accordance with the signal and the format of data to create data in a certain format, and of transmitting a signal for giving an instruction to the measuring instrument in association with the format compatible with the measuring instrument. All data obtained by the inspections in all steps for manufacturing a product is accumulated as inspection data and exchanged among the steps.
    Type: Application
    Filed: January 14, 2003
    Publication date: September 18, 2003
    Inventors: Yoshifumi Yoshida, Koichi Kojima, Yuya Ichikawa, Atsushi Hirai, Hideo Torii
  • Publication number: 20030155615
    Abstract: To provide a semiconductor integrated circuit with a small change in characteristics and further with ideal subthreshold characteristics, in which an influence of a potential of a support substrate is suppressed.
    Type: Application
    Filed: February 7, 2003
    Publication date: August 21, 2003
    Inventors: Yoshifumi Yoshida, Miwa Wake
  • Publication number: 20030129792
    Abstract: Conventionally, when an electric potential of a supporting substrate is fixed, there arises a problem in that impact ions are generated even in the vicinity of embedded insulating film in the proximity of a drain due to generation of a parasitic transistor using the supporting substrate as a gate so as to be likely to cause a parasitic bipolar operation.
    Type: Application
    Filed: October 9, 2002
    Publication date: July 10, 2003
    Inventors: Miwa Wake, Yoshifumi Yoshida
  • Patent number: 6579954
    Abstract: A thermoplastic resin composition comprising an aromatic polysulfone resin and at least one resin selected from aromatic polyester resins, wherein the amount of alkali metal which exists in the aromatic polysulfone resin as a terminal phenolate is 50 ppm or less, and molded article thereof. This composition is excellent in heat resistance and melt-mold processability.
    Type: Grant
    Filed: February 19, 1999
    Date of Patent: June 17, 2003
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Tohru Nagashima, Yoshifumi Yoshida, Hiroshi Nakamura
  • Publication number: 20030054594
    Abstract: A semiconductor integrated circuit is provided in which a change in timing of a circuit or variation in a driving ability do not occur even if the potential of a support substrate is fixed.
    Type: Application
    Filed: September 6, 2002
    Publication date: March 20, 2003
    Inventors: Yoshifumi Yoshida, Miwa Wake
  • Publication number: 20020149038
    Abstract: There is provided a semiconductor device in which improvement of drive capacity, miniaturization, improvement of reliability of a gate insulating film are achieved. The semiconductor device includes a gate insulating film which is located on a semiconductor substrate and nitrided, a P-type polycrystalline silicon gate electrode located on the gate insulating film, an insulating film located on the gate electrode, low concentration impurity regions each having a low concentration impurity introduced in the vicinity of the surface of the semiconductor substrate in a self alignment manner using the gate electrode as a mask, and high concentration impurity regions which are spaced from the gate electrode and each have a high concentration impurity introduced in the vicinity of the surface of the semiconductor substrate. Such a semiconductor device composes a surface channel P-type transistor and a buried channel N-type transistor.
    Type: Application
    Filed: April 3, 2002
    Publication date: October 17, 2002
    Inventors: Yoshifumi Yoshida, Jun Osanai
  • Publication number: 20020151631
    Abstract: Ammonium nitrate powder 10 and aluminum hydroxide powder 39, both of which are flame-retardant materials, are blended and kneaded with a polymer material 41 which should serve as a matrix, to thereby obtain a compound 531. A polymer material obtained by molding such compound 531 by a predetermined molding process will have an excellent flame retardancy without being significantly modified in polymer properties thereof as compared with those before the flame-retardant material is compounded.
    Type: Application
    Filed: January 30, 2002
    Publication date: October 17, 2002
    Applicant: Ishizuka Garasu Kabushiki Kaisha
    Inventors: Yoshifumi Yoshida, Tatsuaki Oda
  • Publication number: 20020151129
    Abstract: There is provided a semiconductor device in which improvement of drive capacity and miniaturization are made. A P-type transistor is composed of a surface channel type transistor so that a channel length is easily reduced. Thus, improvement of drive capacity and miniaturization are promoted. Further, since a gate insulating film is nitrided, reliability of the gate insulating film is improved and passing of boron contained in a p-type polycrystalline silicon gate electrode toward a channel region can be prevented. A step of forming the gate insulating film, a step of nitriding the gate insulating film, a step of performing thermal treatment using an inert gas, a step of forming a gate electrode on the gate insulating film, and a step of introducing a p-type impurity into the gate electrode are performed. Thus, a surface channel P-type transistor and a buried channel N-type transistor are constructed.
    Type: Application
    Filed: March 7, 2002
    Publication date: October 17, 2002
    Inventors: Yoshifumi Yoshida, Jun Osanai