Patents by Inventor Yoshimasa Chikama

Yoshimasa Chikama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130092923
    Abstract: An active matrix substrate includes a plurality of pixel electrodes (19a) arranged in a matrix, and a plurality of TFTs (5a) connected to the respective corresponding pixel electrodes (19a). Each TFT (5a) includes a gate electrode (11aa) provided on an insulating substrate (10a), a gate insulating layer (12) covering the gate electrode (11aa), an oxide semiconductor layer (13a) provided on the gate insulating layer (12) over the gate electrode (11aa) and having a channel region (C), and a source electrode (16aa) and a drain electrode (16b) provided on the oxide semiconductor layer (13a), overlapping the gate electrode (11aa) and facing each other with the channel region (C) being interposed between the source and drain electrodes. A protection insulating layer (17) made of a spin-on glass material is provided on the channel region (C) of the oxide semiconductor layer (13a).
    Type: Application
    Filed: January 12, 2011
    Publication date: April 18, 2013
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Takeshi Hara, Hirohiko Nishiki, Yoshifumi Ohta, Yoshimasa Chikama, Tetsuya Aita, Masahiko Suzuki, Michiko Takei, Okifumi Nakagawa, Yoshiyuki Harumoto, Hinae Mizuno
  • Publication number: 20130056741
    Abstract: A display panel (50a) includes a TFT substrate (20a) in which a plurality of TFTs (5a) are provided, a counter substrate (30a) provided to face the TFT substrate (20a), and a display medium layer (40) provided between the TFT substrate (20a) and the counter substrate (30a), a plurality of pixels being provided so that each of the plurality of pixels is associated with a corresponding one of the TFTs (5a), wherein an oxide semiconductor layer (13) is provided in each of the TFTs (5a) as a channel, and an ultraviolet light absorbing layer (22) having a light transmitting property is provided in each of the pixels (P) so as to overlap the oxide semiconductor layer (13).
    Type: Application
    Filed: February 14, 2011
    Publication date: March 7, 2013
    Applicants: SHARP KABUSHIKI KAISHA
    Inventors: Yoshiyuki Harumoto, Yoshifumi Ohta, Yoshimasa Chikama, Tokuo Yoshida, Masahiko Suzuki, Okifumi Nakagawa, Yoshinobu Miyamoto, Tetsuya Yamashita, Hinae Mizuno
  • Publication number: 20130026462
    Abstract: A method for manufacturing a thin film transistor includes the step of forming a gate electrode (11aa) on an insulating substrate, the step of forming a gate insulating layer (12) to cover the gate electrode (11aa), and thereafter, forming an oxide semiconductor layer (13a) on the gate insulating layer (12), the step of forming a source electrode (16aa) and a drain electrode (16b) on the oxide semiconductor layer (13a) by dry etching, with a channel region (C) of the oxide semiconductor layer being exposed, and the step of supplying oxygen radicals to a channel region of the oxide semiconductor layer.
    Type: Application
    Filed: February 14, 2011
    Publication date: January 31, 2013
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Michiko Takei, Yoshimasa Chikama, Tsuyoshi Inoue, Masahiko Suzuki, Okifumi Nakagawa, Yoshifumi Ohta, Yoshiyuki Harumoto, Hinae Mizuno
  • Publication number: 20130023086
    Abstract: An active matrix substrate includes a plurality of pixel electrodes (P) provided in a matrix, and a plurality of TFTs (5) connected to the pixel electrodes (P). Each of the TFTs (5) includes a gate electrode (11a) provided on an insulating substrate, a gate insulating film (12a) provided to cover the gate electrode (11a), an oxide semiconductor layer (13a) provided on the gate insulating film (12a) to overlap the gate electrode (11a), and a source electrode (17a) and a drain electrode (17b) facing each other and being connected to the oxide semiconductor layer (13a). A protective insulating film (14a) is provided between the oxide semiconductor layer (13a) and the source and drain electrodes (17a) and (17b) to cover the oxide semiconductor layer (13a).
    Type: Application
    Filed: August 23, 2010
    Publication date: January 24, 2013
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Yoshimasa Chikama, Hiromitsu Katsui, Hirohiko Nishiki, Yoshifumi Ohta, Takeshi Hara, Tetsuya Aita, Masahiko Suzuki, Michiko Takei, Okifumi Nakagawa, Yoshiyuki Harumoto, Hinae Mizuno
  • Publication number: 20120326144
    Abstract: A method includes: a step of forming a gate electrode (14) on a substrate (10a); a step of forming a gate insulating film (15) to cover the gate electrode (14), and then forming an In-Ga-Zn-O-based oxide semiconductor layer (16) in which a ratio of In:Ga:Zn in atomic % is 1:1:1 or 4:5:1 on the gate insulating film (15) to overlap the gate electrode (14); a step of forming a source electrode (19a) and a drain electrode (19b) on the oxide semiconductor layer (16) to overlap the gate electrode (14) and to face each other; and a step of performing an annealing process in an atmosphere containing steam (S) on the substrate (10a) provided with the source electrode (19a) and the drain electrode (19b).
    Type: Application
    Filed: February 9, 2011
    Publication date: December 27, 2012
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Yoshifumi Ohta, Yoshimasa Chikama, Masahiko Suzuki, Okifumi Nakagawa, Yoshiyuki Harumoto
  • Patent number: 8304873
    Abstract: A method for manufacturing a display device includes a first step of preparing a first substrate which has a first area to be etched and a second area located at a periphery of the first area and which has a display element on its surface, a second step of etching and removing the first area of the first substrate, a third step of forming a second substrate on a surface of the first substrate that is opposite to the surface on which the display element is located, and a fourth step of removing the second area of the first substrate.
    Type: Grant
    Filed: January 11, 2008
    Date of Patent: November 6, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tohru Okabe, Yoshimasa Chikama
  • Publication number: 20120241750
    Abstract: A semiconductor device includes: a thin film transistor having a gate line (3a), a first insulating film (5), an island-shaped oxide semiconductor layer (7a), a second insulating film (9), a source line (13as), a drain electrode (13ad), and a passivation film; and a terminal portion having a first connecting portion (3c) made of the same conductive film as the gate line, a second connecting portion (13c) made of the same conductive film as the source line and the drain electrode, and a third connecting portion (19c) formed on the second connecting portion.
    Type: Application
    Filed: December 3, 2010
    Publication date: September 27, 2012
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Yoshimasa Chikama, Hirohiko Nishiki, Yoshifumi Ohta, Yuuji Mizuno, Hinae Mizuno, Takeshi Hara, Tetsuya Aita, Masahiko Suzuki, Michiko Takei, Okifumi Nakagawa, Yoshiyuki Harumoto
  • Publication number: 20120223308
    Abstract: The present invention provides a thin-film transistor capable of high-speed operation, a process for producing the same, and a display device including the same. The thin-film transistor of the present invention includes, on a substrate, in the order of: a gate electrode; a gate insulating film; an oxide semiconductor film; and a protective insulating film, the protective insulating film having a planar shape that is completely or substantially the same as the planar shape of the gate electrode.
    Type: Application
    Filed: June 17, 2010
    Publication date: September 6, 2012
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Yoshimasa Chikama
  • Publication number: 20120218485
    Abstract: An active matrix substrate includes a plurality of pixels arranged in a matrix, a plurality of capacitor lines (11b) extending in one of directions in which the pixels are aligned and in parallel to each other, a plurality of TFTs (5), one for each of the pixels, a protective film (16a) covering the TFTs (5), a plurality of pixel electrodes (18a) arranged in a matrix on the protective film (16a) and connected to the respective corresponding TFTs (5), and a plurality of auxiliary capacitors (6), one for each of the pixels. Each of the auxiliary capacitors (6) includes the corresponding capacitor line (11b), the corresponding pixel electrode (18a), and the protective film (16a) between the corresponding capacitor line (11b) and the corresponding pixel electrode (18a).
    Type: Application
    Filed: July 26, 2010
    Publication date: August 30, 2012
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Yoshimasa Chikama, Hirohiko Nishiki, Yoshifumi Ohta, Yuuji Mizuno, Hinae Mizuno, Takeshi Hara, Tetsuya Aita, Masahiko Suzuki, Michiko Takei, Okifumi Nakagawa, Yoshiyuki Harumoto
  • Publication number: 20120199891
    Abstract: A semiconductor device includes: a gate electrode (3) arranged on a substrate (1); a gate insulating layer (5) deposited over the gate electrode (3); an island of an oxide semiconductor layer (7) formed on the gate insulating layer (5) and including a channel region (7c) and first and second contact regions (7s, 7d) located on right- and left-hand sides of the channel region (7c); a source electrode (11) electrically connected to the first contact region (7s); a drain electrode (13) electrically connected to the second contact region (7d); and a protective layer (9) which is arranged on, and in contact with, the oxide semiconductor layer (7). The protective layer (9) covers the channel region (7c) on the surface of the oxide semiconductor layer (7), the sidewalls (7e) thereof located in a channel width direction with respect to the channel region (7c), and other portions (7f) thereof between the channel region (7c) and the sidewalls (7e).
    Type: Application
    Filed: October 4, 2010
    Publication date: August 9, 2012
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Masahiko Suzuki, Hirohiko Nishiki, Yoshimasa Chikama, Yoshifumi Ohta, Tetsuya Aita, Okifumi Nakagawa, Takeshi Hara
  • Publication number: 20120108018
    Abstract: A method for manufacturing a thin film transistor substrate includes a step of forming a gate electrode (11a) and a first interconnect on a substrate (10), a step of forming a gate insulating film (12a) having a contact hole at a position overlapping the first interconnect, a step of forming a source electrode (13a) and a drain electrode (13b) overlapping the gate electrode (11a) and separated apart from each other, and a second interconnect connected via the contact hole to the first interconnect, a step of successively forming an oxide semiconductor film (14) and a second insulating film (15), and thereafter, patterning the second insulating film (15) to form an interlayer insulating film (15a), and a step of reducing the resistance of the oxide semiconductor film (14) exposed through the interlayer insulating film (15a) to form a pixel electrode (14b).
    Type: Application
    Filed: March 16, 2010
    Publication date: May 3, 2012
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Hirohiko Nishiki, Yoshimasa Chikama, Takeshi Hara
  • Publication number: 20120091452
    Abstract: The present invention provides an oxide semiconductor capable of achieving a thin film transistor having stable transistor characteristics, a thin film transistor having a channel layer formed of the oxide semiconductor and a production method thereof, and a display device equipped with the thin film transistor. The oxide semiconductor of the present invention is an oxide semiconductor for a thin film transistor. The oxide semiconductor includes indium, gallium, zinc, and oxygen as constituent atoms, and the oxygen content of the oxide semiconductor is 87% to 95% of the stoichiometric condition set as 100%, in terms of atomic units.
    Type: Application
    Filed: March 10, 2010
    Publication date: April 19, 2012
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Yoshifumi Ohta, Go Mori, Hirohiko Nishiki, Yoshimasa Chikama, Tetsuya Aita, Masahiko Suzuki, Okifumi Nakagawa, Michiko Takei, Yoshiyuki Harumoto, Takeshi Hara
  • Patent number: 8094268
    Abstract: [MEANS FOR SOLVING THE PROBLEMS] A liquid crystal display substrate includes an insulating substrate 10, an interlayer insulating film 11 formed on the insulating substrate 10, an interlayer insulating film 11a in a transmitting portion T, a reflecting metal film 12 formed on an interlayer insulating film 11b in a reflecting portion R, and a color filter 13 formed on the interlayer insulating film 11a and the reflecting metal film 12. The interlayer insulating film 11b in the reflecting portion R has a corrugated surface formed by concave portions and convex portions. A height h1 of the interlayer insulating film 11a in the transmitting portion T is equal to or lower than a height h2 of the convex portion. The liquid crystal display substrate further includes a transparent dielectric layer 14 on the color filter 13 formed in the reflecting portion R.
    Type: Grant
    Filed: July 12, 2006
    Date of Patent: January 10, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tohru Okabe, Yoshimasa Chikama
  • Patent number: 7957151
    Abstract: An electrode connection structure including a first circuit component including a resin plate, a barrier film stacked on a surface of the resin plate, a circuit section formed on the barrier film and a first electrode provided on the surface of the resin plate on which the barrier film is stacked, and a second circuit component arranged to face the first circuit component and having a second electrode facing the first electrode, wherein the first and second electrodes are electrically connected via pressure applied thereto in the directions approaching each other and a portion of the barrier film surrounding the first electrode is at least partially removed from the surface of the resin plate.
    Type: Grant
    Filed: October 30, 2006
    Date of Patent: June 7, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tetsuya Aita, Yoshimasa Chikama
  • Publication number: 20110043720
    Abstract: A method for manufacturing a display device includes; a first step of preparing a plastic substrate placed on a support substrate, a second step of bonding a first region of an expanded silicone sheet to an end of the plastic substrate, and bonding a second region of the silicone sheet to the support substrate having the plastic substrate placed thereon, thereby fixing the plastic substrate to the support substrate by a biasing force of the silicone sheet, and a third step of laminating a plurality of thin films over the plastic substrate fixed to the support substrate.
    Type: Application
    Filed: July 4, 2008
    Publication date: February 24, 2011
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Yoshimasa Chikama, Yohsuke Kanzaki, Yuya Nakano
  • Publication number: 20100316870
    Abstract: A method for manufacturing a display device includes a first step of preparing a first substrate which has a first area to be etched and a second area located at a periphery of the first area and which has a display element on its surface, a second step of etching and removing the first area of the first substrate, a third step of forming a second substrate on a surface of the first substrate that is opposite to the surface on which the display element is located, and a fourth step of removing the second area of the first substrate.
    Type: Application
    Filed: January 11, 2008
    Publication date: December 16, 2010
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Yoshimasa Chikama
  • Patent number: 7670656
    Abstract: A plastic substrate includes resin and glass fibers. In an end surface of the substrate, interfaces between the glass fibers and the resin are covered with a solidified melt of the glass fibers.
    Type: Grant
    Filed: May 1, 2006
    Date of Patent: March 2, 2010
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Yoshimasa Chikama
  • Publication number: 20100013785
    Abstract: A display panel substrate according to the present invention includes at least an insulating substrate, first conductive wires formed on the insulating substrate, a piezoelectric material film formed on the first conductive wires, second conductive wires intersecting with the first conductive wires, and a protecting film for protecting the first conductive wires, the second conductive wires, and the piezoelectric material film. The insulating film is formed at least in an area in an effective display area on the insulating substrate. The piezoelectric film is formed at least at an intersection of a first conductive wire and a second conductive wire. This makes it possible to provide a display panel substrate that allows integration of a touch panel function into a display panel without causing an increase in size of the display panel.
    Type: Application
    Filed: December 17, 2007
    Publication date: January 21, 2010
    Inventors: Atsuhito Murai, Yoshimasa Chikama, Kazuki Takahashi
  • Publication number: 20090279026
    Abstract: [Means for Solving the Problems] A liquid crystal display substrate includes an insulating substrate 10, an interlayer insulating film 11 formed on the insulating substrate 10, an interlayer insulating film 11a in a transmitting portion T, a reflecting metal film 12 formed on an interlayer insulating film 11b in a reflecting portion R, and a color filter 13 formed on the interlayer insulating film 11a and the reflecting metal film 12. The interlayer insulating film 11b in the reflecting portion R has a corrugated surface formed by concave portions and convex portions. A height h1 of the interlayer insulating film 11a in the transmitting portion T is equal to or lower than a height h2 of the convex portion. The liquid crystal display substrate further includes a transparent dielectric layer 14 on the color filter 13 formed in the reflecting portion R.
    Type: Application
    Filed: July 12, 2006
    Publication date: November 12, 2009
    Inventors: Tohru Okabe, Yoshimasa Chikama
  • Publication number: 20090141438
    Abstract: An electrode connection structure including a first circuit component including a resin plate, a barrier film stacked on a surface of the resin plate, a circuit section formed on the barrier film and a first electrode provided on the surface of the resin plate on which the barrier film is stacked, and a second circuit component arranged to face the first circuit component and having a second electrode facing the first electrode, wherein the first and second electrodes are electrically connected via pressure applied thereto in the directions approaching each other and a portion of the barrier film surrounding the first electrode is at least partially removed from the surface of the resin plate.
    Type: Application
    Filed: October 30, 2006
    Publication date: June 4, 2009
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Tetsuya Aita, Yoshimasa Chikama