Patents by Inventor Yoshimasa Chikama

Yoshimasa Chikama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090061182
    Abstract: A plastic substrate includes resin and glass fibers. In an end surface of the substrate, interfaces between the glass fibers and the resin are covered with a solidified melt of the glass fibers.
    Type: Application
    Filed: May 1, 2006
    Publication date: March 5, 2009
    Applicant: SHARP KABUSHIKI KAISHA
    Inventor: Yoshimasa Chikama
  • Patent number: 7075614
    Abstract: There is provided an active matrix substrate which enables to shorten a fabrication process of a pixel electrode, improve exposure precision by self alignment, and prevent leakage failures between pixel electrodes. On top of the interlayer insulating film, there are formed pixel electrodes, which are connected to the TFTs through contact holes piercing through the interlayer insulating film. The pixel electrodes are formed by applying on the interlayer insulating film a photosensitive transparent resin such as negative acrylic polymerized resin containing ITO, ATO or ZnO as transparent conductive particles, performing exposure from the back side of the substrate, and conducting development.
    Type: Grant
    Filed: December 31, 2003
    Date of Patent: July 11, 2006
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshihiro Izumi, Yoshimasa Chikama
  • Patent number: 6897135
    Abstract: In the present method for fabricating metal interconnections, a Ni film is deposited on an insulating substrate by electroless plating, and a photoresist film is formed in a specified pattern on the Ni film. An Au film is deposited by electroless plating in a region where the Ni film is exposed and where the resist is not formed. The photoresist film is removed, and the Ni film exposed by the removal of the photoresist film is removed by etching. A Cu film is formed on the Au film by electroplating or electroless plating selectively. This method consists of only wet deposition process, involves less etching process and provides metal interconnections of low resistance.
    Type: Grant
    Filed: May 3, 2002
    Date of Patent: May 24, 2005
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshihiro Izumi, Yoshimasa Chikama
  • Patent number: 6864936
    Abstract: An active matrix substrate includes: electrode wires constituted by gate electrodes 2 and source electrodes 6 that are arranged in a lattice; an insulating protection film provided at least on the electrode wires so as to have openings 11a in predetermined areas on the source electrodes 6; and a metal layer stacked on the source electrodes 6 in the openings 11a. Since there is a metal layer stacked on the source electrodes 6, the source electrodes 6 can be readily increased in thickness and hence sufficiently reduced in resistance, by means of the metal layer. Thus, the electrode wires become thicker and more conducting. This way, it becomes possible to provide active matrix substrates and their methods of manufacturing that are suitably applicable to, for example, display devices and image-capturing devices.
    Type: Grant
    Filed: January 31, 2001
    Date of Patent: March 8, 2005
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshihiro Izumi, Yoshimasa Chikama
  • Patent number: 6802985
    Abstract: There is provided a method for fabricating electrical wirings capable of being manufactured with low cost and easily applied to large-scale substrates. A photosensitive ground resin film is formed on an insulating substrate by coating process. The ground resin film is subjected to exposure and development processes, by which a ground resin film patterned into a wiring pattern is obtained. Then, on the patterned ground resin film, a low-resistance metal film made of Cu is formed by electroless plating.
    Type: Grant
    Filed: August 25, 2000
    Date of Patent: October 12, 2004
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshimasa Chikama, Yoshihiro Izumi
  • Patent number: 6798032
    Abstract: A SnO2 film having a prescribed pattern feature is formed on a substrate by a wet film-formation technology (e.g., sol-gel method). A Ni film is formed on the SnO2 film by an electroless plating method. The electroless plating method is conducted in the presence of at least one sulfur-containing compound selected from the group consisting of thiosulfates, thiocyanates and sulfur-containing organic compounds.
    Type: Grant
    Filed: June 5, 2003
    Date of Patent: September 28, 2004
    Assignees: Sharp Kabushiki Kaisha, Meltex Inc., Sumitomo Osaka Cemento Co., Ltd.
    Inventors: Yoshihiro Izumi, Yoshimasa Chikama, Satoshi Kawashima, Takaharu Hashimoto, Itsuji Yoshikawa, Masaaki Ishikawa
  • Patent number: 6788376
    Abstract: Pixel electrode fabricating processes are remarkably reduced. A pixel electrode 22 is formed without using any vacuum film forming apparatus by employing a sol-gel material and coating an insulating substrate with the sol-gel material by a spin-coating method or a dipping method, and this allows the fabricating processes to be reduced. During this course, by forming the pixel electrode before the formation of a scanning electrode 23, signal wiring lines and a TFT 24, the electrode wiring and the TFT 24 suffer no thermal damage even if they have a heat resistance temperature of about 350° C. Furthermore, by using a sol-gel material having photosensitivity, patterning processes are reduced by the elimination of the photoresist patterning process and the etching process. An investment for the equipment of a fabricating apparatus can thus be reduced to allow the cost reduction of the active matrix substrate itself to be achieved.
    Type: Grant
    Filed: January 24, 2001
    Date of Patent: September 7, 2004
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshihiro Izumi, Yoshimasa Chikama, Hisao Ochi
  • Publication number: 20040150778
    Abstract: There is provided an active matrix substrate which enables to shorten a fabrication process of a pixel electrode, improve exposure precision by self alignment, and prevent leakage failures between pixel electrodes. The active matrix substrate has TFTs disposed in the shape of a matrix. On a light permeable substrate, there are formed gate signal lines and capacity lines. On a gate insulating film on the lines, there are formed in sequence a semiconductor layer, a source electrode and a drain electrode separated right and left by a channel protection layer. Thus, the TFTs are fabricated. Then, the entire substrate is covered with an interlayer insulating film. On top of the interlayer insulating film, there are formed pixel electrodes, which are connected to the TFTs through contact holes piercing through the interlayer insulating film.
    Type: Application
    Filed: December 31, 2003
    Publication date: August 5, 2004
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Yoshihiro Izumi, Yoshimasa Chikama, Atsuhito Murai
  • Patent number: 6770978
    Abstract: There is provided is a metal line structure in which no defect of blistering occurs on a surface of a Cu/Ni film or a Cu/Au/Ni film even if an Ni plating thickness is reduced. According to this metal line 1, in a Cu/Au/Ni film structure in which an Au film 13 and a Cu film 15 are successively laminated by electroless plating on an Ni film 12 formed by electroless plating, the Ni film 12 has a phosphorus content x of 10 wt %≦x≦15 wt %. It was discovered through experiments that the so-called high phosphorus content type Ni film 12 having a phosphorus content x of 10 to 15 percent by weight became a fine smooth film under a condition of a film thickness of 0.1 &mgr;m or greater.
    Type: Grant
    Filed: February 28, 2001
    Date of Patent: August 3, 2004
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshihiro Izumi, Yoshimasa Chikama, Satoshi Kawashima, Takaharu Hashimoto
  • Patent number: 6750475
    Abstract: An oxide film is formed on an insulating substrate by means of a wet type film forming technique such as a sol-gel method, a chemical deposition method or a liquid phase deposition method. Next, the oxide film is patterned according to the shape of interconnections. Then, a metal film made of Ni is formed on an oxide film pattern by such a wet type film forming technique as a wet type plating method. Further, a metal film made of Au that has a low resistance is laminated on the metal film made of Ni by electroless plating, and a metal film made of Cu that has a low resistance and is low cost is laminated on the Au film by electroplating. Thus, by the above method for manufacturing electric interconnections, a large-area interconnection substrate for a display device and an image detector is able to be fabricated at low cost without using a vacuum film forming apparatus.
    Type: Grant
    Filed: May 17, 2000
    Date of Patent: June 15, 2004
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshihiro Izumi, Yoshimasa Chikama, Hisao Ochi
  • Patent number: 6720211
    Abstract: An oxide film is formed on an insulating substrate by means of a wet type film forming technique such as a sol-gel method, a chemical deposition method or a liquid phase deposition method. Next, the oxide film is patterned according to the shape of interconnections. Then, a metal film made of Ni is formed on an oxide film pattern by such a wet type film forming technique as a wet type plating method. Further, a metal film made of Au that has a low resistance is laminated on the metal film made of Ni by electroless plating, and a metal film made of Cu that has a low resistance and is low cost is laminated on the Au film by electroplating. Thus, by the above method for manufacturing electric interconnections, a large-area interconnection substrate for a display device and an image detector is able to be fabricated at low cost without using a vacuum film forming apparatus.
    Type: Grant
    Filed: May 2, 2002
    Date of Patent: April 13, 2004
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshihiro Izumi, Yoshimasa Chikama, Hisao Ochi
  • Publication number: 20030207567
    Abstract: A SnO2 film having a prescribed pattern feature is formed on a substrate by a wet film-formation technology (e.g., sol-gel method). A Ni film is formed on the SnO2 film by an electroless plating method. The electroless plating method is conducted in the presence of at least one sulfur-containing compound selected from the group consisting of thiosulfates, thiocyanates and sulfur-containing organic compounds.
    Type: Application
    Filed: June 5, 2003
    Publication date: November 6, 2003
    Applicants: Sharp Kabushiki Kaisha, Meltex, Inc., Sumitomo Osaka Cemento Co., Ltd.
    Inventors: Yoshihiro Izumi, Yoshimasa Chikama, Satoshi Kawashima, Takaharu Hashimoto, Itsuji Yoshikawa, Masaaki Ishikawa
  • Patent number: 6627544
    Abstract: A SnO2 film having a prescribed pattern feature is formed on a substrate by a wet film-formation technology (e.g., sol-gel method). A Ni film is formed on the SnO2 film by an electroless plating method. The electroless plating method is conducted in the presence of at least one sulfur-containing compound selected from the group consisting of thiosulfates, thiocyanates and sulfur-containing organic compounds.
    Type: Grant
    Filed: May 22, 2002
    Date of Patent: September 30, 2003
    Assignees: Sharp Kabushiki Kaisha, Meltex Inc., Sumitomo Osaka Cemento Co., Ltd.
    Inventors: Yoshihiro Izumi, Yoshimasa Chikama, Satoshi Kawashima, Takaharu Hashimoto, Itsuji Yoshikawa, Masaaki Ishikawa
  • Patent number: 6518676
    Abstract: A ground pattern film 12 for interconnections is formed on a glass substrate 11, and a plating film 13 is formed by selective plating on the ground pattern film 12. A taper angle &agr; which both sides of the plating film 13 form with the surface of the glass substrate 11 is made in the range of 0<&agr;<90°. This arrangement allows the formation of new metal lines on the plating film 13 without a break and allows the patterning of a new film on the plating film 13 without a remaining film.
    Type: Grant
    Filed: May 25, 2001
    Date of Patent: February 11, 2003
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshimasa Chikama, Yoshihiro Izumi
  • Publication number: 20020187266
    Abstract: A SnO2 film having a prescribed pattern feature is formed on a substrate by a wet film-formation technology (e.g., sol-gel method). A Ni film is formed on the SnO2 film by an electroless plating method. The electroless plating method is conducted in the presence of at least one sulfur-containing compound selected from the group consisting of thiosulfates, thiocyanates and sulfur-containing organic compounds.
    Type: Application
    Filed: May 22, 2002
    Publication date: December 12, 2002
    Inventors: Yoshihiro Izumi, Yoshimasa Chikama, Satoshi Kawashima, Takaharu Hashimoto, Itsuji Yoshikawa, Masaaki Ishikawa
  • Publication number: 20020127833
    Abstract: In the present method for fabricating metal interconnections, a Ni film is deposited on an insulating substrate by electroless plating, and a photoresist film is formed in a specified pattern on the Ni film. An Au film is deposited by electroless plating in a region where the Ni film is exposed and where the resist is not formed. The photoresist film is removed, and the Ni film exposed by the removal of the photoresist film is removed by etching. A Cu film is formed on the Au film by electroplating or electroless plating selectively. This method consists of only wet deposition process, involves less etching process and provides metal interconnections of low resistance.
    Type: Application
    Filed: May 3, 2002
    Publication date: September 12, 2002
    Inventors: Yoshihiro Izumi, Yoshimasa Chikama
  • Publication number: 20020123176
    Abstract: An oxide film is formed on an insulating substrate by means of a wet type film forming technique such as a sol-gel method, a chemical deposition method or a liquid phase deposition method. Next, the oxide film is patterned according to the shape of interconnections. Then, a metal film made of Ni is formed on an oxide film pattern by such a wet type film forming technique as a wet type plating method. Further, a metal film made of Au that has a low resistance is laminated on the metal film made of Ni by electroless plating, and a metal film made of Cu that has a low resistance and is low cost is laminated on the Au film by electroplating. Thus, by the above method for manufacturing electric interconnections, a large-area interconnection substrate for a display device and an image detector is able to be fabricated at low cost without using a vacuum film forming apparatus.
    Type: Application
    Filed: May 2, 2002
    Publication date: September 5, 2002
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Yoshihiro Izumi, Yoshimasa Chikama, Hisao Ochi
  • Patent number: 6413845
    Abstract: In the present method for fabricating metal interconnections, a Ni film is deposited on an insulating substrate by electroless plating, and a photoresist film is formed in a specified pattern on the Ni film. An Au film is deposited by electroless plating in a region where the Ni film is exposed and where the resist is not formed. The photoresist film is removed, and the Ni film exposed by the removal of the photoresist film is removed by etching. A Cu film is formed on the Au film by electroplating or electroless plating selectively. This method consists of only wet deposition process, involves less etching process and provides metal interconnections of low resistance.
    Type: Grant
    Filed: April 11, 2000
    Date of Patent: July 2, 2002
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshihiro Izumi, Yoshimasa Chikama
  • Publication number: 20020003048
    Abstract: A ground pattern film 12 for interconnections is formed on a glass substrate 11, and a plating film 13 is formed by selective plating on the ground pattern film 12. A taper angle &agr; which both sides of the plating film 13 form with the surface of the glass substrate 11 is made in the range of 0<&agr;<90°. This arrangement allows the formation of new metal lines on the plating film 13 without a break and allows the patterning of a new film on the plating film 13 without a remaining film.
    Type: Application
    Filed: May 25, 2001
    Publication date: January 10, 2002
    Inventors: Yoshimasa Chikama, Yoshihiro Izumi
  • Publication number: 20010048489
    Abstract: There is provided an active matrix substrate which enables to shorten a fabrication process of a pixel electrode, improve exposure precision by self alignment, and prevent leakage failures between pixel electrodes. The active matrix substrate has TFTs disposed in the shape of a matrix. On a light permeable substrate, there are formed gate signal lines and capacity lines. On a gate insulating film on the lines, there are formed in sequence a semiconductor layer, a source electrode and a drain electrode separated right and left by a channel protection layer. Thus, the TFTs are fabricated. Then, the entire substrate is covered with an interlayer insulating film. On top of the interlayer insulating film, there are formed pixel electrodes, which are connected to the TFTs through contact holes piercing through the interlayer insulating film.
    Type: Application
    Filed: May 24, 2001
    Publication date: December 6, 2001
    Inventors: Yoshihiro Izumi, Yoshimasa Chikama, Atsuhito Murai