Patents by Inventor Yoshito Ikeda

Yoshito Ikeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6774449
    Abstract: The semiconductor device of the present invention includes: a gallium nitride (GaN) compound semiconductor layer; and a Schottky electrode formed on the GaN compound semiconductor layer, wherein the Schottky electrode contains silicon.
    Type: Grant
    Filed: September 18, 2000
    Date of Patent: August 10, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Katsunori Nishii, Yoshito Ikeda, Hiroyuki Masato, Kaoru Inoue
  • Patent number: 6770922
    Abstract: A semiconductor device has a first semiconductor layer composed of a group III-V nitride, an oxide film formed by oxidizing a second semiconductor layer composed of a group III-V nitride to be located on the gate electrode formation region of the first semiconductor layer, an insulating film formed on the oxide film to have a composition different from the composition of the oxide film, and a gate electrode formed on the insulating film.
    Type: Grant
    Filed: February 26, 2003
    Date of Patent: August 3, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kaoru Inoue, Yoshito Ikeda, Yutaka Hirose, Katsunori Nishii
  • Publication number: 20040137761
    Abstract: In a method for fabricating a semiconductor device, a first semiconductor layer of aluminum gallium nitride is first formed on a substrate, and a protection film containing silicon is then formed on the first semiconductor layer in such a manner that a device-isolation region is uncovered. Thereafter, the method further includes the step of heat-treating the first semiconductor layer in an oxidizing atmosphere whose temperature is adjusted to be within a range of 950° C. or more and 1050 ° C. or less.
    Type: Application
    Filed: July 17, 2003
    Publication date: July 15, 2004
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Kaoru Inoue, Yoshito Ikeda, Katsunori Nishii, Yutaka Hirose
  • Publication number: 20040137179
    Abstract: An antiadhesive material that is excellent in biocompatibility and bioabsorbability, as well as excellent strength in suturing and bonding, is provided. A reinforcing material 12 made of a biodegradable polymer is placed in a gelatin solution so that the reinforcing material 12 is impregnated with the solution, and the gelatin is caused to gelate and dried. By so doing, an antiadhesive material in which a gelatin film 11 and the reinforcing material 12 are integrated is obtained. The reinforcing material 12 preferably is arranged in a portion of the gelatin film 11 to be subjected to suturing, and preferably is arranged along a periphery of the, gelatin film 11. The gelatin film 11 preferably is a cross-linked gelatin film, and the reinforcing material 12 preferably is a nonwoven fabric.
    Type: Application
    Filed: December 11, 2003
    Publication date: July 15, 2004
    Inventors: Shojiro Matsuda, Yoshimi Tanaka, Yoshito Ikeda
  • Publication number: 20040119003
    Abstract: An image forming apparatus is disclosed that is capable of making it simple to initialize a laser system thereof. The image forming apparatus includes a first photo detector that detects a part of a laser beam from each of the lasers and generates respective power adjustment signals for the lasers, a second photo detector that detects another part of the scanning laser beam of each of the lasers and generates a synchronization signal corresponding to each laser, and a power adjustment control unit that changes, the output power of each of the lasers to a predetermined value. During the adjustment of output powers of the lasers, the power of a laser is monitored by using the synchronization signal. The power adjustment control unit turns on a laser for power adjustment, and turns off the laser when the scanning synchronization signal is detected twice to complete the power adjustment of the laser, and then starts power adjustment of the next laser.
    Type: Application
    Filed: September 4, 2003
    Publication date: June 24, 2004
    Inventor: Yoshito Ikeda
  • Patent number: 6737683
    Abstract: A semiconductor device has an active region composed of a group III-V nitride semiconductor and ohmic electrodes and a gate electrode each formed on the active region. The active region has an entire surface thereof exposed to a plasma such that a surface potential for electrons therein is lower than in the case where the entire surface is not exposed to the plasma.
    Type: Grant
    Filed: February 25, 2003
    Date of Patent: May 18, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kaoru Inoue, Yoshito Ikeda, Yutaka Hirose, Katsunori Nishii
  • Publication number: 20040061194
    Abstract: A buffer layer, an undoped gallium nitride layer, and an n-type gallium nitride active layer are formed on a sapphire substrate. Ohmic contacts and a Schottky contact are then formed on the n-type gallium nitride active layer as a source contact, a drain contact and a gate contact, respectively. The Schottky contact is a copper alloy, such as palladium copper, in which the content by weight of copper is 5%.
    Type: Application
    Filed: June 3, 2003
    Publication date: April 1, 2004
    Inventors: Yoshito Ikeda, Kaoru Inoue, Yutaka Hirose, Katsunori Nishii
  • Publication number: 20030222276
    Abstract: An active region formed of a Group III nitride semiconductor is formed on a substrate. Then, an electrode is formed on the active region and a protective insulating film is formed on a part of the active region located in the peripheral portion of the electrode by oxidizing the Group III nitride semiconductor.
    Type: Application
    Filed: May 14, 2003
    Publication date: December 4, 2003
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Katsunori Nishii, Yoshito Ikeda, Kaoru Inoue
  • Patent number: 6654042
    Abstract: An optical writing apparatus including a semiconductor laser having plural light emitting elements and a single light-receiving element and plural semiconductor laser drive controlling devices. The plural light emitting elements in the semiconductor laser array are driven such that an optical writing operation at a same time per each of plural lines is performed. A commonly used LD drive controlling circuit drives the LD array. An output timing-determining device outputs a switch changing-over signal to either one of respective changing-over switches in a changing-over switch circuit. After an operational delay time of the changing-over switch elapses, an APC signal is output to an APC control section of the LD drive controlling circuit connected to a negative feedback loop formed by a changing-over operation of the changing-over switch circuit. After the completion of the APC operation, the outputting of the switch changing-over signal to the changing-over switch is stopped.
    Type: Grant
    Filed: November 30, 2000
    Date of Patent: November 25, 2003
    Assignee: Ricoh Company, Ltd.
    Inventor: Yoshito Ikeda
  • Publication number: 20030213975
    Abstract: A semiconductor device includes an insulating oxide layer formed by oxidizing a nitride semiconductor and an electrode formed of a conductive metal oxide on the insulating oxide layer.
    Type: Application
    Filed: April 17, 2003
    Publication date: November 20, 2003
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO, LTD.
    Inventors: Yutaka Hirose, Kaoru Inoue, Yoshito Ikeda
  • Publication number: 20030209762
    Abstract: An insulating-gate semiconductor device has a first nitride semiconductor layer formed over a substrate and an insulating oxidation layer obtained by oxidizing a second nitride semiconductor layer formed on the first nitride semiconductor layer. A gate electrode is formed on the insulating oxidation layer.
    Type: Application
    Filed: June 9, 2003
    Publication date: November 13, 2003
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Katsunori Nishii, Kaoru Inoue, Toshinobu Matsuno, Yoshito Ikeda, Hiroyuki Masato
  • Publication number: 20030205721
    Abstract: The semiconductor device of this invention includes an active region formed from a group III nitride semiconductor grown on a substrate and an insulating oxide film formed in a peripheral portion of the active region by oxidizing the group III nitride semiconductor. On the active region, a gate electrode in Schottky contact with the active region extending onto the insulating oxide film and having an extended portion on the insulating oxide film is formed, and ohmic electrodes respectively serving as a source electrode and a drain electrode are formed with space from side edges along the gate length direction of the gate electrode.
    Type: Application
    Filed: March 21, 2001
    Publication date: November 6, 2003
    Inventors: Katsunori Nishii, Kaoru Inoue, Toshinobu Matsuno, Yoshito Ikeda, Hiroyuki Masato
  • Publication number: 20030160265
    Abstract: A semiconductor device has a first semiconductor layer composed of a group III-V nitride, an oxide film formed by oxidizing a second semiconductor layer composed of a group III-V nitride to be located on the gate electrode formation region of the first semiconductor layer, an insulating film formed on the oxide film to have a composition different from the composition of the oxide film, and a gate electrode formed on the insulating film.
    Type: Application
    Filed: February 26, 2003
    Publication date: August 28, 2003
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Kaoru Inoue, Yoshito Ikeda, Yutaka Hirose, Katsunori Nishii
  • Publication number: 20030160269
    Abstract: A semiconductor device has an active region composed of a group III-V nitride semiconductor and ohmic electrodes and a gate electrode each formed on the active region. The active region has an entire surface thereof exposed to a plasma such that a surface potential for electrons therein is lower than in the case where the entire surface is not exposed to the plasma.
    Type: Application
    Filed: February 25, 2003
    Publication date: August 28, 2003
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Kaoru Inoue, Yoshito Ikeda, Yutaka Hirose, Katsunori Nishii
  • Patent number: 6593193
    Abstract: An insulating-gate semiconductor device has a first nitride semiconductor layer formed over a substrate and an insulating oxidation layer obtained by oxidizing a second nitride semiconductor layer formed on the first nitride semiconductor layer. A gate electrode is formed on the insulating oxidation layer.
    Type: Grant
    Filed: January 25, 2002
    Date of Patent: July 15, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Katsunori Nishii, Kaoru Inoue, Toshinobu Matsuno, Yoshito Ikeda, Hiroyuki Masato
  • Publication number: 20030107101
    Abstract: The semiconductor device of the present invention includes: a gallium nitride (GaN) compound semiconductor layer; and a Schottky electrode formed on the GaN compound semiconductor layer, wherein the Schottky electrode contains silicon.
    Type: Application
    Filed: December 27, 2002
    Publication date: June 12, 2003
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Katsunori Nishii, Yoshito Ikeda, Hiroyuki Masato, Kaoru Inoue
  • Publication number: 20030109088
    Abstract: The semiconductor device of the present invention includes: a gallium nitride (GaN) compound semiconductor layer; and a Schottky electrode formed on the GaN compound semiconductor layer, wherein the Schottky electrode contains silicon.
    Type: Application
    Filed: December 20, 2002
    Publication date: June 12, 2003
    Applicant: Matsushita Electronics Corporation
    Inventors: Katsunori Nishii, Yoshito Ikeda, Hiroyuki Masato, Kaoru Inoue
  • Publication number: 20030090744
    Abstract: An image forming apparatus shifts a scanning position on a surface scanned of each of a plurality of optical beams in a main scanning direction and a sub-scanning direction, and scans a plurality of lines simultaneously in the main scanning direction by a deflecting part. A synchronization detecting sensor detects the plurality of optical beams. A counting part counts a clock having a higher frequency than a dot clock in an interval between a synchronization detection point of a first beam and a synchronization detection point of a second beam, the first and second beams being included in the optical beams detected by the synchronization detecting sensor. A determining part determines a starting position of writing for each of the plurality of optical beams based on a counted value counted by the counting part.
    Type: Application
    Filed: October 25, 2002
    Publication date: May 15, 2003
    Inventor: Yoshito Ikeda
  • Patent number: 6535364
    Abstract: A magnetic resistance element is provided that includes an upper magnetic layer, which is formed in contact with an anti-ferromagnetic layer, and at least two magnetic layers that are layered with tunnel barrier wall layers respectively inserted between the first magnetic layer and each of the at least two magnetic layers such that the magnetic resistance element has a combined resistance that corresponds to one of four predefined magnetic resistances and that can be changed to another of the four predefined magnetic resistances by applying a predefined recording magnetic field pattern to the magnetic resistance element.
    Type: Grant
    Filed: January 14, 2000
    Date of Patent: March 18, 2003
    Assignee: Sony Corporation
    Inventors: Seiji Kumagai, Yoshito Ikeda, Terunobu Miyazaki, Yoshiyuki Fukumoto
  • Patent number: 6519123
    Abstract: A magnetic tunneling element in which the tunnel current flows reliably to exhibit a stable magnetic tunneling effect. The magnetic tunneling element includes a first magnetic layer, a tunnel barrier layer formed on the first magnetic layer, and a second magnetic layer formed on the tunnel barrier layer. The tunnel barrier layer is a metal film oxidized by inductively coupled oxygen plasma and a second magnetic layer is formed on the tunnel barrier layer.
    Type: Grant
    Filed: September 9, 1999
    Date of Patent: February 11, 2003
    Assignee: Sony Corporation
    Inventors: Junichi Sugawara, Eiji Nakashio, Seiji Kumagai, Yoshito Ikeda