Abstract: The present invention is related to a biodegradable high-efficiency dengue vaccine, a method for making the same, and a pharmaceutical composition comprising the same. The biodegradable high-efficiency dengue vaccine comprises a biodegradable nanocomplex with electric properties holding a dengue viral protein inside. An organism has antibody responses after vaccination with the biodegradable nanocomplex twice. Accordingly, in comparison with the Alum adjuvant and Ribi adjuvant used in the traditional dengue vaccine of the prior art, the vaccination times in the present invention is decreased to further reduce the vaccination cost, so the biodegradable high-efficiency dengue vaccine is good for being a commercial vaccine.

Abstract: A method and a system for managing cache files, adapted for a local end apparatus to manage files cached from a service end apparatus, are provided. In the method, a file is divided into a plurality of segments, and a part of the segments are downloaded from the service end apparatus and stored in the local end apparatus. Then, the segments of the file to be downloaded are increased or decreased according to a utility rate of the file.

Abstract: A method for manufacturing thin film solar cells, includes forming a light permeable first electrode layer in the back light surface of a glass substrate, and formed in the first electrode layer a plurality of first openings for exposing a part of the back light surface therefrom; forming a photoelectric conversion layer on the first electrode layer and the exposed back light surface, and forming a plurality of second openings in the photoelectric conversion layer for exposing a part of the first electrode layer therefrom; and forming a glistening second electrode layer having a plurality of third openings formed therein, wherein the second electrode layer comprises a conductive colloid comprised of non-diffractive fillings and polymeric base material.

Abstract: A manufacturing method of an array substrate includes the following steps. A first conductive layer, a gate insulating layer, a semiconductor layer, an etching stop layer, and a first patterned photoresist are successively formed on a substrate. The etching stop layer and the semiconductor layer uncovered by the first patterned photoresist are then removed by a first etching process. A patterned gate insulating layer and a patterned etching stop layer are then formed through a second etching process. The first conductive layer uncovered by the patterned gate insulating layer is then removed to form a gate electrode. The semiconductor layer uncovered by the patterned etching stop layer is then removed to form a patterned semiconductor layer and partially expose the patterned gate insulating layer.

Abstract: A manufacturing method of an array substrate includes the following steps. A first conductive layer, a gate insulating layer, a semiconductor layer, an etching stop layer, and a first patterned photoresist are successively formed on a substrate. The etching stop layer and the semiconductor layer uncovered by the first patterned photoresist are then removed by a first etching process. A patterned gate insulating layer and a patterned etching stop layer are then formed through a second etching process. The first conductive layer uncovered by the patterned gate insulating layer is then removed to form a gate electrode. The semiconductor layer uncovered by the patterned etching stop layer is then removed to form a patterned semiconductor layer and partially expose the patterned gate insulating layer.

Abstract: A manufacturing method for a Zinc Oxide (ZnO) piezoelectric thin-film with high C-axis orientation comprises the steps of providing a substrate having a base, a SiO2 layer and a Si3N4 layer; forming a bottom electrode layer on the Si3N4 layer; patterning the bottom electrode layer; sputtering a Zinc Oxide layer on the Si3N4 layer and the bottom electrode layer; forming a photoresist layer on the Si3N4 layer and the Zinc Oxide layer; patterning the photoresist layer to reveal the Zinc Oxide layer; forming a top electrode layer on the Zinc Oxide layer and the photoresist layer; removing the photoresist layer and the top electrode layer formed on the photoresist layer, and the top electrode layer formed on the Zinc Oxide layer can be remained; and patterning the Si3N4 layer to form a recess that reveals the base of the substrate.

Abstract: A manufacturing method of an array substrate includes the following steps. A first conductive layer, a gate insulating layer, a semiconductor layer, an etching stop layer, and a first patterned photoresist are successively formed on a substrate. The etching stop layer and the semiconductor layer uncovered by the first patterned photoresist are then removed by a first etching process. A patterned gate insulating layer and a patterned etching stop layer are then formed through a second etching process. The first conductive layer uncovered by the patterned gate insulating layer is then removed to form a gate electrode. The semiconductor layer uncovered by the patterned etching stop layer is then removed to form a patterned semiconductor layer and partially expose the patterned gate insulating layer.

Abstract: A method for manufacturing a P-I-N microcrystalline silicon structure for thin-film solar cells, includes the steps of: (a) forming a P-type layer; (b) forming an I-type layer including a plurality of sub-layers successively stacked on the P-type layer using gas mixtures including fluoride and hydride that have different gas ratios, respectively; and (c) forming an N-type layer on the I-type layer. First, second, and third I-type sub-layers may be formed on the P-type layer using gas mixtures including fluoride and hydride at a first, second, and third gas ratios, respectively. Then, advantageously, the third gas ratio may be larger than the second gas ratio and the second gas ratio may be larger than the first gas ratio, and the first gas ratio may be 8%, the second gas ratio may range between 15% and 35%, and the third gas ratio may range between 35% and 50%.

Abstract: A method for manufacturing a P-I-N microcrystalline silicon structure for thin-film solar cells, includes the steps of: (a) forming a P-type layer; (b) forming an I-type layer including a plurality of sub-layers successively stacked on the P-type layer using gas mixtures including fluoride and hydride that have different gas ratios, respectively; and (c) forming an N-type layer on the I-type layer. First, second, and third I-type sub-layers may be formed on the P-type layer using gas mixtures including fluoride and hydride at a first, second, and third gas ratios, respectively. Then, advantageously, the third gas ratio may be larger than the second gas ratio and the second gas ratio may be larger than the first gas ratio, and the first gas ratio may be 8%, the second gas ratio may range between 15% and 35%, and the third gas ratio may range between 35% and 50%.

Abstract: A manufacturing method of an array substrate includes the following steps. A gate electrode and a gate insulator layer are successively formed on a substrate. A semiconductor layer, an etching stop layer, a hard mask layer, and a second patterned photoresist are successively formed on the gate insulator layer. The second patterned photoresist is employed for performing an over etching process to the hard mask layer to form a patterned hard mask layer. The second patterned photoresist is employed for performing a first etching process to the etching stop layer. The second patterned photoresist is then employed for performing a second etching process to the semiconductor layer to form a patterned semiconductor layer. The etching stop layer uncovered by the patterned hard mask layer is then removed for forming a patterned etching stop layer.

Abstract: A method for manufacturing thin film solar cells, includes forming a light permeable first electrode layer in the back light surface of a glass substrate, and formed in the first electrode layer a plurality of first openings for exposing a part of the back light surface therefrom; forming a photoelectric conversion layer on the first electrode layer and the exposed back light surface, and forming a plurality of second openings in the photoelectric conversion layer for exposing a part of the first electrode layer therefrom; and forming a glistening second electrode layer having a plurality of third openings formed therein, wherein the second electrode layer comprises a conductive colloid comprised of non-diffractive fillings and polymeric base material.

Abstract: A manufacturing method for a Zinc Oxide (ZnO) piezoelectric thin-film with high C-axis orientation comprises the steps of providing a substrate having a base, a SiO2 layer and a Si3N4 layer; forming a bottom electrode layer on the Si3N4 layer; patterning the bottom electrode layer; sputtering a Zinc Oxide layer on the Si3N4 layer and the bottom electrode layer; forming a photoresist layer on the Si3N4 layer and the Zinc Oxide layer; patterning the photoresist layer to reveal the Zinc Oxide layer; forming a top electrode layer on the Zinc Oxide layer and the photoresist layer; removing the photoresist layer and the top electrode layer formed on the photoresist layer, and the top electrode layer formed on the Zinc Oxide layer can be remained; and patterning the Si3N4 layer to form a recess that reveals the base of the substrate.

Abstract: The prevent disclosure discloses a structure of thermal resistive layer and the method of forming the same. The thermal resistive structures, formed on a plastic substrate, comprises a porous layer, formed on said plastic substrate, including a plurality of oxides of hollow structure, and a buffer layer, formed on said porous layer, wherein said porous layer can protect said plastic substrate from damage caused by the heat generated during manufacturing process. With the structure and method disclosed above, making a thin film transistor and forming electronic devices on the plastic substrate in the technology of Low Temperature PolySilicon, i.e. LTPS, without changing any parameters is possible.

Abstract: An electrostatic discharge guide using metal sputtering process and modifying plastic case is applied to an electronic device. The plastic case and a metal case are laminated. The plastic case is defined with a tip portion spaced from the metal case on side wall thereof. A conductive layer formed on the surface of the plastic case opposite to the metal case extends to the tip of the tip portion, and is electrically connected to a ground of the electronic device. Therefore, when electrostatic charges accumulated on the metal case exceed a specific value, the static electricity is discharged to the ground of the electronic device based on the point discharge principle, instead of causing an electric shock to a user.

Abstract: The prevent invention discloses a structure of thermal resistive layer and the method of forming the same. The thermal resistive structures, formed on a plastic substrate, comprises a porous layer, formed on said plastic substrate, including a plurality of oxides of hollow structure, and a buffer layer, formed on said porous layer, wherein said porous layer can protect said plastic substrate from damage caused by the heat generated during manufacturing process. With the structure and method disclosed above, making a thin film transistor and forming electronic devices on the plastic substrate in the technology of Low Temperature PolySilicon, i.e. LTPS, without changing any parameters is easy to carry out.

Abstract: An electrostatic guiding structure with metal oxide generated through anodic oxidation includes a metallic case, an oxide layer, a system ground layer, and at least one conductor. The metallic case has an accommodating space, and the system ground layer and the conductor are both located in the accommodating space. The metallic case has an oxide layer formed on a surface thereof after an anode processing. The conductor is electrically connected to the oxide layer on an inner surface of the metallic case and the system ground layer, such that the static electricity is released from the metallic case to the system ground layer.

Abstract: An electronic device with an electrostatic guiding structure includes a metal case, a plastic case overlapping the metal case, a conductive strip, and an electrically insulating strip. The conductive strip is electrically connected to a conductive region of the plastic case, and has at least one tip portion. An end point of the tip portion is located at an edge of the electrically insulating strip, and separated from the metal case with the electrically insulating strip. The conductive region is electrically connected to a ground region of an electronic module. Therefore, when electrostatic charges accumulated in the metal case is above a specific value, the electrostatic charges are discharged to the ground region of the electronic module according to point discharge principle, thereby protecting user of the electronic device from getting an electric shock.

Abstract: In a method for fabricating a flexible pixel array substrate, first, a release layer is formed on a rigid substrate. Next, on the release layer, a polymer film is formed, the adhesive strength between the rigid substrate and the release layer being higher than that between the release layer and the polymer film. The polymer film is formed by spin coating a polymer monomer and performing a curing process to form a polymer layer. Afterwards, a pixel array is formed on the polymer film. The polymer film with the pixel array formed thereon is separated from the rigid substrate.

Abstract: The prevent invention discloses a structure of thermal resistive layer and the method of forming the same. The thermal resistive structures, formed on a plastic substrate, comprises a porous layer, formed on said plastic substrate, including a plurality of oxides of hollow structure, and a buffer layer, formed on said porous layer, wherein said porous layer can protect said plastic substrate from damage caused by the heat generated during manufacturing process. With the structure and method disclosed above, making a thin film transistor and forming electronic devices on the plastic substrate in the technology of Low Temperature PolySilicon, i.e. LTPS, without changing any parameters is easy to carry out.

Abstract: An electronic device with an electrostatic guiding structure includes a metal case, a plastic case overlapping the metal case, a conductive strip, and an electrically insulating strip. The conductive strip is electrically connected to a conductive region of the plastic case, and has at least one tip portion. An end point of the tip portion is located at an edge of the electrically insulating strip, and separated from the metal case with the electrically insulating strip. The conductive region is electrically connected to a ground region of an electronic module. Therefore, when electrostatic charges accumulated in the metal case is above a specific value, the electrostatic charges are discharged to the ground region of the electronic module according to point discharge principle, thereby protecting user of the electronic device from getting an electric shock.