Patents by Inventor Yu Kou
Yu Kou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11349689Abstract: A receiver for data recovery from a channel signal of a communications channel. The receiver includes a quantization circuit to generate a quantized code corresponding to the channel signal. A first decision circuit recovers, in a first signal processing mode, digital data for the channel signal based on the quantized representation of the channel signal. A second decision circuit recovers, in a second signal processing mode, the digital data for the channel signal based on the quantized representation of the channel signal. A controller selects between the first signal processing mode and the second signal processing mode based on a parameter indicative of a signal quality of the channel signal.Type: GrantFiled: May 1, 2020Date of Patent: May 31, 2022Assignee: eTopus Technology Inc.Inventors: Kai Keung Chan, Danfeng Xu, Yu Kou
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Publication number: 20210216086Abstract: A method and an apparatus for planning an obstacle-free measurement trajectory of a coordinate measuring machine, and a computer program are provided. An original measurement trajectory is determined, all compact obstacles along the original measurement trajectory are determined, an obstacle entrance pose on the original measurement trajectory and an obstacle exit pose on the original measurement trajectory are determined for each compact obstacle, and at least one obstacle-free alternative measurement trajectory is determined for each compact obstacle.Type: ApplicationFiled: January 13, 2021Publication date: July 15, 2021Inventor: Yu Kou
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Publication number: 20200259684Abstract: A receiver for data recovery from a channel signal of a communications channel. The receiver includes a quantization circuit to generate a quantized code corresponding to the channel signal. A first decision circuit recovers, in a first signal processing mode, digital data for the channel signal based on the quantized representation of the channel signal. A second decision circuit recovers, in a second signal processing mode, the digital data for the channel signal based on the quantized representation of the channel signal. A controller selects between the first signal processing mode and the second signal processing mode based on a parameter indicative of a signal quality of the channel signal.Type: ApplicationFiled: May 1, 2020Publication date: August 13, 2020Inventors: Kai Keung Chan, Danfeng Xu, Yu Kou
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Patent number: 10680857Abstract: A receiver for data recovery from a channel signal of a communications channel. The receiver includes a quantization circuit to generate a quantized code corresponding to the channel signal. A first decision circuit recovers, in a first signal processing mode, digital data for the channel signal based on the quantized representation of the channel signal. A second decision circuit recovers, in a second signal processing mode, the digital data for the channel signal based on the quantized representation of the channel signal. A controller selects between the first signal processing mode and the second signal processing mode based on a parameter indicative of a signal quality of the channel signal.Type: GrantFiled: March 5, 2019Date of Patent: June 9, 2020Assignee: eTopus Technology Inc.Inventors: Kai Keung Chan, Danfeng Xu, Yu Kou
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Publication number: 20190207787Abstract: A receiver for data recovery from a channel signal of a communications channel. The receiver includes a quantization circuit to generate a quantized code corresponding to the channel signal. A first decision circuit recovers, in a first signal processing mode, digital data for the channel signal based on the quantized representation of the channel signal. A second decision circuit recovers, in a second signal processing mode, the digital data for the channel signal based on the quantized representation of the channel signal. A controller selects between the first signal processing mode and the second signal processing mode based on a parameter indicative of a signal quality of the channel signal.Type: ApplicationFiled: March 5, 2019Publication date: July 4, 2019Inventors: Kai Keung Chan, Danfeng Xu, Yu Kou
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Patent number: 10270627Abstract: A receiver for data recovery from a channel signal of a communications channel. The receiver includes a quantization circuit to generate a quantized code corresponding to the channel signal. A first decision circuit recovers, in a first signal processing mode, digital data for the channel signal based on the quantized representation of the channel signal. A second decision circuit recovers, in a second signal processing mode, the digital data for the channel signal based on the quantized representation of the channel signal. A controller selects between the first signal processing mode and the second signal processing mode based on a parameter indicative of a signal quality of the channel signal.Type: GrantFiled: March 14, 2016Date of Patent: April 23, 2019Assignee: eTopus Technology Inc.Inventors: Kai Keung Chan, Danfeng Xu, Yu Kou
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Patent number: 9875157Abstract: A storage system includes a channel detector, an LDPC decoder, and an erasure block. The channel detector is configured to receive data corresponding to data read from a storage and output an LLR signal. The LDPC decoder is configured to receive the LLR signal and output a feedback signal to the channel detector. The erasure block is configured to erase at a portion of at least one of the LLR signal and the feedback signal. A method for testing includes generating an error rate function corresponding to an erasure pattern. The function is a function of a number of LDPC iterations. The method includes determining testing parameters at least in part based on the error rate function, wherein the testing parameters comprise a testing number of LDPC iterations, a passing error rate, and the erasure pattern. The method includes testing storage devices using the testing parameters.Type: GrantFiled: June 6, 2014Date of Patent: January 23, 2018Assignee: SK Hynix Memory Solutions Inc.Inventors: Yu Kou, Lingqi Zeng, Jason Bellorado, Marcus Marrow
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Patent number: 9780796Abstract: A receiver having analog to digital converters with phase adjustable sampling clocks. A first analog to digital converter converts an analog signal into first digital samples under control of a first sampling clock. A first clock generator adjusts a phase of the first sampling clock based on at least one first phase control signal. A second analog to digital converter converts the analog signal into second digital samples under control of a second sampling clock. A second clock generator adjusts the phase of the second sampling clock based on at least one second phase control signal. A data decision circuit recovers data based on the first and second samples. Feedback circuitry receives the recovered data and generates at least one first phase control signal for the first clock generator and generates at least one second phase control signal for the second clock generator based on the first phase control signal.Type: GrantFiled: September 20, 2016Date of Patent: October 3, 2017Assignee: eTopus Technology Inc.Inventor: Yu Kou
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Patent number: 9742422Abstract: A receiver having an analog to digital converter with adjustable reference voltages that are calibrated to account for process variations. The receiver comprises an analog to digital converter. The analog to digital converter includes a reference generator to generate a set of N reference voltages. The reference generator adjusts voltage levels of the set of N reference voltages based on one or more control signals. A plurality of comparators compare an input signal to the set of N reference voltages. A calibration circuit generates the one or more control signals for adjusting the voltage levels of the N reference voltages based on outputs of the comparators.Type: GrantFiled: June 15, 2016Date of Patent: August 22, 2017Assignee: eTopus Technology Inc.Inventors: Danfeng Xu, Kai Keung Chan, Yu Kou
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Patent number: 9705531Abstract: A multi-mode viterbi decoder supporting different decoding modes. The viterbi decoder comprises circuitry to output one or more data symbol values. The circuitry sets the one or more data symbol values to a first quantity of unit intervals in a first decoding mode (e.g. PAM-4). The circuitry sets the one or more data symbol values to a second quantity of unit intervals in a second decoding mode (e.g. NRZ). The second quantity of unit intervals is greater than the first quantity of unit intervals. A branch metric circuit is adapted to, in the first decoding mode, generate a set of viterbi branch metrics based on the data symbol values for the first quantity of unit intervals. The branch metric circuit is adapted to, in the second decoding mode, generate the set of viterbi branch metrics based on the data symbol values for the second quantity of unit intervals.Type: GrantFiled: February 18, 2015Date of Patent: July 11, 2017Assignee: eTopus Technology Inc.Inventors: Kai Keung Chan, Yu Kou, Tze Yin Cheung, Danfeng Xu
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Publication number: 20170012630Abstract: A receiver having analog to digital converters with phase adjustable sampling clocks. A first analog to digital converter converts an analog signal into first digital samples under control of a first sampling clock. A first clock generator adjusts a phase of the first sampling clock based on at least one first phase control signal. A second analog to digital converter converts the analog signal into second digital samples under control of a second sampling clock. A second clock generator adjusts the phase of the second sampling clock based on at least one second phase control signal. A data decision circuit recovers data based on the first and second samples. Feedback circuitry receives the recovered data and generates at least one first phase control signal for the first clock generator and generates at least one second phase control signal for the second clock generator based on the first phase control signal.Type: ApplicationFiled: September 20, 2016Publication date: January 12, 2017Inventor: Yu Kou
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Publication number: 20160301420Abstract: A receiver having an analog to digital converter with adjustable reference voltages that are calibrated to account for process variations. The receiver comprises an analog to digital converter. The analog to digital converter includes a reference generator to generate a set of N reference voltages. The reference generator adjusts voltage levels of the set of N reference voltages based on one or more control signals. A plurality of comparators compare an input signal to the set of N reference voltages. A calibration circuit generates the one or more control signals for adjusting the voltage levels of the N reference voltages based on outputs of the comparators.Type: ApplicationFiled: June 15, 2016Publication date: October 13, 2016Inventors: Danfeng Xu, Kai Keung Chan, Yu Kou
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Patent number: 9461654Abstract: A receiver having analog to digital converters with phase adjustable sampling clocks. A first analog to digital converter converts an analog signal into first digital samples under control of a first sampling clock. A first clock generator adjusts a phase of the first sampling clock based on at least one first phase control signal. A second analog to digital converter converts the analog signal into second digital samples under control of a second sampling clock. A second clock generator adjusts the phase of the second sampling clock based on at least one second phase control signal. A data decision circuit recovers data based on the first and second samples. Feedback circuitry receives the recovered data and generates at least one first phase control signal for the first clock generator and generates at least one second phase control signal for the second clock generator based on the first phase control signal.Type: GrantFiled: June 1, 2015Date of Patent: October 4, 2016Assignee: eTopus Technology Inc.Inventor: Yu Kou
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Patent number: 9425950Abstract: A receiver for high speed communications. The receiver includes an analog to digital converter to convert an analog input signal into at least one digital input signal at timings controlled by a sampling clock. A finite impulse response filter generates at least one filtered input signal based on the digital input signal. A data decision circuit recovers data based on the filtered input signal. The filtered input signal and the recovered data can be provided to a feedback loop to determine a timing error of the sampling clock, which is then used to generate the sampling clock.Type: GrantFiled: December 16, 2014Date of Patent: August 23, 2016Assignee: eTopus Technology Inc.Inventor: Yu Kou
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Publication number: 20160241274Abstract: A multi-mode viterbi decoder supporting different decoding modes. The viterbi decoder comprises circuitry to output one or more data symbol values. The circuitry sets the one or more data symbol values to a first quantity of unit intervals in a first decoding mode (e.g. PAM-4). The circuitry sets the one or more data symbol values to a second quantity of unit intervals in a second decoding mode (e.g. NRZ). The second quantity of unit intervals is greater than the first quantity of unit intervals. A branch metric circuit is adapted to, in the first decoding mode, generate a set of viterbi branch metrics based on the data symbol values for the first quantity of unit intervals. The branch metric circuit is adapted to, in the second decoding mode, generate the set of viterbi branch metrics based on the data symbol values for the second quantity of unit intervals.Type: ApplicationFiled: February 18, 2015Publication date: August 18, 2016Inventors: Kai Keung Chan, Yu Kou, Tze Yin Cheung, Danfeng Xu
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Patent number: 9407295Abstract: Aspects of the disclosure pertain to a system and method for providing component detector switching for a diversity loop detector. Switching between component detectors is performed via one of: a periodic state likelihood reset process, a slope-based switching process, or a cross-over connection process. The joint decision circuit switches among component detectors to promote improved performance with present of constant or transition phase offset.Type: GrantFiled: January 15, 2013Date of Patent: August 2, 2016Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Yang Han, Yu Kou, Xuebin Wu, Bruce A. Wilson
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Patent number: 9397680Abstract: A receiver having an analog to digital converter with adjustable reference voltages that are calibrated to account for process variations. The receiver comprises an analog to digital converter. The analog to digital converter includes a reference generator to generate a set of N reference voltages. The reference generator adjusts voltage levels of the set of N reference voltages based on one or more control signals. A plurality of comparators compare an input signal to the set of N reference voltages. A calibration circuit generates the one or more control signals for adjusting the voltage levels of the N reference voltages based on outputs of the comparators.Type: GrantFiled: October 31, 2014Date of Patent: July 19, 2016Assignee: eTopus Technology Inc.Inventors: Danfeng Xu, Kai Keung Chan, Yu Kou
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Publication number: 20160197702Abstract: A receiver for data recovery from a channel signal of a communications channel. The receiver includes a quantization circuit to generate a quantized code corresponding to the channel signal. A first decision circuit recovers, in a first signal processing mode, digital data for the channel signal based on the quantized representation of the channel signal. A second decision circuit recovers, in a second signal processing mode, the digital data for the channel signal based on the quantized representation of the channel signal. A controller selects between the first signal processing mode and the second signal processing mode based on a parameter indicative of a signal quality of the channel signal.Type: ApplicationFiled: March 14, 2016Publication date: July 7, 2016Inventors: Kai Keung Chan, Danfeng Xu, Yu Kou
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Publication number: 20160173271Abstract: A receiver for high speed communications. The receiver includes an analog to digital converter to convert an analog input signal into at least one digital input signal at timings controlled by a sampling clock. A finite impulse response filter generates at least one filtered input signal based on the digital input signal. A data decision circuit recovers data based on the filtered input signal. The filtered input signal and the recovered data can be provided to a feedback loop to determine a timing error of the sampling clock, which is then used to generate the sampling clock.Type: ApplicationFiled: December 16, 2014Publication date: June 16, 2016Inventor: Yu Kou
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Patent number: 9368233Abstract: An amount of time and an error rate function are received, where the error rate function defines a relationship between a number of iterations associated with iterative decoding and an error rate. A testing error rate is determined based at least in part on the amount of time. The number of iterations which corresponds to the testing error rate in the error rate function is selected to be a testing number of iterations; the testing error rate and the testing number of iterations are associated with testing storage media using iterative decoding.Type: GrantFiled: July 17, 2014Date of Patent: June 14, 2016Assignee: SK Hynix Memory Solutions Inc.Inventors: Yu Kou, Lingqi Zeng