Patents by Inventor Yu Kou

Yu Kou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8321750
    Abstract: RLL encoding is performed to generate RLL data, including by: using a first run-length constraint and using a second run-length constraint. G is a maximum number of zeroes between two ones, I is a maximum number of zeroes between two ones in either a first subsequence or a second subsequence where the first subsequence includes odd bits associated with a DC-balanced sequence and the second subsequence includes even bits associated with the DC-balanced sequence, and S is a number of bits per symbol associated with a systematic ECC. The RLL data is encoded using the systematic ECC to obtain ECC data which includes one or more data symbols and one or more parity symbols. The data symbols and the parity symbols are interleaved.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: November 27, 2012
    Assignee: Link—A—Media Devices Corporation
    Inventor: Yu Kou
  • Patent number: 8281224
    Abstract: Data is processed by obtaining data and redundant information from an expected position in a channel. Soft position information associated with the data is obtained and error correction decoding is performed using the data, the redundant information, and the soft position information to obtain a decoded position and decoded data. It is determined if the decoded position matches the expected position and the decoded data is output in the event the decoded position matches the expected position.
    Type: Grant
    Filed: July 24, 2009
    Date of Patent: October 2, 2012
    Assignee: Link—A—Media Devices Corporation
    Inventors: Yu Kou, Lingqi Zeng, Kin Man Ng, Kwok W. Yeung
  • Publication number: 20120246536
    Abstract: A cost function is obtained. For each of a plurality of groups of check nodes associated with low-density parity-check (LDPC) encoded data, the cost function is evaluated using information associated with a variable node and/or information associated with a check node. One of the groups of check nodes is selecting based at least in part on the evaluated cost functions. Error correction decoding related processing is performed on the selected group of check nodes.
    Type: Application
    Filed: June 7, 2012
    Publication date: September 27, 2012
    Applicant: Link_A_Media Devices Corporation
    Inventors: Kin Man Ng, Lingqi Zeng, Yu Kou, Kwok W. Yeung
  • Patent number: 8266497
    Abstract: A technique for tested is disclosed herein. A low-density parity-check (LDPC) code is received. For the received LDPC code, an error rate function is generated that is a function of a number of iterations. A number of test iterations and a passing error rate are determined using the error rate function. One or more storage media are tested using the LDPC code, the number of test iterations, and the passing error rate.
    Type: Grant
    Filed: May 5, 2009
    Date of Patent: September 11, 2012
    Assignee: Link—A—Media Devices Corporation
    Inventors: Yu Kou, Lingqi Zeng
  • Patent number: 8219873
    Abstract: Data is decoded by obtaining a cost function. For each of a plurality of groups of check nodes associated with low-density parity-check (LDPC) encoded data, the cost function is evaluated using information associated with a variable node and/or information associated with a check node. One of the groups of check nodes is selecting based at least in part on the evaluated cost functions. Processing related to error correction decoding is performed on the selected group of check nodes.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: July 10, 2012
    Assignee: Link—A—Media Devices Corporation
    Inventors: Kin Man Ng, Lingqi Zeng, Yu Kou, Kwok W. Yeung
  • Publication number: 20120166912
    Abstract: RLL encoding is performed to generate RLL data, including by: using a first run-length constraint and using a second run-length constraint. G is a maximum number of zeroes between two ones, I is a maximum number of zeroes between two ones in either a first subsequence or a second subsequence where the first subsequence includes odd bits associated with a DC-balanced sequence and the second subsequence includes even bits associated with the DC-balanced sequence, and S is a number of bits per symbol associated with a systematic ECC. The RLL data is encoded using the systematic ECC to obtain ECC data which includes one or more data symbols and one or more parity symbols. The data symbols and the parity symbols are interleaved.
    Type: Application
    Filed: March 2, 2012
    Publication date: June 28, 2012
    Applicant: LINK_A_MEDIA DEVICES CORPORATION
    Inventor: Yu Kou
  • Patent number: 8161347
    Abstract: A method of satisfying a specified run length constraint is disclosed. A systematically error correction encoded sequence of received symbols is received, wherein the received symbols include data symbols and parity symbols. The parity symbols are interleaved with the data symbols to produce interleaved symbols that satisfy the specified run length constraint.
    Type: Grant
    Filed: April 12, 2007
    Date of Patent: April 17, 2012
    Assignee: Link—A—Media Devices Corporation
    Inventor: Yu Kou
  • Publication number: 20110252294
    Abstract: A method for decoding data is disclosed. The method includes partitioning a low-density parity check (LDPC) matrix into a plurality of groups, each comprising one or more check node layers. The method further includes selecting one of the groups based at least in part on a cost function, the cost function based at least in part on information associated with a variable node, or information associated with a check node, or both. The method further includes performing LDPC layered decoding on the selected group.
    Type: Application
    Filed: April 11, 2011
    Publication date: October 13, 2011
    Applicant: LINK_A_MEDIA DEVICES CORPORATION
    Inventors: Kin Man Ng, Kwok W. Yeung, Lingqi Zeng, Yu Kou, Aditi R. Ganesan
  • Publication number: 20110208981
    Abstract: A current limiting and averaging circuit for driving a peripheral core circuit with a lower limit current value in response to a supply signal, includes a current limiting module, an energy storage module, and a converter module. The current limiting module provides a limited supply signal whose current value is smaller than or equal to an upper limit value according to the supply signal. The energy storage module stores a storage signal according to the limited supply signal when the upper limit value is higher than the lower limit current value and provides a discharge signal according to the storage signal when the upper limit value is lower than the lower limit current value. The converter module provides a driving signal for driving the peripheral core circuit in response to the limited supply signal or the limited supply signal and the discharge signal.
    Type: Application
    Filed: September 1, 2010
    Publication date: August 25, 2011
    Applicant: QUANTA COMPUTER INC.
    Inventors: Fang-Yu Kou, Jui-Hui Lin, Jui-I Wu, Hung-Jen Hou
  • Publication number: 20110191653
    Abstract: In processing quasi-cyclic low-density parity-check (QC-LDPC) data, an input signal is received which includes decision and reliability information corresponding to unpadded data. Decision and reliability information corresponding to padded data is introduced into the input signal. Message passing is performed one or more times to obtain decoded data. This includes using (1) the decision and reliability information corresponding to the unpadded data and (2) the decision and reliability information corresponding to the padded data, where a preference is given to the decision and reliability information corresponding to the padded data over the decision and reliability information corresponding to the padded data during message passing. Zero padding is removed from the decoded data.
    Type: Application
    Filed: February 25, 2011
    Publication date: August 4, 2011
    Applicant: LINK_A_MEDIA DEVICES CORPORATION
    Inventors: Lingqi Zeng, Yu Kou, Kin Man Ng, Kwok W. Yeung
  • Publication number: 20110185264
    Abstract: It is decided whether to adjust data associated with a decoder. In the event it is decided to adjust the data associated with the decoder, the data is adjusted to obtain adjusted data and decoding is performed using the decoder and the adjusted data. In the event it is decided to not adjust the data associated with the decoder, decoding is performed using the decoder and the data associated with the decoder.
    Type: Application
    Filed: November 23, 2010
    Publication date: July 28, 2011
    Applicant: LINK_A_MEDIA DEVICES CORPORATION
    Inventors: Lingqi Zeng, Yu Kou
  • Patent number: 7613988
    Abstract: Processing Reed Solomon data is disclosed. A scratch polynomial having a degree is obtained using an inversionless Berlekamp-Massey process. The degree of the scratch polynomial is limited. A magnitude of an error associated with the Reed Solomon data is determined based at least in part on information associated with the degree limited scratch polynomial. In some embodiments, determining the magnitude of an error using the degree limited scratch polynomial enables a smaller device.
    Type: Grant
    Filed: October 18, 2005
    Date of Patent: November 3, 2009
    Assignee: Link—A—Media Devices Corporation
    Inventors: Yingquan Wu, Yu Kou
  • Patent number: 7526019
    Abstract: A system for providing multi-channel multi-mode QAM equalization and carrier recovery is provided. According to one exemplary embodiment, the system includes an equalization circuit and a carrier recovery circuit operating in a concurrent manner to provide equalization and carrier recovery. The equalization circuit and the carrier recovery circuit each have two operating modes, namely, an acquisition mode and a tracking mode. The carrier recovery circuit evaluates a phase detection error calculated based on signals obtained from the equalization circuit. Based on the evaluation of the phase detection error, the equalization circuit and the carrier recovery circuit are respectively directed to switch operating mode, if appropriate.
    Type: Grant
    Filed: March 27, 2003
    Date of Patent: April 28, 2009
    Assignee: Broadlogic Network Technologies Inc.
    Inventors: Vladimir Radionov, Bin-Fan Liu, Yu Kou
  • Patent number: 7388932
    Abstract: An improved multi-channel demodulator is provided. The improved demodulator includes an automatic gain control, a data buffer and a demodulation engine. Data from various RF channels are processed by the automatic gain control in order to keep the data at their respective constant levels. Output from the automatic gain control is passed to the data buffer for storage. Corresponding data from a selected channel is then processed by the demodulation engine. The improved demodulator is able to operate in any one of three operating modes, namely, a data processing mode, a channel switching mode and a waiting mode. In the data processing mode, the demodulation engine processes the channel data that is currently loaded into the demodulation engine. In the channel switching mode, the demodulation engine stores the current channel data into the data buffer and retrieves and loads channel data from another channel for processing.
    Type: Grant
    Filed: December 30, 2002
    Date of Patent: June 17, 2008
    Assignee: Broadlogic Network Technologies, Inc.
    Inventors: WeiMin Zhang, Vladimir Radionov, Roger Stenerson, Bin-Fan Liu, Yu Kou
  • Publication number: 20080123316
    Abstract: An electromagnetic interference shielding apparatus for a signal transceiver employs two folded-edge mechanisms coupled together and an adhesive. The electromagnetic interference shielding apparatus includes a metal cover, a chassis having a waveguide output hole, and an adhesive. A first combination portion having a first curved section is disposed on an edge of the metal cover. A second combination portion having a second curved section corresponding to the first combination portion is disposed on an edge of the chassis. The adhesive is used to combine the first combination portion and the second combination portion. The waveguide output hole outputs a signal transmitted by the signal transceiver. The first combination portion and the second combination portion form a curved space that is used with the adhesive to prevent leakage of the transmitted signal and the interference of external noises.
    Type: Application
    Filed: August 30, 2007
    Publication date: May 29, 2008
    Applicant: MICROELECTRONICS TECHNOLOGY INC.
    Inventors: Ruei Yuen Chen, Fang Yu Kou, Yi Hsiang Huang
  • Publication number: 20060117042
    Abstract: A collaboration system and method via computer is provided. The collaboration system comprises a computing platform for storing an identifier, address and other information associated with at least one object; at least one service connector for communicating with a service using the identifier, address of the at least one object to interact with the service for the information associated with the object and transfer the information to the computing platform; and at least one tool for communicating with the computing platform to exchange the information associated with the object. According to the present invention, a tool may display the current information of a remote object. The tool does not necessarily have the capability to communicate with different remote services. Therefore, user might concentrate on the collaboration object and tools.
    Type: Application
    Filed: November 29, 2005
    Publication date: June 1, 2006
    Inventors: Xiao Hu, Yu Kou, Yue Ma
  • Publication number: 20010003606
    Abstract: A method for improving the stability of an anti-reflection coating layer is provided. The anti-reflection coating layer covered by a SiOxNy layer is provided. A surface treatment step is performed with an oxidizer-based plasma on the SiOxNy layer to form an oxide layer. The oxidizer-based plasma comprises O2, and N2O.
    Type: Application
    Filed: June 4, 1999
    Publication date: June 14, 2001
    Inventors: HUNG-YU KOU, BRIAN WANG
  • Patent number: 6184115
    Abstract: The present invention is directed towards a method of fabricating a self-aligned silicide on gate electrode and source/drain region of a semiconductor device. A semiconductor substrate having gate oxide layer and polysilicon layer is provided. Next, a first silicide layer is formed on polysilicon layer. The substrate is patterned and then, etched to form a gate structure. A spacer is formed on the sidewall of the gate structure and source/drain region is formed adjacent thereto. A metal layer is covered on the surface of the substrate. The substrate is performed a thermal process to convert the portion of the metal layer on gate structure and source/drain region into self-aligned silicide.
    Type: Grant
    Filed: February 16, 1999
    Date of Patent: February 6, 2001
    Assignee: United Semiconductor Corp.
    Inventors: Hung-Yu Kou, Chih-Ching Hsu