Patents by Inventor Yu Kou
Yu Kou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140140384Abstract: A method for reducing a number of bits for representing a value is disclosed. A first value represented with a first number of bits is transformed to a second value represented with a second number of bits, wherein the first number of bits is greater than the second number of bits. The transformed second value is scaled by a scale factor to a third value. Transforming includes selecting a target window with a width of a third number of bits, wherein the third number of bits is smaller than the first number of bits. Transforming further includes saturating the first value to a most significant bit (MSB) within the selected target window and extracting bits within the selected target window from the saturated value.Type: ApplicationFiled: November 6, 2013Publication date: May 22, 2014Applicant: SK hynix memory solutions inc.Inventors: Yu Kou, Lingqi Zeng
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Publication number: 20140122965Abstract: Second interleaved data is de-interleaved using a second interleaving mapping to obtain encoded data. The second interleaved data includes a copy of constrained data in the same sequence and having the same values as the constrained data. Also, the portion of the second interleaved data that includes the copy of the constrained data satisfies a modulation constraint associated with limiting a number of consecutive events to a maximum number of consecutive events. The encoded data is decoded to obtain first interleaved data and the first interleaved data is de-interleaved using a first interleaving mapping to obtain the constrained data, a copy of which is included in the second interleaved data, where the constrained data satisfies the modulation constraint.Type: ApplicationFiled: October 14, 2013Publication date: May 1, 2014Applicant: SK Hynix Memory Solutions Inc.Inventors: Lingqi Zeng, Yu Kou, Kin Man Ng
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Patent number: 8677218Abstract: It is decided whether to adjust data associated with a decoder. In the event it is decided to adjust the data associated with the decoder, the data is adjusted to obtain adjusted data and decoding is performed using the decoder and the adjusted data. In the event it is decided to not adjust the data associated with the decoder, decoding is performed using the decoder and the data associated with the decoder.Type: GrantFiled: November 23, 2010Date of Patent: March 18, 2014Assignee: SK hynix memory solutions inc.Inventors: Lingqi Zeng, Yu Kou
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Patent number: 8671326Abstract: A method of encoding user data into a first set of codewords using a first code, generating a first set of parity information based at least in part on the first set of codewords and at least a second code, and writing at least parity information associated with the first set of parity information to shingled magnetic recording storage. A method of performing decoding on a first set of read-back signal data read back from shingled magnetic recording storage and associated with a first set of codewords, and if decoding of at least one read-back signal in the first set of read-back signal data fails, performing decoding on at least some of a second set of read-back signal data associated with a set of parity information.Type: GrantFiled: May 15, 2012Date of Patent: March 11, 2014Assignee: SK hynix memory solutions inc.Inventors: Xiangyu Tang, Yu Kou, Lingqi Zeng
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Patent number: 8650453Abstract: A cost function is obtained. For each of a plurality of groups of nodes, the cost function is evaluated by obtaining, for a given group of nodes, one or more reliability values associated with the given group of nodes; the one or more reliability values include sign and magnitude. For a given group of nodes, a reliability value with a smallest magnitude is selected where the evaluated cost function for the given group of nodes is set to the smallest magnitude. One of the plurality of groups of nodes is selected based at least in part on the evaluated cost functions. Error correction decoding related processing is performed on the selected group of nodes.Type: GrantFiled: February 28, 2013Date of Patent: February 11, 2014Assignee: SK hynix memory solutions inc.Inventors: Kin Man Ng, Lingqi Zeng, Yu Kou, Kwok W. Yeung
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Patent number: 8631311Abstract: A method for recovering data is disclosed. A sensed analog signal is converted into digital samples using an analog-to-digital converter (ADC). The digital samples are processed into processed digital samples using a first filter. The processed digital samples are decoded into decoded data. Whether the decoded data is acceptable is then determined. The processed digital samples are fed back to the first filter using a reprocessing circuit such that the processed digital samples are reprocessed into reprocessed digital samples in the event that the decoded data is unacceptable. A set of reprocessing coefficients is provided for the first filter to reprocess the processed digital samples.Type: GrantFiled: April 23, 2012Date of Patent: January 14, 2014Assignee: SK hynix memory solutions inc.Inventors: Kai Keung Chan, Yu Kou, Xin-Ning Song, Wing Hui
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Patent number: 8607132Abstract: A method for reducing a number of bits for representing a value is disclosed. A first value represented with a first number of bits is transformed to a second value represented with a second number of bits, wherein the first number of bits is greater than the second number of bits. The transformed second value is scaled by a scale factor to a third value. Transforming includes selecting a target window with a width of a third number of bits, wherein the third number of bits is smaller than the first number of bits. Transforming further includes saturating the first value to a most significant bit (MSB) within the selected target window and extracting bits within the selected target window from the saturated value.Type: GrantFiled: May 2, 2011Date of Patent: December 10, 2013Assignee: SK hynix memory solutions inc.Inventors: Yu Kou, Lingqi Zeng
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Patent number: 8589760Abstract: A method for detecting a defect in a portion of a storage device is disclosed. Reference data and data read from the portion are compared to determine a number of error bits and a number of error symbols. An error ratio is computed, wherein the error ratio comprises a ratio of the number of error bits to the number of error symbols. A defect is detected based on whether the error ratio exceeds a threshold. In some embodiments, the reference data and the read data are compared to determine an error vector, wherein a bit in the error vector with a value one indicates a bit error in the read data. For each of a plurality of windows of the error vector, a corresponding number of error bits is determined. A defect is detected based on whether any of the numbers of error bits exceeds a threshold.Type: GrantFiled: March 30, 2011Date of Patent: November 19, 2013Assignee: SK hynix memory solutions inc.Inventors: Yu Kou, Lingqi Zeng
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Patent number: 8583979Abstract: A technique for processing data. The technique includes modulation encoding input data. A first interleaving process is used to obtain first interleaved data. The first interleaved data is systematically encoded. The systematically encoded data is interleaved using a second interleaving process to obtain second interleaved data. The second interleaving process is an inverse of the first interleaving process, at least for a common portion.Type: GrantFiled: May 19, 2009Date of Patent: November 12, 2013Assignee: SK hynix memory solutions inc.Inventors: Lingqi Zeng, Yu Kou, Kin Man Ng
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Patent number: 8572463Abstract: In processing quasi-cyclic low-density parity-check (QC-LDPC) data, an input signal is received which includes decision and reliability information corresponding to unpadded data. Decision and reliability information corresponding to padded data is introduced into the input signal. Message passing is performed one or more times to obtain decoded data. This includes using (1) the decision and reliability information corresponding to the unpadded data and (2) the decision and reliability information corresponding to the padded data, where a preference is given to the decision and reliability information corresponding to the unpadded data over the decision and reliability information corresponding to the unpadded data during message passing. Zero padding is removed from the decoded data.Type: GrantFiled: February 25, 2011Date of Patent: October 29, 2013Assignee: SK hynix memory solutions inc.Inventors: Lingqi Zeng, Yu Kou, Kin Man Ng, Kwok W. Yeung
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Patent number: 8560900Abstract: Adjusting receiving parameters without known data is disclosed, including: receiving an indication of whether data associated with a sector is error correcting code (ECC) uncorrectable; in the event that the indication is that the data is uncorrectable, determining a plurality of statistical information outputs using a detector; and using at least a subset of the plurality of statistical information outputs to adjust a set of one or more receiver parameters.Type: GrantFiled: June 14, 2011Date of Patent: October 15, 2013Assignee: SK hynix memory solutions inc.Inventors: Jason Bellorado, Marcus Marrow, Yu Kou
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Publication number: 20130246880Abstract: A cost function is obtained. For each of a plurality of groups of nodes, the cost function is evaluated by obtaining, for a given group of nodes, one or more reliability values associated with the given group of nodes; the one or more reliability values include sign and magnitude. For a given group of nodes, a reliability value with a smallest magnitude is selected where the evaluated cost function for the given group of nodes is set to the smallest magnitude. One of the plurality of groups of nodes is selected based at least in part on the evaluated cost functions. Error correction decoding related processing is performed on the selected group of nodes.Type: ApplicationFiled: February 28, 2013Publication date: September 19, 2013Applicant: SK HYNIX MEMORY SOLUTIONS INC.Inventors: Kin Man Ng, Lingqi Zeng, Yu Kou, Kwok W. Yeung
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Patent number: 8504894Abstract: Encoding is performed by putting a low-density parity-check (LDPC) generator matrix into partial quasi-cyclic form comprising an identity matrix, a parity generator matrix, a zero matrix and a remainder matrix. The parity generator matrix is quasi-cyclic and the remainder matrix is not quasi-cyclic. An encoder is used to generate LDPC encoded data using the parity generator matrix and without using the remainder matrix.Type: GrantFiled: March 2, 2011Date of Patent: August 6, 2013Assignee: SK hynix memory solutions inc.Inventors: Lingqi Zeng, Yu Kou, Kin Man Ng, Kwok W. Yeung
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Patent number: 8489973Abstract: The present application refers to a method for determining an extrinsic information input to an ECC decoder of a turbo equalizer. In one embodiment, a first loop-back signal is represented with a first number of bits, wherein the first loop-back signal comprises a signal looped back from an output of an ECC decoder. An output of a signal detector is represented with a second number of bits. An extrinsic information input to the ECC decoder is determined based at least in part on the first loop-back signal, the represented output of the signal detector, and at least one comparison with at least one predetermined threshold.Type: GrantFiled: August 2, 2011Date of Patent: July 16, 2013Assignee: SK hynix memory solutions inc.Inventors: Lingqi Zeng, Yu Kou
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Patent number: 8448041Abstract: Low-density parity-check (LDPC) encoding is performed by encoding input data using a first sub-matrix of a parity check matrix to obtain intermediate data. The parity check matrix includes the first sub-matrix and a second sub-matrix having a matrix inversion. The intermediate data is encoded using the matrix inversion of the second sub-matrix of the parity check matrix.Type: GrantFiled: December 16, 2010Date of Patent: May 21, 2013Assignee: SK hynix memory solutions inc.Inventors: Lingqi Zeng, Abhiram Prabhakar, Kin Man Ng, Yu Kou
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Patent number: 8443257Abstract: Encoding is performed by dividing a quasi-cyclic low-density parity-check (QC-LDPC) parity check matrix into a first sub-matrix and a second sub-matrix. The first sub-matrix includes a plurality of circulant vectors and the plurality of circulant vectors is associated with a circulant size. Input data is received having a length which is a product of an integer multiplier and the circulant size. A first stage of multi-stage LDPC encoding is performed using the input data and a subset of the plurality of circulant vectors; the number of circulant vectors in the subset equals the integer multiplier.Type: GrantFiled: March 2, 2011Date of Patent: May 14, 2013Assignee: SK hynix memory solutions inc.Inventors: Lingqi Zeng, Yu Kou, Kin Man Ng, Kwok W. Yeung
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Patent number: 8418020Abstract: A cost function is obtained. For each of a plurality of groups of check nodes associated with low-density parity-check (LDPC) encoded data, the cost function is evaluated using information associated with a variable node and/or information associated with a check node. One of the groups of check nodes is selecting based at least in part on the evaluated cost functions. Error correction decoding related processing is performed on the selected group of check nodes.Type: GrantFiled: June 7, 2012Date of Patent: April 9, 2013Assignee: SK hynix memory solutions inc.Inventors: Kin Man Ng, Lingqi Zeng, Yu Kou, Kwok W. Yeung
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Patent number: 8386869Abstract: A defect portion in a signal is processed by receiving an input signal. A location of a defect portion within the input signal and an amplitude of the defect portion is determined. An adjusted signal is generated by adjusting the amplitude of the defect portion using the determined location of the defect portion and the determined amplitude of the defect portion. Information associated with the adjusted signal is decoded.Type: GrantFiled: June 16, 2009Date of Patent: February 26, 2013Assignee: Link—A—Media Devices CorporationInventors: Yu Kou, Zheng Wu
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Patent number: 8347126Abstract: A current limiting and averaging circuit for driving a peripheral core circuit with a lower limit current value in response to a supply signal, includes a current limiting module, an energy storage module, and a converter module. The current limiting module provides a limited supply signal whose current value is smaller than or equal to an upper limit value according to the supply signal. The energy storage module stores a storage signal according to the limited supply signal when the upper limit value is higher than the lower limit current value and provides a discharge signal according to the storage signal when the upper limit value is lower than the lower limit current value. The converter module provides a driving signal for driving the peripheral core circuit in response to the limited supply signal or the limited supply signal and the discharge signal.Type: GrantFiled: September 1, 2010Date of Patent: January 1, 2013Assignee: Quanta Computer Inc.Inventors: Fang-Yu Kou, Jui-Hui Lin, Jui-I Wu, Hung-Jen Hou
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Publication number: 20120304036Abstract: An amount of time and an error rate function are received, where the error rate function defines a relationship between a number of iterations associated with iterative decoding and an error rate. A testing error rate is determined based at least in part on the amount of time. The number of iterations which corresponds to the testing error rate in the error rate function is selected to be a testing number of iterations; the testing error rate and the testing number of iterations are associated with testing storage media using iterative decoding.Type: ApplicationFiled: August 9, 2012Publication date: November 29, 2012Applicant: LINK_A_MEDIA DEVICES CORPORATIONInventors: Yu Kou, Lingqi Zeng