Patents by Inventor Yuan Yu

Yuan Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11953079
    Abstract: A knob-driven adjusting mechanism has two fastening belts, one adjusting device, two base seats and two shafts. The fastening belt goes through a long groove. The fastening belt is formed with a tooth row on the side of the long groove. The adjusting device has a shell seat and a knob, and each fastening belt respectively goes through the shell seat. The knob is configured on the shell seat in a rotary form to drive the fastening belts. Each base seat is respectively used for the two side parts configured on an object. The base seat has two protruding support parts. Each shaft is respectively configured on each base seat. The two ends of the shaft respectively goes into each support part in the axial direction. Each shaft is respectively connected to each fastening belt, so that each fastening belt can respectively rotate in relation to the base seat.
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: April 9, 2024
    Inventors: Yuan-Ming Chen, Tuan-Yu Chen, Yen-Yu Chen
  • Patent number: 11955515
    Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure on the fin structure, forming first and second S/D regions within the superlattice structure, forming a gate structure between the first and second S/D regions, forming first and second contact structures on first surfaces of the first and second S/D regions, and forming a third contact structure, on a second surface of the first S/D region, with a work function metal (WFM) silicide layer and a dual metal liner. The second surface is opposite to the first surface of the first S/D region and the WFM silicide layer has a work function value closer to a conduction band energy than a valence band energy of a material of the first S/D region.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Chuan Chiu, Chia-Hao Chang, Cheng-Chi Chuang, Chih-Hao Wang, Huan-Chieh Su, Chun-Yuan Chen, Li-Zhen Yu, Yu-Ming Lin
  • Patent number: 11947173
    Abstract: A package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.
    Type: Grant
    Filed: May 5, 2023
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
  • Patent number: 11946349
    Abstract: A downhole throttling device based on wireless control includes an inlet nozzle, a throttling assembly, an electrical sealing cylinder, a gas guide cylinder, a lower adapter sleeve, an end socket, a female sleeve, and electrical components. The inlet nozzle is connected to the throttling assembly, the throttling assembly is connected to the electrical sealing cylinder and the gas guide cylinder, the electrical sealing cylinder and the gas guide cylinder are both connected to the lower adapter sleeve, the lower adapter sleeve is respectively connected to the end socket and the female sleeve, and the electrical components are arranged in the electrical sealing cylinder. A throttling effect is achieved by detecting the temperature and pressure in a tube by a temperature/pressure sensor in the electrical components and controlling a motor to rotate a movable valve in the throttling assembly by a circuit control assembly, thereby achieving wireless control over downhole throttling.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: April 2, 2024
    Assignees: PetroChina Company Limited, Sichuan Shengnuo Oil. And Gas Engineering Technology Service Co., Ltd
    Inventors: Jun Xie, Huiyun Ma, Jian Yang, Chenggang Yu, Yukun Fu, Qiang Yin, Kui Li, Yuan Jiang, Dezheng Yi, Yanyan Liu, Haifeng Zhong, Xiaodong Liu
  • Publication number: 20240104019
    Abstract: Disclosed is a method for enhancing memory utilization and throughput of a computing platform in training a deep neural network (DNN). The critical features of the method includes: calculating a memory size for every operation in a computational graph, storing the operations in the computational graph in multiple groups with the operations in each group being executable in parallel and a total memory size less than a memory threshold of a computational device, sequentially selecting a group and updating a prefetched group buffer, and simultaneously executing the group and prefetching data for a group in the prefetched group buffer to the corresponding computational device when the prefetched group buffer is update. Because of group execution and data prefetch, the memory utilization is optimized and the throughput is significantly increased to eliminate issues of out-of-memory and thrashing.
    Type: Application
    Filed: September 9, 2020
    Publication date: March 28, 2024
    Applicant: AETHERAI IP HOLDING LLC
    Inventors: Chi-Chung CHEN, Wei-Hsiang YU, Chao-Yuan YEH
  • Publication number: 20240105775
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first source/drain structure and a second source/drain structure over and in a substrate. The method includes forming a first gate stack, a second gate stack, a third gate stack, and a fourth gate stack over the substrate. Each of the first gate stack or the second gate stack is wider than each of the third gate stack or the fourth gate stack. The method includes forming a first contact structure and a second contact structure over the first source/drain structure and the second source/drain structure respectively. A first average width of the first contact structure is substantially equal to a second average width of the second contact structure.
    Type: Application
    Filed: February 9, 2023
    Publication date: March 28, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Yu CHIANG, Hsiao-Han LIU, Yuan-Hung TSENG, Chih-Yung LIN
  • Patent number: 11939280
    Abstract: A method for preparing isophorone diisocyanate by (1) reacting isophorone with hydrogen cyanide in the presence of a catalyst to obtain isophorone nitrile; (2) reacting the isophorone nitrile obtained in step (1) with ammonia gas and hydrogen in the presence of a catalyst to obtain isophorone diamine; and (3) subjecting the isophorone diamine to a phosgenation reaction to obtain the isophorone diisocyanate, wherein the content of impurities containing a secondary amine group in the isophorone diamine that undergoes the phosgenation reaction in step (3) is ?0.5 wt. The method reduces the content of hydrolyzed chlorine in the isophorone diisocyanate product, improves the yellowing resistance of the product, and the harm due to presence of hydrolyzed chlorine in the product is reduced.
    Type: Grant
    Filed: December 25, 2018
    Date of Patent: March 26, 2024
    Assignee: WANHUA CHEMICAL GROUP CO., LTD.
    Inventors: Yong Yu, Yonghua Shang, Lei Zhao, Wenbin Li, Ye Sun, Wei He, Xuelei Cui, Jingxu Wang, Degang Liu, Yuan Li
  • Patent number: 11940616
    Abstract: A switchable light transmission module is disclosed that includes a substrate having a first surface defining at least part of an enclosed volume, a porous layer disposed on the first surface and in fluid communication with the enclosed volume, and a reservoir in fluid communication with the enclosed volume. The reservoir is configured to supply a fluid to the sealed volume such that the fluid contacts the porous layer. The fluid has a refractive index that is close to the refractive index of the porous layer, has a high wettability for the porous layer, and does not dissolve the porous layer. When in a dry state, voids in the porous layer are filled with air which has a much different refractive index than the porous layer itself, resulting in a surface that is reflective and not very transmissive.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: March 26, 2024
    Assignee: The Trustees of Columbia University in the City of New York
    Inventors: Jyotirmoy Mandal, Yuan Yang, Nanfang Yu
  • Publication number: 20240096996
    Abstract: A semiconductor device includes a first dielectric layer, a stack of semiconductor layers disposed over the first dielectric layer, a gate structure wrapping around each of the semiconductor layers and extending lengthwise along a direction, and a dielectric fin structure and an isolation structure disposed on opposite sides of the stack of semiconductor layers and embedded in the gate structure. The dielectric fin structure has a first width along the direction smaller than a second width of the isolation structure along the direction. The isolation structure includes a second dielectric layer extending through the gate structure and the first dielectric layer, and a third dielectric layer extending through the first dielectric layer and disposed on a bottom surface of the gate structure and a sidewall of the first dielectric layer.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Inventors: Huan-Chieh Su, Chun-Yuan Chen, Li-Zhen Yu, Lo-Heng Chang, Cheng-Chi Chuang, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20240093142
    Abstract: The present invention relates to the fields of microorgan-isms, feed, food and ecological restoration, in particular to a strain for degrading deoxynivalenol (DON) and the use thereof. The strain has the deposit number CCTCC No. M 2020565. The strain can grow by means of taking the toxic compound DON as a sole carbon source, and convert the DON into chemical components for itself. The reaction process is irreversible, the reaction conditions are moderate, and secondary pollu-tion cannot be caused. The strain provided in the present invention can be used for preparing a biological detoxification preparation for DON. The strain provided in the present invention can be used for degrading DON in feed and food raw materials, primary processing products, deep processing products and related processing byproducts. The strain provided in the present invention can be applied to various ecosystems such as soil or bodies of water polluted by DON to achieve the purposes of DON degradation and ecological restoration.
    Type: Application
    Filed: November 11, 2021
    Publication date: March 21, 2024
    Inventors: Huiying LUO, Honghai ZHANG, Bin YAO, Huoqing HUANG, Yaru WANG, Yingguo BAI, Xiaoyun SU, Yuan WANG, Tao TU, Jie ZHANG, Huimin YU, Xing QIN, Xiaolu WANG
  • Publication number: 20240098908
    Abstract: A preparation method for a circuit board connection structure includes: providing a circuit board module that including a first outer wiring layer, and the first outer wiring layer including solder pads; forming a first pyrolytic adhesive layer and an inner wiring layer on the first outer wiring layer; forming a second pyrolytic adhesive layer and a second copper foil layer on the inner wiring layer; defining a plurality of through holes each configured to expose one of the solder pads; forming a copper plating layer on the second copper foil layer; etching the copper plating layer and the second copper foil layer to form a second outer wiring layer, thereby obtaining an intermediate body; heating and washing the intermediate body to remove the first pyrolytic adhesive layer and the second pyrolytic adhesive layer. The present application also provides a circuit board connection structure.
    Type: Application
    Filed: August 14, 2023
    Publication date: March 21, 2024
    Applicants: HongQiSheng Precision Electronics (QinHuangDao) Co.,Ltd., Avary Holding (Shenzhen) Co., Limited.
    Inventors: CHIH-CHIEH FU, YUAN-YU LIN, QUAN YUAN
  • Patent number: 11935871
    Abstract: A semiconductor package including a first semiconductor die, a second semiconductor die, a first insulating encapsulation, a dielectric layer structure, a conductor structure and a second insulating encapsulation is provided. The first semiconductor die includes a first semiconductor substrate and a through silicon via (TSV) extending from a first side to a second side of the semiconductor substrate. The second semiconductor die is disposed on the first side of the semiconductor substrate. The first insulating encapsulation on the second semiconductor die encapsulates the first semiconductor die. A terminal of the TSV is coplanar with a surface of the first insulating encapsulation. The dielectric layer structure covers the first semiconductor die and the first insulating encapsulation. The conductor structure extends through the dielectric layer structure and contacts with the through silicon via.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Yi Tsai, Cheng-Chieh Hsieh, Tsung-Hsien Chiang, Hui-Chun Chiang, Tzu-Sung Huang, Ming-Hung Tseng, Kris Lipu Chuang, Chung-Ming Weng, Tsung-Yuan Yu, Tzuan-Horng Liu
  • Patent number: 11935878
    Abstract: A method for manufacturing a package structure includes providing a carrier board; providing at least one die having a top surface, a bottom surface, and a side surface on the carrier board; and forming a protective layer to cover at least a portion of the side surface of the die. The die includes a substrate, a semiconductor layer, a gate structure, a source structure and a drain structure, at least one dielectric layer, and at least one pad. The semiconductor layer is disposed on the substrate. The gate structure is disposed on the semiconductor layer. The source and the drain structures are disposed on opposite sides of the gate structure. The dielectric layer covers the gate, source, and drain structures. The pad is disposed on the dielectric layer and penetrates through the dielectric layer to electrically contact with the gate, source or drain structure.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: March 19, 2024
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Hsiu-Mei Yu, Guang-Yuan Jiang, Cheng-Yi Hsieh, Wei-Chan Chang, Chang-Sheng Lin
  • Patent number: 11931363
    Abstract: A compound of Formula (I), or a pharmaceutically acceptable salt thereof, is provided that has been shown to be useful for treating a PRC2-mediated disease or disorder: wherein R1, R2, R3, R4, R5, and n are as defined herein.
    Type: Grant
    Filed: October 19, 2021
    Date of Patent: March 19, 2024
    Assignee: NOVARTIS AG
    Inventors: Ho Man Chan, Xiang-Ju Justin Gu, Ying Huang, Ling Li, Yuan Mi, Wei Qi, Martin Sendzik, Yongfeng Sun, Long Wang, Zhengtian Yu, Hailong Zhang, Ji Yue (Jeff) Zhang, Man Zhang, Qiong Zhang, Kehao Zhao
  • Publication number: 20240085690
    Abstract: A structured material is provided that includes a substrate and a porous structured polymer layer disposed thereon. The porous structured polymer layer includes a plurality of voids, and has a high hemispherical reflectance a high a hemispherical thermal emittance. The structured material is thus particularly advantageous for cool-roof coatings, enabling surfaces coated by the material to stay cool, even under strong sunlight. The material can be produced via structuring of polymers in a mixture including a solvent and a non-solvent. Sequential evaporation of the solvent and the non-solvent provide a polymer layer with the plurality of voids.
    Type: Application
    Filed: August 8, 2023
    Publication date: March 14, 2024
    Applicant: THE TRUSTEES OF COLUMBIA UNIVERSITY IN THE CITY OF NEW YORK
    Inventors: Jyotirmoy MANDAL, Yuan YANG, Nanfang YU
  • Patent number: 11919824
    Abstract: Disclosed are a silicon nitride ceramic sintered body and preparation method thereof. The silicon nitride ceramic sintered body includes a sintered bulk and a hard surface layer having a thickness of 10-1000 ?m, formed on a surface of the sintered bulk, wherein the sintered bulk comprises a first silicon nitride crystalline phase and a first grain boundary phase; the hard surface layer comprises a second silicon nitride crystalline phase and a second grain boundary phase; the first grain boundary phase comprises a metal tungsten phase being tungsten elementary substance and/or a tungsten alloy; the second grain boundary phase comprises tungsten carbide particles; tungsten element in the metal tungsten phase accounts for 80-100 wt % of total tungsten element in the first grain boundary phase; and tungsten element in the tungsten carbide particles accounts for 60-100 wt % of total tungsten element in the second grain boundary phase.
    Type: Grant
    Filed: May 19, 2023
    Date of Patent: March 5, 2024
    Assignees: Lanzhou Institute of Chemical Physics, CAS, Yantai Zhongke Research Institute of Advanced Materials and Green Chemical Engineering, Shandong Laboratory of Yantai Advanced Materials and Green Manufacturing
    Inventors: Zhuhui Qiao, Lujie Wang, Tongyang Li, Ziyue Wang, Yuan Yu, Huaguo Tang
  • Publication number: 20240069277
    Abstract: A semiconductor package includes a first die stack structure and a second die stack structure, an insulating encapsulation, a redistribution structure, at least one prism structure and at least one reflector. The first die stack structure and the second die stack structure are laterally spaced apart from each other along a first direction, and each of the first die stack structure and the second die stack structure comprises an electronic die; and a photonic die electronically communicating with the electronic die. The insulating encapsulation laterally encapsulates the first die stack structure and the second die stack structure. The redistribution structure is disposed on the first die stack structure, the second die stack structure and the insulating encapsulation, and electrically connected to the first die stack structure and the second die stack structure. The at least one prism structure is disposed within the redistribution structure and optically coupled to the photonic die.
    Type: Application
    Filed: August 29, 2022
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Yi Kuo, Chen-Hua Yu, Cheng-Chieh Hsieh, Che-Hsiang Hsu, Chung-Ming Weng, Tsung-Yuan Yu
  • Publication number: 20240068043
    Abstract: Provided is a method for diagnosing and monitoring progression of cancer or effectiveness of a therapeutic treatment. The method includes detecting a methylation level of at least one gene in a biological sample containing circulating free DNA. Also provided are primer pairs and probes for diagnosis or prognosis of cancer in a subject in need thereof.
    Type: Application
    Filed: March 1, 2022
    Publication date: February 29, 2024
    Applicant: NATIONAL TAIWAN UNIVERSITY
    Inventors: Hsing-Chen TSAI, Chong-Jen YU, Hsuan-Hsuan LU, Shu-Yung LIN, Yi-Jhen HUANG, Chen-Yuan DONG
  • Patent number: 11914188
    Abstract: An atom trap integrated platform (ATIP) comprises a substrate, a membrane, and a suspended waveguide. The substrate has an opening formed therein. The membrane extends across a portion of the substrate opening. The suspended waveguide is formed on the membrane such that the suspended waveguide extends from a first edge of the substrate to a second edge. A magneto-optical trap (MOT) is formed around the suspended waveguide by emitting a plurality of cooling beams and a repump through the substrate opening. Evanescent fields are established above the suspended waveguide by coupling two trapping beams through the suspended waveguide, which trapping beams are red-detuned and blue-detuned with respect to the resonant optical transition of the atoms. By forming the MOT within the evanescent fields, an evanescent field optical trap (EFOT) is formed.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: February 27, 2024
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventors: Jongmin Lee, Michael Gehl, Grant Biedermann, Yuan-Yu Jau, Christopher T. DeRose
  • Patent number: 11916023
    Abstract: A package includes a package component, a device die over and bonded to the package component, a metal cap having a top portion over the device die, and a thermal interface material between and contacting the device die and the metal cap. The thermal interface material includes a first portion directly over an inner portion of the device die, and a second portion extending directly over a corner region of the device die. The first portion has a first thickness. The second portion has a second thickness greater than the first thickness.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sung-Hui Huang, Da-Cyuan Yu, Kuan-Yu Huang, Pai Yuan Li, Hsiang-Fan Lee