Abstract: A method of cleaning a nozzle of a gas supply system includes loading an apparatus including a carrier and an automated nozzle cleaning system in the carrier onto a load port containing a gas supply system. The automated nozzle cleaning system includes a first nozzle cleaning device, a second nozzle cleaning device and a monitoring device, and the carrier is positioned to enable a gas inlet of the carrier to be connected to a nozzle of the gas supply system. The method also includes vacuuming contaminant particles from the nozzle using the first nozzle cleaning device, mechanically removing the contaminant particles adhering to the nozzle off the nozzle using the second nozzle cleaning device, and measuring a level of the contaminant particles using the monitoring device.

Abstract: A PCI-E expansion card module is configured to insert in a slot with a rotation switch. The PCI-E expansion card module includes a PCI-E expansion card body and an unlock mechanism. The PCI-E expansion card body includes an inserting portion and a positioning hook. The unlock mechanism is disposed beside the PCI-E expansion card body, and the unlock mechanism includes a pushing member. When the PCI-E expansion card body is inserted into the slot, the rotation switch is on a moving path of the pushing member. The pushing member moves and pushes the rotation switch to release a limitation of the PCI-E expansion card body.

Abstract: A paper-based micro-concentrator includes a bearing substrate, a fluid reservoir unit, a filter paper, an external electric field, an ion exchange membrane and a magnet. The fluid reservoir unit includes a first buffer solution tank and a second buffer solution tank, which are interval disposed on the bearing substrate. The filter paper is disposed on the bearing substrate, and two ends of the filter paper are respectively placed in the first buffer solution tank and the second buffer solution tank. The external electric field includes a cathode and an anode, which are respectively placed in the first buffer solution tank and the second buffer solution tank. The ion exchange membrane is disposed on the filter paper and close to the first buffer solution tank. The magnet is movably disposed under the bearing substrate.

Abstract: A method for manufacturing a fan-out chip packaging structure with decreased use of a crack-inducing hot-soldering process includes a first carrier plate with first and a second outer wiring layers. Two first conductive posts are formed on the first outer wiring layer, one end of each post is electrically connected to the first outer wiring layer. A receiving groove is formed between first conductive posts, and a sidewall of each post is surrounded by a first insulating layer. An embedded component is laid in the receiving groove and a second carrier plate is formed on the first insulating layer, wherein the second carrier plate carries third and fourth outer wiring layers. A first outer component is connected to the second outer wiring layer, and a second outer component is connected to the fourth outer wiring layer.

Abstract: A memory device includes a first active area, a first doped structure of a first doping type, a second active area, a first gate structure and a second doped structure of a second doping type different from the first doping type. The second active area is disposed between the first active area and the first doped structure. The first gate structure is disposed between the first active area and the second active area in a layout view, and configured to store a first bit with the first active area and the second active area. The second doped structure is coupled to the first gate structure and disposed between the first doped structure and the second active area. The second doped structure and the first doped structure are configured to receive a first signal corresponding to the first bit from the first gate structure.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for receiving a request from a client to process a computational graph; obtaining data representing the computational graph, the computational graph comprising a plurality of nodes and directed edges, wherein each node represents a respective operation, wherein each directed edge connects a respective first node to a respective second node that represents an operation that receives, as input, an output of an operation represented by the respective first node; identifying a plurality of available devices for performing the requested operation; partitioning the computational graph into a plurality of subgraphs, each subgraph comprising one or more nodes in the computational graph; and assigning, for each subgraph, the operations represented by the one or more nodes in the subgraph to a respective available device in the plurality of available devices for operation.

Abstract: An optical interconnect structure including a base substrate, an optical waveguide, a first reflector, a second reflector, a dielectric layer, a first lens, and a second lens is provided. The optical waveguide is embedded in the base substrate. The optical waveguide includes a first end portion and a second end portion opposite to the first end portion. The first reflector is disposed between the base substrate and the first end portion of the optical waveguide. The second reflector is disposed between the base substrate and the second end portion of the optical waveguide. The dielectric layer covers the base substrate and the optical waveguide. The first lens is disposed on the dielectric layer and located above the first end portion of the optical waveguide. The second lens is disposed on the dielectric layer and located above the second end portion of the optical waveguide.

Abstract: Systems and methods for processing loops in computational graphs representing machine learning models are disclosed. An example method begins with obtaining data representing a computational graph. Data identifying an allocation of the computational graph across devices is obtained. Additionally, one or more nodes in the computational graph that represent a respective control flow statement are identified. For each identified node, a structure of nodes and edges that represents an operation that provides a current state of recursion or iteration in the respective control flow statement is generated. This structure is inserted into the computational graph and the allocation of nodes to devices is modified to assign the structure to a device.

Abstract: A high efficiency embedded-artificial synaptic element includes a semiconductor substrate, a select transistor, a metal layer, a first memory transistor and a second memory transistor. The select transistor is disposed on the semiconductor substrate and includes a select gate structure, a drain region and a source region. The metal layer is connected to the drain region. The first memory transistor includes a first gate structure, a first electrode region and a first memristor. The second memory transistor includes a second gate structure, a second electrode region and a second memristor. The second electrode region and the first electrode region are connected to each other and form a connection region, which is connected to the metal layer. The first memristor is formed between the first gate structure and the connection region, and the second memristor is formed between the second gate structure and the connection region.

Abstract: A high density embedded-artificial synaptic element includes a semiconductor substrate, a select transistor, a metal layer and a memory transistor. The select transistor is disposed on the semiconductor substrate and includes a first gate structure, a drain region and a source region. The drain region and the source region are located on the opposite sides of the first gate structure. The metal layer is connected to the drain region. The memory transistor is disposed on the semiconductor substrate and includes a second gate structure, a first electrode region, a second electrode region, a first memristor and a second memristor. The second gate structure is connected to the metal layer. The first memristor is formed between the second gate structure and the first electrode region. The second memristor is formed between the second gate structure and the second electrode region.

Abstract: Disclosed are semiconductor packages and manufacturing method of the semiconductor packages. In one embodiment, a semiconductor package includes a substrate, a first waveguide, a semiconductor die, and an adhesive layer. The first waveguide is disposed on the substrate. The semiconductor die is disposed on the substrate and includes a second waveguide aligned with the first waveguide. The adhesive layer is disposed between the first waveguide and the second waveguide.

Abstract: A semiconductor device includes a substrate. The semiconductor device further includes a waveguide on a first side of the substrate. The semiconductor device further includes a photodetector (PD) on a second side of the substrate, opposite the first side of the substrate. The semiconductor device further includes an optical through via (OTV) optically connecting the PD with the waveguide, wherein the OTV extends through the substrate from the first side of the substrate to the second side of the substrate.

Abstract: A package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.

Abstract: A wireless charging device includes a plug module, a rack and a wireless charger. The plug module has a top wall, and two opposite side walls connected with two opposite sides of the top wall. A front end of a top surface of the top wall of the plug module is defined as an inclined plane. The rack is mounted on the inclined plane of the plug module. A front end of a bottom surface of the rack is recessed inward to form a lower accommodating groove. The inclined plane is mounted in the lower accommodating groove. A top surface of the rack is recessed downward to form an upper accommodating groove. The wireless charger is mounted in the upper accommodating groove.

Abstract: An expansion card assembly, including an expansion card body and a connector. The expansion card body includes a notch recessed into an edge thereof. The connector includes a housing. The housing includes a top surface, a bottom surface, and an engaging portion disposed on the bottom surface. The bottom surface is close to the expansion card body. The engaging portion is exposed out of the notch. The engaging portion connects the connector with an external power cord. A user operates the engaging portion at the bottom surface of the housing of the connector with fingers. Therefore, the expansion card assembly and the connector solve the problem that the too narrow space between the top surface of the housing and the other components makes it difficult for the user to stretch fingers into the space between the top surface of the housing and the other component.

Abstract: A semiconductor device includes an optical connector element and an optical coupler. The optical connector element includes a base structure, a first polymer via and a cladding layer. The base structure has a first surface and a second surface opposite to the first surface. The first polymer via passes through the base structure from the first surface to the second surface. The cladding layer is surrounding the first polymer via, wherein a refractive index of the cladding layer is different than a refractive index of the first polymer via. The optical coupler is disposed over the optical connector element, wherein the optical coupler receives optical signals from the first polymer via.

Abstract: Disclosed herein are related to a memory cell including one or more programmable resistors and a control transistor. In one aspect, a programmable resistor includes a gate structure and one or more source/drain structures for forming a transistor. A resistance of the programmable resistor may be set by applying a voltage to the gate structure, while the control transistor is enabled. Data stored by the programmable resistor can be read by sensing current through the programmable resistor, while the control transistor is disabled. In one aspect, the one or more programmable resistors and the control transistor are implemented by same type of components, allowing the memory cell to be formed in a compact manner through a simplified the fabrication process.

Abstract: The present disclosure discloses a preparation method of a multi-functional marine engineering alloy. Through the coupling of a multi-principal alloy structure, structural entropy, and temperature and powder metallurgy and heat treatment, mutual solubility between elements and free energy of an alloy system are regulated, Cu grain boundary segregation is eliminated, and uniform and dispersed nano-precipitation of the anti-fouling element Cu in corrosion-resistant and high-plasticity multi-principal alloys is realized. The preparation method is simple and controllable to operate, and the prepared material has plasticity higher than 75%, high yield strength, excellent corrosion resistance and anti-fouling property, and has important application prospects in the field of marine engineering.

Abstract: A calibration device for an intraoral scanner is provided. The calibration device includes a base, a moving portion, a circuit board, and a sensor. The moving portion is disposed on the base. The moving portion is moveable on the base along an extending direction of the calibration device. The moving portion includes a driving structure, a position determining portion, and a target plate. The position determining portion is coupled to and driven by the driving structure. The position determining portion has a first feature portion and a second feature portion different from the first feature portion. The target plate is coupled to the position determining portion. The circuit board is disposed at one side of the moving portion. The sensor is disposed on the circuit board. The sensor is configured to detect the first feature portion and the second feature portion to determine a position of the moving portion.

Abstract: A manufacturing method of a semiconductor package includes the following steps. A supporting layer is formed over a redistribution structure. A first planarization process is performed over the supporting layer. A lower dielectric layer is formed over the supporting layer, wherein the lower dielectric layer includes a concave exposing a device mounting region of the supporting layer. A first sacrificial layer is formed over the supporting layer, wherein the sacrificial layer filling the concave. A second planarization process is performed over the lower dielectric layer and the first sacrificial layer. A transition waveguide provided over the lower dielectric layer. The first sacrificial layer is removed. A semiconductor device is mounted over the device mounting region, wherein the semiconductor device includes a device waveguide is optically coupled to the transition waveguide.