Abstract: A method for manufacturing a memory includes: providing a substrate and multiple discrete pseudo bit line contact layers, a plurality of active areas being provided in the substrate, and each bit line contact layer being electrically connected to the active areas; forming pseudo bit line structures at tops of the pseudo bit line contact layers; forming sacrificial layers that fill regions between the adjacent pseudo bit line structures and are located on side walls of the pseudo bit line structures and the pseudo bit line contact layers; after forming the sacrificial layers, removing the pseudo bit line structures to form through holes exposing the pseudo bit line contact layers; removing the pseudo bit line contact layers to form through holes in the substrate; and forming bit line contact layers that fill the through holes in the substrate and are electrically connected to the active areas.

Abstract: A method for manufacturing a memory includes the following operations. A substrate and a plurality of separate initial bit line contact structures are provided, in which a plurality of active regions are formed in the substrate, and each of the initial bit line contact structures is electrically connected with the active regions, and each of the initial bit line contact structures is partially located in the substrate. Pseudo-bit line structures on the tops of the initial bit line contact structures are formed. The initial bit line contact structures are etched to form bit line contact layers and gaps between the substrate and the side walls of the bit line contact layers. First dielectric layers are formed on the side walls of the pseudo-bit line structures, in which the first dielectric layers are also located right above the gaps.

Abstract: A manufacturing method of a memory includes: providing a substrate and a bit line contact layer; forming a dummy bit line structure on top of the bit line contact layer; forming a spacer layer on the sidewall of both the dummy bit line structure and the bit line contact layer; forming a dielectric layer on the sidewall of the spacer layer; forming a sacrificial layer filling the area between adjacent dummy bit line structures, wherein the sacrificial layer covers the sidewall of the dielectric layer; after the sacrificial layer is formed, removing the dummy bit line structure; forming a bit line conductive portion which fills the hole and covers the bit line contact layer; and, after the bit line conductive portion is formed, removing the spacer layer.

Abstract: A semiconductor device is provided. The semiconductor device includes a plurality of memory cell groups and a plurality of sense amplification unit groups, and at least two memory cell groups share a same sense amplification unit group.

Abstract: A method for manufacturing a memory includes the following steps. A substrate and bit line contact layers are provided. Pseudo bit line structures are formed at tops of the bit line contact layers. Sacrificial layers filling regions between adjacent bit line structures are formed, and the sacrificial layers are located on side walls of the pseudo bit line structures and side walls of the bit line contact layers. After forming the sacrificial layers, the pseudo bit line structures are removed to form through holes exposing the bit line contact layers. Bit line conductive parts filling the through holes and covering the bit line contact layers are formed.

Abstract: A lens antenna system is disclosed. The lens antenna system comprises a hybrid focal source antenna circuit configured to generate a source antenna beam for integration with different lens structures. In some embodiments, the hybrid focal source antenna circuit comprises a set of antenna elements coupled to one another. In some embodiments, the set of antenna elements comprises a first antenna element configured to be excited in a first spherical mode; and a second antenna element configured to be excited in a second, different, spherical mode. In some embodiments, the first spherical mode and the second spherical mode are co-polarized. In some embodiments, the lens antenna system further comprises a lens configured to shape the source antenna beam associated with the hybrid focal source antenna circuit, in order to provide an output antenna beam.

Abstract: An apparatus comprising an interconnect comprising a conductive core; a first conductive layer connected to the conductive core and extending parallel to the conductive core towards a first end of the conductive core; a second conductive layer connected to the conductive core and extending parallel to the conductive core towards a second end of the conductive core; a first non-conductive layer between the conductive core and the first conductive layer; and a second non-conductive layer between the first conductive layer and the second conductive layer.

Abstract: The present disclosure relates to a potting adhesive, including: a component A and a component B, the component A including a first liquid organic adhesive containing dimethyl siloxane, the component B including a second liquid organic adhesive containing methyl hydrogen siloxane and silicone oil, at least one of the component A and the component B further including ceramic particles which are spherical particles with a particle size of 0.1 mm to 3 mm. The present disclosure further relates to a heat dissipation device, including an adhesive potting groove, a transformer provided in the adhesive potting groove, and a filling medium which fills and is consolidated in a gap between the transformer and the adhesive potting groove.

Abstract: Method, systems and apparatuses may provide for technology that divides an application into a plurality of portions that are each associated with one or more functions of the application and determine a plurality of transition probabilities between the plurality of portions. Some technology may also receive at least a first portion of the plurality of portions, and receive a relation file indicating the plurality of transition probabilities between the plurality of portions.

Abstract: A substrate structure of the memory, and a method for preparing the substrate structure of the memory are provided. The method includes: providing a substrate; forming a first mask layer on the substrate, the first mask layer including a plurality of strip patterns extending in a direction and spaced apart from each other; forming a first dielectric layer covering the first mask layer; forming a plurality of sacrificial portions spaced apart from each other in the first dielectric layer and covering a portion of the plurality of strip patterns; filling gaps between the sacrificial portions with a second dielectric material; forming a second mask layer by removing the sacrificial portions while retaining the second dielectric material in the gaps; and performing layer-by-layer etching into the substrate to form a plurality of active areas arranged in an array.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The method includes: providing a substrate; forming, on the substrate, a first mask layer having a plurality of strip-shaped first patterns arranged in parallel; forming, on the first mask layer, a second mask layer having a plurality of strip-shaped second patterns arranged in parallel; forming, on the second mask layer, a third mask layer having a plurality of strip-shaped third patterns arranged in parallel, the second patterns overlap with the third patterns, and the second patterns and the third patterns are configured to sever the first patterns at predetermined positions; and performing layer-by-layer etching, using the first mask layer, the second mask layer, and the third mask layer as masks to transfer the first patterns, the second patterns, and the third patterns to the substrate to form an array of discrete active areas.

Abstract: A computer implemented method, computer system and computer program product are provided for lost detection for paired mobile devices. According to the method, a processor receives behavior data of paired mobile devices from one or more sensors of the paired mobile devices, wherein the behavior data comprising one or more parameters that reflect current status of the paired mobile devices. And the processor compares the received behavior data with human behavior data model. And, in response to the received behavior data being not matched with the human behavior data model, the processor determines that at least one of the paired mobile devices is lost.

Abstract: In one embodiment, an interconnect apparatus (e.g., an interposer apparatus) includes a plurality of interconnect probes that each include a wave spring structure that includes a plurality of stacked wave spring discs. The wave spring discs may be formed in a sinusoidal wave form shape, or in another wave form shape.

Abstract: A method of manufacturing a semiconductor structure: providing a substrate with a trench; forming a first conductive layer in the trench, wherein the top of the first conductive layer is lower than the top of the trench; forming a dielectric layer on the first conductive layer; and forming a second conductive layer on the dielectric layer.

Abstract: A method for forming an active region array and a semiconductor structure are provided. The method for forming the active region array includes the steps of: providing a substrate; forming a first mask layer on a surface of the substrate, a first etched pattern being provided in the first mask layer; forming a second mask layer covering a surface of the first mask layer; forming a third mask layer having a second etched pattern on a surface of the second mask layer; forming a flank covering a sidewall of the second etched pattern; removing the third mask layer to form a third etched pattern between adjacent flanks; etching the first mask layer along the third etched pattern to form a fourth etched pattern in the first mask layer; and etching the substrate along the first etched pattern and the fourth etched pattern, to form multiple active regions in the substrate.

Abstract: Disclosed herein are compounds comprising an electrophilic moiety and rigid moiety for use in modulating an activity of Pin1. The rigid moiety comprises at least one functional group that is capable of forming hydrogen bonds with hydrogen atoms, wherein the electrophilic moiety and the rigid moiety are arranged such that the electrophilic moiety is capable of covalently binding to the Cys113 residue of Pin1, and the rigid moiety is capable of forming hydrogen bonds with the Gln131 and His 157 residues of Pin1. Further disclosed are novel compounds having Formula Id: wherein the dashed line, W, X, Y, Z, Ra-Rc, R1, R2, L1, L2 and n are as defined herein, and libraries comprising such compounds. Further disclosed are methods of identifying a compound capable of modulating an activity of Pin1, by screening a library of compounds.

Abstract: The embodiments provide a semiconductor structure and a fabrication method thereof. The semiconductor structure includes: a substrate including an active region and a shallow trench isolation region spaced apart from each other; a plurality of isolation structures arranged on a surface of the substrate; a plurality of grooves arranged between the plurality of isolation structures, wherein a bottom of the groove has a first inclined plane, and the first inclined plane is formed in the active region; and a conductive plug arranged in the groove. According to embodiments of the present disclosure, it is avoidable that an air gap is formed inside a polycrystalline silicon in the fabrication process of a storage node contact (SNC) structure.

Abstract: The invention features compositions and methods for inhibiting the Pin1 protein, and the treatment of disorders characterized by elevated Pin1 levels.

Abstract: Shoe covers that include a waterproof sock shaped unitary tubular member. The shoe covers are configured to cover footwear having a sole with a bottom. The member includes a first waterproof tubular portion that has an upper opening configured to receive an ankle and a heel of a foot of a person when the footwear and shoe cover are donned. The member further includes a second waterproof tubular portion that has a bottom surface and is configured to correspond to and seal against the bottom of the sole of the footwear when the member is donned on the footwear. The bottom surface of the second waterproof tubular portion defines an opening. When the footwear is cycling footwear that includes a cleat projecting from the bottom, the opening may be configured to receive the cleat of the cycling footwear. Methods of donning and manufacturing the shoe covers also are disclosed.

Abstract: An apparatus is described. The apparatus includes a semiconductor chip having cross-talk noise cancellation circuitry disposed between a disturber trace and a trace to be protected from cross-talk noise emanating from the disturber trace. The trace is to be coupled to a receiver disposed on a different semiconductor chip.