Abstract: A battery protection chip, a polling detection method and a polling detection circuit based on a battery protection chip are provided. The circuit includes: a polling signal generator for generating first and second selection signals based on a basic clock signal, a plurality of state signals and a priority of a plurality of detection items. An input array selector selects one of a plurality of reference signals and one of a plurality of feedback signals to output to a comparator based on the first selection signal; the comparator compares the feedback reference signals and outputs an indication signal. An output sampler samples the indication signal according to the second selection signal and updates the plurality of state signals according to a sampling result.

Abstract: Disclosed are a high-temperature superconducting suspension type wireless power transmission device and an assembly method thereof. The device comprises an alternating current power supply, wherein the alternating current power supply is electrically connected with a transmitting coil, and the transmitting coil is made of high-temperature superconducting materials; a suspended matter is mounted above the transmitting coil, the suspended matter is electrically connected with a receiving coil corresponding to the transmitting coil, and a plurality of permanent magnets fixedly connected with the suspended matter are uniformly mounted along the periphery of the receiving coil; and the transmitting coil is located in a low-temperature container to maintain a superconducting state. In combination with the superconducting magnetic suspension technology and the superconducting wireless charging technology, power is stored without the need of a complex energy storage device.

Abstract: Various embodiments provide for determining redundant logic in a circuit design based on one or more enable conditions of clock gates, which can be part of electronic design automation (EDA). In particular, some embodiments use one or more enable conditions (of the clock gates) with a satisfiability solver to determine redundant logic coupled to clock circuit elements gated by the clock gates.

Abstract: In one aspect, use of compounds as active agents to treat a hearing impairment and to prevent a hearing impairment, and methods of treating and/or preventing hearing impairments or disorders using the compositions are disclosed. Momelotinib and Fedratinib exhibit excellent protection against antibiotic-induced hearing loss in zebrafish and mice when administered prophylactically. In one aspect, Momelotinib or Fedratinib can be used as a therapy for the treatment and/or prevention of hearing loss. This abstract is intended as a scanning tool for purposes of searching in the particular art and is not intended to be limiting of the present invention.

Abstract: In one aspect, use of compounds as active agents to treat a hearing impairment and to prevent a hearing impairment, and methods of treating and/or preventing hearing impairments or disorders using the compositions are disclosed. Momelotinib and Fedratinib exhibit excellent protection against antibiotic-induced hearing loss in zebrafish and mice when administered prophylactically. In one aspect, Momelotinib or Fedratinib can be used as a therapy for the treatment and/or prevention of hearing loss. This abstract is intended as a scanning tool for purposes of searching in the particular art and is not intended to be limiting of the present invention.

Abstract: In one aspect, use of compounds as active agents to treat a hearing impairment and to prevent a hearing impairment, and methods of treating and/or preventing hearing impairments or disorders using the compositions are disclosed. Momelotinib and Fedratinib exhibit excellent protection against antibiotic-induced hearing loss in zebrafish and mice when administered prophylactically. In one aspect, Momelotinib or Fedratinib can be used as a therapy for the treatment and/or prevention of hearing loss. This abstract is intended as a scanning tool for purposes of searching in the particular art and is not intended to be limiting of the present invention.

Abstract: Various embodiments provide for routing a circuit design using routing congestion based on fractional via cost, via density, or both in view of one or more design rules. For instance, some embodiments model via cost based on one or more design rules to determine routing congestion, where routing demand (e.g., routing capacity occupied by) of a via is fractional to the amount of the track blocked by the via. Additionally, some embodiments apply via density modeling based on one or more design rules to determine a routing demand of a via for routing congestion.

Abstract: Disclosed are a duplexer, a network device, a control method, an electronic device and a storage medium. The duplexer may include: a filter, a dielectric tuning component; and a control module connected with the dielectric tuning component and configured to control a relative position between the dielectric tuning component and the filter to adjust an operating frequency of the duplexer.

Abstract: Disclosed are a high-temperature superconducting suspension type wireless power transmission device and an assembly method thereof. The device comprises an alternating current power supply, wherein the alternating current power supply is electrically connected with a transmitting coil, and the transmitting coil is made of high-temperature superconducting materials; a suspended matter is mounted above the transmitting coil, the suspended matter is electrically connected with a receiving coil corresponding to the transmitting coil, and a plurality of permanent magnets fixedly connected with the suspended matter are uniformly mounted along the periphery of the receiving coil; and the transmitting coil is located in a low-temperature container to maintain a superconducting state. In combination with the superconducting magnetic suspension technology and the superconducting wireless charging technology, power is stored without the need of a complex energy storage device.

Abstract: A system includes a machine configured to perform operations including accessing an integrated circuit design including a buffer tree that interconnects a plurality of inputs and buffers. The buffer tree includes a baseline timing characteristic. The operations include identifying a set of candidate solutions for improving the baseline timing characteristic using an initial timing model and selecting a subset of candidate solutions that have a timing characteristic lower than the baseline timing characteristic. Then the subset of candidate solutions are evaluated using a detailed timing model and based on determining that at least one candidate solution in the subset has a timing characteristic that is better than the baseline timing characteristic, selecting a candidate solution from the set of candidate solutions, and updating the buffer tree based on the candidate solution.

Abstract: Various embodiments provide for routing a net of a circuit design using rule-based routing blockage extension, which may be part of electronic design automation (EDA). In particular, some embodiments route a net of a circuit design by determining a dimension extension value based on a design rule of the circuit design and applying the dimension extension value to at least one existing routing blockage.

Abstract: Aspects of the present disclosure address systems and methods for performing a machine-learning based clustering of clock sinks during clock tree synthesis. An integrated circuit (IC) design comprising a clock net that includes a plurality of clock sinks is accessed. An initial number of clusters to generate from the set of clock sinks is determined using a machine-learning model. A first set of clusters is generated from the set of clocks sinks and includes the initial number of clusters. A timing analysis is performed to determine whether each cluster in the first set of clusters satisfies design rule constraints. The initial number of clusters is adjusted based on the timing analysis and a clustering solution is generated based on the adjusted number of clusters.

Abstract: Various embodiments provide for clustering-based grouping of cells in a cell library, which can be used for pruning the cell library. In particular, various embodiments provide for a clustering-based grouping of cells in a cell library based on a criterion (or cell attribute), and for pruning of the cell library based on the grouping of cells, which can optimize the cell library for the criterion. For instance, some embodiments provide for a clustering-based grouping of cells based on leakage power and then applying cell library pruning to optimize for cell leakage power.

Abstract: The present invention provides constructs of the parainfluenza virus type-5 (PIV5) virus expressing the SARS-CoV-2 envelope spike (S) and nucleocapsid (N) proteins of SARS-CoV-2 variants for use as safe, stable, efficacious, and cost-effective vaccines against COVID-19.

Abstract: Various embodiments provide a system for performing operations that comprise accessing an integrated circuit design that includes a clock tree interconnecting a clock source to a plurality of clock sinks. The operations include receiving a request to adjust a present timing offset of the clock tree to a target timing offset. In response, a group of clock sinks to be adjusted are identified to satisfy the request. The clock tree is then modified by moving a terminal of the group from a first location in the clock tree to a second location in the clock tree to update the clock tree. An indication is provided that the updated clock tree has been modified and complies with the target timing offset.

Abstract: A preparation method of a granular adsorbent is provided, including the following: adding a pyrrole monomer to an acidic solution, and adding an oxidant as an initiator to allow a polymerization reaction of the pyrrole monomer to produce polypyrrole (PPy), where an adsorption material powder is added to a reaction system before, during, or immediately after the polymerization reaction, and a resulting mixture is thoroughly stirred; after the polymerization reaction is completed, filtering a resulting reaction system to obtain a filter cake, which is the granular adsorbent; or subjecting the resulting reaction system to centrifugal sedimentation to obtain the monolithic adsorbent. In the present disclosure, the pyrrole monomer is subjected to a polymerization reaction to generate PPy; before being tightly stacked, network structures of PPy wrap the adsorption material powder; and the granular adsorbent is formed through sedimentation and stacking.

Abstract: A pose tracking method and apparatus are disclosed. The pose tracking method includes obtaining an image of a trackable target having a plurality of markers, detecting first points in the obtained image to which the markers are projected, matching the first points and second points corresponding to positions of the markers in a coordinate system set based on the trackable target based on rotation information of the trackable target, and estimating a pose of the trackable target based on matching pairs of the first points and the second points.

Abstract: In some embodiments, an electronic device presents a weak password warning in a password management user interface that includes information about the user account with which the password is associated. In some embodiments, an electronic device presents a weak password warning in a login user interface.

Abstract: A switch control circuit a multiplexer switch circuit and a control method for a multiplexer switch control circuit are provided. The switch control circuit comprises a first control switch, a first capacitor and a field-effect transistor switch. When the first control switch is switched off, a charging voltage released by the first capacitor can control the switching-on of the field-effect transistor switch. At this moment, since the first control switch is switched off, and a power source signal cannot reach a gate electrode of the field-effect transistor switch, power source noise cannot be coupled to a line where source and drain electrodes of the field-effect transistor switch are located. Thus, in a discharge stage of the first capacitor, a discharge voltage can serve as a control signal to control the switching-on of the field-effect transistor switch.

Abstract: A system includes one or more processors and a computer storage medium storing instructions that cause a machine to perform operations including accessing an integrated circuit (IC) design including an initial clock tree. The operations include selecting a first driver to evaluate for resizing, the first driver being a first size and having a first leakage current and determining a baseline power consumption measurement of clock tree based on the first size and the first leakage current of the first driver. The operations include identifying a plurality of replacement drivers to replace the first driver and determining a power consumption measurement for a second driver. Based on determining that the power consumption measurement for the second driver is less than the baseline power consumption measurement replacing the first driver with the second driver and generating a layout instance based on the second driver.