Abstract: An integrated circuit (IC) design is accessed from a database in memory. The IC design comprises a route connecting a source to a sink. A set of buffering candidates for buffering are generated for the net. A timing improvement associated with a buffering candidate in the set of buffering candidates is determined using a first timing model. The buffering candidate is pruned from the set of buffering candidates based on the timing improvement and a cost associated with the buffering candidate. The pruned set of buffering candidates is evaluated using a second timing model, and a buffering solution for the net is selected from the pruned set of buffering candidates based on a result of the evaluating. The IC design is updated to include the buffering solution selected for the net.

Abstract: An integrated circuit (IC) design is accessed from a database in memory. The IC design comprises a routing topology for a net comprising interconnections between a set of pins. The IC design further comprises a set of candidate locations for inserting buffers. A set of cells from a cell library in memory is accessed. A candidate location from the set of candidate locations is assessed to determine whether at least one cell in the set of cells fits at the location. Based on determining that at least one cell in the set of cells fits at the candidate location, the location is marked as bufferable. A largest cell width that fits at the candidate location is determined based on the set of cells and a buffering solution is generated for the net using the largest cell width as a constraint on buffer insertion performed at the candidate location.

Abstract: A data processing method and device, and a computer readable storage medium, the data processing method, applied to a node in an Information-Centric Network (ICN), includes: acquiring a first offset address corresponding to a first ICN packet; querying a record pointed to by the first offset address and performing data processing according to a query result; the record pointed to by the first offset address is used to store a storage address of a second ICN packet or forwarding information of the second ICN packet in response to the second ICN packet corresponding to the first ICN packet being stored locally.

Abstract: A pose estimation method includes obtains an event stream from an event-based vision sensor configured to capture a target object to which light-emitting devices flickering at a predetermined first frequency are attached, obtains a polarity change period of at least one pixel based on the event stream, generates an image frame sequence using at least one target pixel having a polarity change period corresponding to the first frequency, among the at least one pixel, extracts a feature sequence including feature vectors corresponding to the at least one target pixel, from the image frame sequence, and estimates a pose sequence of the target object by applying the feature sequence to a deep neural network (DNN) model.

Abstract: A system includes a machine configured to perform operations including accessing an integrated circuit design including a buffer tree that interconnects a plurality of inputs and buffers. The buffer tree includes a baseline timing characteristic. The operations include identifying a set of candidate solutions for improving the baseline timing characteristic using an initial timing model and selecting a subset of candidate solutions that have a timing characteristic lower than the baseline timing characteristic. Then the subset of candidate solutions are evaluated using a detailed timing model and based on determining that at least one candidate solution in the subset has a timing characteristic that is better than the baseline timing characteristic, selecting a candidate solution from the set of candidate solutions, and updating the buffer tree based on the candidate solution.

Abstract: Various embodiments provide for routing a circuit design based on adjusting a routing demand. More specifically, some embodiments implement routing demand smoothing of a grid cell, routing overflow spreading of a grid cell, or some combination of both prior to detailed routing of a circuit design, which can result in improved detailed routing over conventional routing techniques.

Abstract: A method and apparatus for processing sparse points. The method includes determining spatial hierarchical point data based on a key point set and a local point set of a sparse point set, determining relationship feature data by encoding a spatial hierarchical relationship between points of the spatial hierarchical point data, generating a global feature and a local feature of the sparse point set through a conversion operation associated with the relationship feature data, and generating a processing result for the sparse point set based on the global feature and the local feature.

Abstract: An electronic device: displays an electronic form with a plurality of fields; detects an autofill input that corresponds to a field of the plurality of fields in the electronic form; and in response to detecting the autofill input, updates the electronic form to display fields that have been populated based on a user profile. If the autofill input is associated with a first category of information in the user profile, updating the electronic form includes populating at least two of the plurality of fields using information from the user profile that corresponds to the first category of information. If the autofill input is associated with a second category of information in the user profile, updating the electronic form includes populating at least two of the plurality of fields using information from the user profile that corresponds to the second category of information.

Abstract: A display substrate, a display panel and a method for manufacturing the display substrate are provided. The display substrate comprises a backing substrate and a plurality of pixel areas formed on the backing substrate, wherein the display substrate further comprises a quantum dot layer, the quantum dot layer comprises a plurality of quantum dot units located in the plurality of pixel areas respectively, wherein the quantum dot units comprise a matrix layer and quantum dots dispersed in the matrix layer, the matrix layer comprises a central region and a peripheral region disposed around the central region, the peripheral region comprises a polymer of photocurable monomers, and the central region comprises unpolymerized photocurable monomers.

Abstract: Various embodiments provide for determining clock gates for decloning based on simulation and a satisfiability solver, which can be part of electronic design automation (EDA). In particular, some embodiments use a simulation process to quickly determine whether enable signals associated with two clock gates are logically equivalent using a random input vector to a circuit design and, if logically equivalent by the simulation process, use a satisfiability solver to determine a variable assignment (e.g., at least one vector) such that the enable signals are found to be non-equivalent.

Abstract: A system for performing operations including accessing an integrated circuit design that includes a clock tree interconnecting a clock source to a plurality of clock sinks. The operations include receiving a request to adjust a current timing offset of the clock tree to a target timing offset. The clock tree is modified by moving a terminal of the group from a first location in the clock tree to a second location in the clock tree to generate an updated clock tree. During modification, the first and second locations are analyzed to determine a load reduction and increase at the respective terminals. One or more neighboring clock tree instances are adjusted to compensate for the load reduction and increase. The operations include providing an indication that the clock tree has been updated and complies with the target timing offset.

Abstract: An integrated circuit (IC) design is accessed from a database in memory. The IC design comprises an initial buffer tree for a net in the IC design. A maximum cost constraint for rebuffering the net is determined based on the initial buffer tree. A partial rebuffering solution is generated for net and a cost associated with the partial rebuffering solution is determined. Based on determining the cost of the partial rebuffering solution satisfies the maximum cost constraint, the partial rebuffering solution is saved in a set of partial rebuffering solutions for the net. A set of candidate rebuffering solutions for the net is generated based on the set of partial rebuffering solutions, and a rebuffering solution for the net is selected from the set of candidate rebuffering solutions. The database is updated to replace the initial buffer tree in the IC design with the rebuffering solution selected for the net.

Abstract: Aspects of the present disclosure address systems and methods for clock tree synthesis (CTS). A first iteration of CTS is performed to generate an intermediate clock tree for an integrated circuit (IC) design that includes one or more macros. Target pin insertion delays (PIDs) for the one or more macros are computed based on the intermediate clock tree using a linear program. A second iteration of CTS is performed using the target PIDs for the one or more macros to generate an optimized clock tree for the IC design.

Abstract: Aspects of the present disclosure address systems and methods for performing a machine-learning based clustering of dock sinks during clock tree synthesis. An integrated circuit design comprising a clock net that includes a plurality of clock sinks is accessed. A set of clusters are generated by clustering the set of clock objects of the clock net. A machine-learning model is used to assess whether each cluster satisfies one or more design rule constraints. Based on determining each cluster in the set of dusters is assessed by the machine-learning model to satisfy the one or more design rule constraints, a timing analysis is performed to determine whether each cluster in the set of clusters satisfies the target timing constraints. A clustering solution for the clock net is generated based on the set of clusters in response to determining each cluster satisfies the one or more design rule constraints.

Abstract: Aspects of the present disclosure address systems and methods for local cluster refinement for integrated circuit (IC) designs using a dynamic weighting scheme. Initial cluster definitions are accessed. The initial cluster definitions define a plurality of clusters where each cluster includes a plurality of pins. Each cluster is evaluated with respect to one or more design rule constraints. Based on the evaluation, clusters are identified from the plurality of clusters. A set of refinement candidates are generated based on the one or more clusters. A scoring function that employs a dynamic weighting scheme is used to determine a refinement quality score for each refinement candidate in the set of candidates and one or more refinement candidates are selected from among the set of refinement candidates based on respective refinement quality scores. A refined clustering solution is generated based on the selected refinement candidates.

Abstract: The present disclosure provides a bandpass filter based on effective localized surface plasmons (ELSPs) and an operation method thereof. The bandpass filter includes a metal ground plane on a lower portion and a dielectric substrate in a middle as well as microstrips and dielectric resonators on an upper portion, where the microstrips at two terminals are symmetric with each other; each dielectric resonator includes a cuboid dielectric body and two metal strips, where the two metal strips each the same as the cuboid dielectric body in length are respectively located in a middle of an upper surface and lower surface of the dielectric body; and two microstrips are respectively connected to the metal strips on lower surfaces of two dielectric resonators, so as to be used as ports for feeding.

Abstract: Various embodiments provide for clock network generation for a circuit design using an inverting integrated clock gate (ICG). According to some embodiments, a clock network with one or more inverting ICGs is generated, after a topology of the clock network is defined, by applying a non-inverting ICG-to-inverting ICG transform to one or more nodes of the clock network that comprise a non-inverting ICG. Additionally, according to some embodiments, a clock network is generated bottom-up (from the clock sinks to the root clock signal source) using one or more inverting ICGs.

Abstract: Various embodiments provide for clock network generation for a circuit design using a negative-edge integrated clock gate (ICG). According to some embodiments, a clock network with one or more negative-edge ICGs is generated, after a topology of the clock network is defined, by applying a positive-edge ICG-to-negative-edge ICG transform to one or more nodes of the clock network that comprise a positive-edge ICG. Additionally, according to some embodiments, a clock network is generated bottom-up (from the clock sinks to the root clock signal source) using one or more negative-edge ICGs.

Abstract: Various embodiments provide for layer assignment of a network of a circuit design based on a wirelength threshold, which can facilitate consideration of timing and electromigration and which may be part of electronic design automation (EDA) of a circuit design. More particularly, some embodiments determine (e.g., calculate) a wirelength threshold for a net (e.g., each net) of a circuit design based on one or more characteristics of the net, and select a layer for at least a portion of the net based on the wirelength threshold.