Abstract: The invention discloses a pixel structure and a pixel unit. The pixel structure includes a main electrode; and a plurality of branch electrodes connected to the main electrode; wherein the branch electrode includes a first branch electrode and a second branch electrode, an acute intersecting angle between the first branch electrode and the main electrode is a first angle, and an acute intersecting angle between the second branch electrode and the main electrode is a second angle. The invention solves the whitening phenomenon which occurs in the side view by designing the acute intersecting angle between the branch electrode and the main electrode as the first angle and the second angle.

Abstract: A pixel unit, a display panel and a display device are provided. The pixel unit includes: a first sub-pixel, comprising a first sub-region and a second sub-region; and a second sub-pixel, disposed adjacent to the first sub-pixel and comprising a third sub-region and a fourth sub-region; wherein the first sub-region is disposed adjacent to the third sub-region, and the second sub-region is disposed adjacent to the fourth sub-region; wherein a divided voltage of the first sub-region is same as a divided voltage of the third sub-region; the divided voltage of the first sub-region, a divided voltage of the second sub-region and a divided voltage of the fourth sub-region are different from one another. The pixel unit of the embodiment is advantageous for improving the washout and color shift problem of a larger side view angle and improving the optical characteristics of the viewing angle.

Abstract: Various embodiments provide for layer assignment of a network of a circuit design based on a resistance or capacitance characteristic, such as a resistance/capacitance characteristic associated with a layer, a wire, or a via of the circuit design. In particular, various embodiments consider a resistance/capacitance characteristic of a layer, a wire, or a via of a circuit design to determine a set of layers for routing one or more networks of the circuit design, which can enable some embodiments to route the networks on the layers within a certain range that has very close resistance/capacitance (RC) characteristics, and can permit routing each network on layers having the smallest RC characteristic difference.

Abstract: A method for driving a pixel matrix is provided, and the pixel matrix includes multiple sub-pixels arranged in a matrix. Voltages applied along any one of data lines change in polarity once every four sub-pixels or every two sub-pixels, any one of the data lines controls voltage inputs of sub-pixel respectively connected to two sides thereof or controls voltage inputs of two sub-pixels both connected to one side thereof. The method includes: receiving an image data and acquiring original pixel data according to the image data; generating a first driving voltage and a second driving voltage according to the original pixel data; and loading the first driving voltage or the second driving voltage to the pixel matrix along any one of the data lines. The invention also provides a display device corresponding to the method. The invention can avoid crosstalk, bright dark lines and improve display effect.

Abstract: A method and apparatus for processing sparse points. The method includes determining spatial hierarchical point data based on a key point set and a local point set of a sparse point set, determining relationship feature data by encoding a spatial hierarchical relationship between points of the spatial hierarchical point data, generating a global feature and a local feature of the sparse point set through a conversion operation associated with the relationship feature data, and generating a processing result for the sparse point set based on the global feature and the local feature.

Abstract: The present disclosure provides a bandpass filter based on effective localized surface plasmons (ELSPs) and an operation method thereof. The bandpass filter includes a metal ground plane on a lower portion and a dielectric substrate in a middle as well as microstrips and dielectric resonators on an upper portion, where the microstrips at two terminals are symmetric with each other; each dielectric resonator includes a cuboid dielectric body and two metal strips, where the two metal strips each the same as the cuboid dielectric body in length are respectively located in a middle of an upper surface and lower surface of the dielectric body; and two microstrips are respectively connected to the metal strips on lower surfaces of two dielectric resonators, so as to be used as ports for feeding.

Abstract: Various embodiments described herein provide for track assignment of wires of a network of a circuit design by dynamic programming. In particular, various embodiments use a dynamic programming process to determine a set of breaking points for a routing wire of a global-routed and layer-assigned circuit design, and to determine track assignments for each of the sub-wires (sub-routes) formed by applying the set of selected breaking points to the routing wire. This results in a set of track-assigned sub-wires (or track-assigned sub-routes), which various embodiments can connect together to generate a connected set of track-assigned sub-wires that can be used in place of the routing wire.

Abstract: A data processing method and device, and a computer readable storage medium, the data processing method, applied to a node in an Information-Centric Network (ICN), includes: acquiring a first offset address corresponding to a first ICN packet; querying a record pointed to by the first offset address and performing data processing according to a query result; the record pointed to by the first offset address is used to store a storage address of a second ICN packet or forwarding information of the second ICN packet in response to the second ICN packet corresponding to the first ICN packet being stored locally.

Abstract: A pixel unit, a display panel and a display device are provided. The pixel unit includes: a first sub-pixel, comprising a first sub-region and a second sub-region; and a second sub-pixel, disposed adjacent to the first sub-pixel and comprising a third sub-region and a fourth sub-region; wherein the first sub-region is disposed adjacent to the third sub-region, and the second sub-region is disposed adjacent to the fourth sub-region; wherein a divided voltage of the first sub-region is same as a divided voltage of the third sub-region; the divided voltage of the first sub-region, a divided voltage of the second sub-region and a divided voltage of the fourth sub-region are different from one another. The pixel unit of the embodiment is advantageous for improving the washout and color shift problem of a larger side view angle and improving the optical characteristics of the viewing angle.

Abstract: A method for driving a pixel matrix is provided, and the pixel matrix includes multiple sub-pixels arranged in a matrix. Voltages applied along any one of data lines change in polarity once every four sub-pixels or every two sub-pixels, any one of the data lines controls voltage inputs of sub-pixel respectively connected to two sides thereof or controls voltage inputs of two sub-pixels both connected to one side thereof. The method includes: receiving an image data and acquiring original pixel data according to the image data; generating a first driving voltage and a second driving voltage according to the original pixel data; and loading the first driving voltage or the second driving voltage to the pixel matrix along any one of the data lines. The invention also provides a display device corresponding to the method. The invention can avoid crosstalk, bright dark lines and improve display effect.

Abstract: Various embodiments provide for routing a network of a circuit design based on at least one of a placement blockage or a layer-assigned network of a circuit design. For instance, some embodiments route a network of a circuit design (e.g., clock net, date net) by generating a congestion map based on modeling layer-assigned networks, considering (e.g., accounting for) routing congestion based on a placement blockage of the circuit design, or some combination of both.

Abstract: Electronic design automation systems, methods, and media are presented for cell cloning during circuit design. In one embodiment, for a circuit design comprising a plurality of flip-flop elements having clock inputs provided by a routing tree, a delay is identified for each flip-flop element. The flip-flop elements are clustered by delay to generate at least two clusters of flip-flop elements. Elements within the clusters are then grouped by physical characteristics to generate delay groups of flip-flop elements. An updated routing tree is then generated for the circuit design using the first delay group and the second delay group.

Abstract: A pose tracking method and apparatus are disclosed. The pose tracking method includes obtaining an image of a trackable target having a plurality of markers, detecting first points in the obtained image to which the markers are projected, matching the first points and second points corresponding to positions of the markers in a coordinate system set based on the trackable target based on rotation information of the trackable target, and estimating a pose of the trackable target based on matching pairs of the first points and the second points.

Abstract: Aspects of the present disclosure address improved systems and methods for buffer insertion in an integrated circuit (IC) design using a cost function that accounts for edge spacing and stack via constraints associated with cells in the IC design. An integrated circuit (IC) design comprising a routing topology for a net is accessed. A set of candidate insertion locations along the routing topology are identified. A set of buffering candidates is generated based on the candidate insertion locations. A buffering candidate comprises a cell inserted at a candidate insertion location along the routing topology. A cost associated with the buffering candidate is determined based on a number of potential edge spacing conflicts and a number of stack vias associated with the cell. A buffering solution for the net is selected from the buffering candidate based on the cost associated with the buffering candidate.

Abstract: Electronic design automation systems, methods, and media are presented for multi-dimension clock gate design in clock tree synthesis. In one embodiment, an input list of clock gate types is accessed, and the list is then used in generating a clock gate matrix. A circuit design with a clock tree is then accessed. The multi-dimensional design involves automatically selecting, for a first clock gate of the routing tree, a first clock gate type from the clock gate matrix based on a size and associated area for the first clock gate type to select a drive strength value for the first clock gate in the routing tree. The first clock gate is then resized to generate a resized first clock gate using the clock gate matrix to adjust a first delay value associated with the first clock gate while maintaining the drive strength value.

Abstract: Aspects of the present disclosure address systems and methods for fixing clock tree design constraint violations. An initial clock tree is generated. The generating of the initial clock tree comprises routing a clock net using an initial value for a parameter that controls a priority ratio between total route length and a maximum source-to-sink route length in each net of the clock tree. A violation to a clock tree design constraint is detected in the clock net in the clock tree, and based on detecting the violation, a rerouting candidate is generated by rerouting the clock net using an adjusted value for the parameter. A target clock tree is selected based on a comparison of timing characteristics of the rerouting candidate with the clock tree design constraint.

Abstract: A system and method for providing an autonomous delivery vehicle (ADV) incorporated with intelligent ramp control is disclosed. The ADV is configured to make decisions to deploy/retract the ramps depending on some conditions around the ADV. The ADV comprising a computing device including a means for executing artificial intelligence (AI) software, a ramp system comprising a plurality of ramps, and a sensor assembly in communication with the computing device to collect environmental data around the ADV. The data is communicated to the AI software, which is configured to analyze the environmental data to detect one or more obstacles proximate to the plurality of ramps of the ADV. Further, AI software determines a decision to deploy/retract at least one ramp based on the analysis and transmits the decision to the computing device. The computing device is configured to manipulate each ramp to deploy/retract based on the received decision.

Abstract: Aspects of the present disclosure address improved systems and methods for rebuffering an integrated circuit (IC) design using a unified improvement scoring algorithm. A plurality of rebuffering candidates are generated based on an initial buffer tree in an integrated circuit (IC) design. A rebuffering candidate in the plurality of rebuffering candidates comprises a modified buffer tree based on the initial buffer tree. A buffering cost of each rebuffering candidate is determined. A reference buffer tree is selected from among the rebuffering candidates based on the buffering cost of each rebuffering candidate. An improvement score of each rebuffering candidate is determined based on the buffering cost of each rebuffering candidate relative to the reference buffer tree. A new buffer tree is selected from among the plurality of rebuffering candidates to replace the initial buffer tree based on the improvement score of each rebuffering candidate.

Abstract: Aspects of the present disclosure address improved systems and methods for runtime efficient circuit placement location selection as described herein. An example embodiment includes identifying, for each route of the one or more routes that interconnect the terminals of a circuit design with the one or more pins of a first circuit element, a corresponding set of movement positions along said each route to generate a set of movement configurations for the first circuit element. The set of movement configurations is analyzed to generate a plurality of location clusters from the set of movement configurations, and for each location cluster of the plurality of location clusters, identifying one or more selected movement configurations within said each cluster. The one or more selected movement configurations for said each cluster to select an updated movement configuration.

Abstract: An array substrate, a liquid crystal display panel and a display device are provided. The array substrate includes: a substrate; a common electrode and a gate electrode, both disposed on the substrate; and a shielding electrode, disposed on the common electrode and the gate electrode, wherein an orthographic projection of the shielding electrode on the substrate is overlapped with an orthographic projection of the gate electrode on the substrate as well as an orthographic projection of the common electrode on the substrate, and the shielding electrode is electrically connected to the common electrode. In the embodiment of the disclosure, the shielding electrode is disposed on the common electrode and the gate electrode, so that the influence of the voltage difference formed by the gate electrode and the common electrode can be effectively shielded, thereby eliminating the phenomenon of push mura.