Abstract: A pose estimation method includes obtains an event stream from an event-based vision sensor configured to capture a target object to which light-emitting devices flickering at a predetermined first frequency are attached, obtains a polarity change period of at least one pixel based on the event stream, generates an image frame sequence using at least one target pixel having a polarity change period corresponding to the first frequency, among the at least one pixel, extracts a feature sequence including feature vectors corresponding to the at least one target pixel, from the image frame sequence, and estimates a pose sequence of the target object by applying the feature sequence to a deep neural network (DNN) model.

Abstract: A server receives a request for a business account with the messaging system that includes a business name and a contact point. The server determines whether users of the messaging system associate the business name with the contact point. The server also determines whether the business name and/or the contact point has characteristics consistent with the request originating from a genuine business. The business account is validated if users of the messaging system associate the business name with the contact point and at least one of the business name or the contact point have characteristics consistent with the request originating from a genuine business. The business account profile is updated to indicate it is verified. Client devices are adapted to display messages from the business account in conjunction with a visual indicator that the business account is verified.

Abstract: Electronic design automation systems, methods, and media are presented for clock gate placement with data path awareness. One embodiment involves accessing a circuit design with a clock tree, clock gates, and an initial movement area. A set of positions for a set of data path connection points associated with the data routing lines are identified, along with an expansion direction from the initial placement position toward the set of positions for the set of data path connection points, and the initial movement is expanded to consider additional placement options for the clock gate based on the data path connection points.

Abstract: Various embodiments provide for routing a network of a circuit design based on at least one of via spacing or pin density. For instance, some embodiments route a net of a circuit design (e.g., data nets, clock nets) by generating a congestion map based on modeling via spacing, modeling pin density, or some combination of both.

Abstract: Various embodiments provide for assigning a clock pin to a clock tap within a circuit design based on connectivity between circuit devices of the circuit design. For some embodiments, an initial clock tap assignment, between a clock tap of a circuit design and a clock pin of the circuit design, is accessed as input, and a modified clock tap assignment (between the clock tap and another clock pin of the circuit design) can be generated based on one or more of the following considerations: a clock tap assignment should try to assign clock pins of connected circuit devices to the same clock tap; a clock tap assignment should try to assign clock pins of connected circuit devices having the critical timing problems; a clock tap assignment should try to assign clock pins of connected circuit devices to clock taps with longer common path length.

Abstract: Electronic design automation systems, methods, and media are presented for slack scheduling. Some embodiments analyzing slack values at the input and output of a circuit element across multiple views. A skew value is then selected which maximizes the slack at the input and output of the circuit element across all views. In some embodiments, this selection operation is streamlined by first identifying skew ranges that preserve a local worst negative slack, and the selected skew value to maximize the slacks is chosen from the identified skew ranges, in order to limit the computational resources in identifying the skew which maximizes the minimum slack value. An updated circuit design and associated circuitry may then be generated.

Abstract: Aspects of the present disclosure address improved systems and methods for layer assignment to improve timing in integrated circuit (IC) designs. An initial placement layout of a net of an IC design is accessed. A plurality of buffer insertion candidates is generated using multiple candidate buffer insertion points and multiple layer assignments from among multiple layers of the IC design. Timing characteristics of each buffer insertion candidate are determined, and timing improvements provided by each buffer insertion candidate are determined based on respective timing characteristics. A buffer insertion candidate is selected from the plurality of buffer insertion candidates based on the timing improvement provided by the buffer insertion candidate. A layout instance for the IC is generated based in part on the selected buffer insertion candidate.

Abstract: In some embodiments, an electronic device presents a weak password warning in a password management user interface that includes information about the user account with which the password is associated. In some embodiments, an electronic device presents a weak password warning in a login user interface.

Abstract: The present invention discloses a method for driving a pixel matrix, the pixel matrix includes a plurality of sub-pixels arranged in a matrix, the method including: receiving an image data, and acquiring original pixel data according to the image data; generating a first driving voltage and a second driving voltage according to the original pixel data; and loading the first driving voltage or the second driving voltage to the pixel matrix in a data line direction within one frame. The invention avoids crosstalk, bright and dark lines, and improves the display effect.

Abstract: A method for driving a pixel matrix is provided, and the pixel matrix includes multiple sub-pixels arranged in a matrix. Voltages applied along any one of data lines change in polarity once every four sub-pixels or every two sub-pixels, any one of the data lines controls voltage inputs of sub-pixel respectively connected to two sides thereof or controls voltage inputs of two sub-pixels both connected to one side thereof. The method includes: receiving an image data and acquiring original pixel data according to the image data; generating a first driving voltage and a second driving voltage according to the original pixel data; and loading the first driving voltage or the second driving voltage to the pixel matrix along any one of the data lines. The invention also provides a display device corresponding to the method. The invention can avoid crosstalk, bright dark lines and improve display effect.

Abstract: The invention discloses a pixel structure including: a main electrode, and a plurality of branch electrodes connected to the main electrode; wherein closed areas and open areas are formed among the plurality of the branch electrodes. The invention solves the problem that the liquid crystal at the edge position of the peripheral closed design scheme is easily affected by the electric field and the alignment disorder occurs by designing the branch electrode in the ITO electrode as the closed area and the open area, so that the display is uniform and the display effect is improved. Further, with respect to the design of the peripheral opening, the invention reduces the number of black streaks and increases the light transmittance due to the closed areas and the open areas of the interval distribution.

Abstract: Electronic design automation systems, methods, and media are presented for a waveform propagation timing model for use with circuit designs and electronic design automation (EDA). One embodiment involves generating a gate output waveform for a circuit element using a driver input signal waveform and then generating a circuit element output waveform using the gate output waveform and an N-pole model of an interconnect with the first circuit element using moment matching. Timing values are then determined from the circuit element output waveform, such as delay and slew values. This waveform may then be propagated through the circuit, and an updated design generated using the timing values estimated from the modeled waveforms.

Abstract: Aspects of the present disclosure address systems and methods for shortening clock-tree wirelength based on target offsets in connected routes. A clock tree comprising routes that interconnect a plurality of clock-tree instances is accessed from memory. A clock-tree instance is selected for evaluation. A baseline power consumption measurement corresponding to a sub-tree of the clock-tree instance with the clock-tree instance at a first size is determined. An alternative power consumption measurement corresponding to the sub-tree of the clock-tree instance with the clock-tree instance at a second size is determined. Based on determining that the baseline power consumption measurement is less than the alternative power consumption measurement, the clock-tree instance is resized according to the second size.

Abstract: An array substrate, a liquid crystal display panel and a display device are provided. The array substrate includes: a substrate; a common electrode and a gate electrode, both disposed on the substrate; and a shielding electrode, disposed on the common electrode and the gate electrode, wherein an orthographic projection of the shielding electrode on the substrate is overlapped with an orthographic projection of the gate electrode on the substrate as well as an orthographic projection of the common electrode on the substrate, and the shielding electrode is electrically connected to the common electrode. In the embodiment of the disclosure, the shielding electrode is disposed on the common electrode and the gate electrode, so that the influence of the voltage difference formed by the gate electrode and the common electrode can be effectively shielded, thereby eliminating the phenomenon of push mura.

Abstract: Aspects of the present disclosure address improved systems and methods for core-route-based clock tree wirelength reduction. A method may include accessing an integrated circuit design comprising a clock tree comprising routes that interconnect terminals of a plurality of clock tree instances. The method further includes identifying a core route in the clock tree. The method further includes determining a first offset based on a distance between the first terminal and the core route and determining a second offset based on a distance from the second terminal to the core route. The method further includes determining a target offset based on a combination of the first and second offsets and moving the clock tree instance toward the core route by the target offset.

Abstract: The present disclosure relates to a system and method for routing in an electronic circuit design. Embodiments may include providing, using a processor, a hierarchical electronic design having a plurality of partitions, at least one routing blockage, a source pin location, and one or more sink pin locations. Embodiments may also include generating a routing wire network configured to connect the source pin location and the one or more sink pin locations to create one or more segments, wherein generating the routing wire network includes creating two or more feed-through ports at one or more of the plurality of partitions. Embodiments may further include applying a maze-routing approach to each of the one or more segments of the routing wire network to form a routed net associated with the hierarchical electronic design.

Abstract: Aspects of the present disclosure address improved systems and methods for generating a clock tree based on route-driven placement of fan-out clock drivers. Consistent with some embodiments, a method may include constructing a spanning tree comprising one or more paths that interconnect a set of clock sinks of a clock net of an integrated circuit device design. The method further includes calculating a center of the set of the clock sinks based on clock sink locations in the integrated circuit device design and identifying a point on the spanning tree nearest to the center of the set of clock sinks. The method further includes generating a clock tree by placing a clock driver at the point on the spanning tree that is nearest to the center of the set of clock sinks.

Abstract: Aspects of the present disclosure address systems and methods for shortening clock tree wirelength based on target offsets in connected routes. A method may include accessing a clock tree comprising routes that interconnect a plurality of pins. Each pin corresponds to a terminal of a clock tree instance. The method further includes identifying a first and second terminal of a clock tree instance in the clock tree. The method further includes determining a first offset based on a distance between the first terminal and a branch in a first route connected to the first terminal and determining a second offset based on a distance between the second terminal and a branch in a second route connected to the second terminal. The method further includes moving the clock tree instance from a first location to a second location based on a target offset determined by comparing the first and second offsets.

Abstract: Systems, methods, media, and other such embodiments described herein relate to generation of routing trees. One embodiment involves accessing a circuit design with a source and a plurality of sinks, and then using a first bottom-up wavefront analysis to select branch point candidates for the sinks. A branch point cost function is used to select among the branch point candidates. This process may be repeated until a final tier of analysis results in a final wavefront that is within a threshold distance of the source. The selected branch points are then used in generating a routing tree between the source and the sinks. In various different embodiments, different cost point functions may be used, and different operations used to manage obstructions or other specific routing considerations.

Abstract: Various embodiments provide for circuit design routing based on parallel run length (PRL) rules. In particular, a plurality of PRL rules is accessed and used to generate a set of additional routing blockages around an existing routing blockage of the circuit design. The additional routing blockages can be positioned relative to the existing routing blockage. During routing, the set of additional routing blockages can be modeled into a capacity map, which is then used by global to generate routing guide(s) between at least two nodes of the circuit design. In doing so, the various embodiments can assist in routing a wire while avoiding violation of the plurality of PRL rules with respect to the existing blockage, can speed up performance of global routing, can make it easier for detailed routing to honor routing guides produced by global routing, and can speed up performance of detailed routing in resolving DRC violations.