Fabrication of RRAM Cell Using CMOS Compatible Processes
Generally, the subject matter disclosed herein relates to the fabrication of an RRAM cell using CMOS compatible processes. A resistance random access memory device is disclosed which includes a semiconducting substrate, a top electrode, at least one metal silicide bottom electrode formed at least partially in the substrate, wherein at least a portion of the at least one bottom electrode is positioned below the top electrode, and at least one insulating layer positioned between the top electrode and at least a portion of the at least one bottom electrode. A method of making a resistance random access memory device is disclosed that includes forming an isolation structure in a semiconducting substrate to thereby define an enclosed area, performing at least one ion implantation process to implant dopant atoms into the substrate within the enclosed area, after performing the at least one ion implantation process, forming a layer of refractory metal above at least portions of the substrate, and performing at least one heat treatment process to form at least one metal silicide bottom electrode at least partially in the substrate, wherein at least a portion of the at least one bottom electrode is positioned below at least a portion of a top electrode of the device.
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1. Field of the Disclosure
Generally, the present disclosure relates to sophisticated integrated circuits, and, more particularly, to the fabrication of an RRAM cell with, in one embodiment, one or more bottom electrodes formed by silicidation using CMOS compatible processes.
2. Description of the Related Art
Memory circuits and devices are widely used in the electronics industry. In general, memory devices permit the storage of a “bit” of information, i.e., a “1” (logically high) or a “0” (logically low) signal. Vast numbers of these memory devices are formed on a single chip so as to permit the storage of a vast quantity of digital information. Various forms of such devices, and read/write circuitry employed with such devices, have been used in the industry for years, e.g., RAM (Random Access Memory) devices, ROM (Read Only Memory) devices, EEPROM (Electrically Erasable Read Only Memory) devices, etc.
Nonvolatile memory is a type of memory that retains stored data when power is removed from the memory device. Such nonvolatile memory devices are widely employed in mobile communication devices, computers, memory cards, etc. Flash memory is an example of one type of nonvolatile memory that is greatly used in such modern electronic devices.
More recently, another form of memory, RRAM (Resistance Random Access Memory) has been introduced to the industry.
Importantly, as noted above, the prior art RRAM device 100 is made using a traditional layer-by-layer approach that involves many discrete deposition, lithography and etching steps, perhaps for each layer of the device. Such a layered construction of the prior art RRAM device 100 makes it more difficult to incorporate it into integrated circuit devices that are manufactured using modern CMOS processing technology and methods. For example, fabrication of an RRAM device using the layer-by-layer approach may result in the overall height of the RRAM device 100 being greater than the height of other structures that are formed in traditional CMOS-type devices, such as PMOS and NMOS transistors. Such height differences can lead to patterning errors in photolithography operations and/or mandate additional processing steps be taken to avoid or reduce the adverse effects of such height differences, e.g., the performance of one or more additional deposition and planarization processes.
The present disclosure relates to methods and devices for avoiding or at least reducing the effects of one or more of the problems identified above.
SUMMARY OF THE DISCLOSUREThe following presents a simplified summary of the present disclosure in order to provide a basic understanding of some aspects disclosed herein. This summary is not an exhaustive overview of the disclosure, nor is it intended to identify key or critical elements of the subject matter disclosed here. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.
Generally, the subject matter disclosed herein relates to the fabrication of an RRAM cell using CMOS compatible processes. In the disclosed examples, the RRAM devices disclosed herein may be of a single bit or a dual bit configuration. In one illustrative embodiment, a resistance random access memory device is disclosed which includes a semiconducting substrate, a metal silicide top electrode positioned above the substrate, a single metal silicide bottom electrode formed at least partially in said substrate, wherein at least a portion of the single bottom electrode is positioned below an entire width of the top electrode and at least one insulating layer positioned between the top electrode and single bottom electrode. In another illustrative example, a resistance random access memory device includes a semiconducting substrate, and a metal silicide top electrode positioned above the substrate. The illustrative device further includes two separated metal silicide bottom electrodes formed at least partially in the substrate, wherein at least a portion of each of the two bottom electrodes is positioned below separate portions of the top electrode, and at least one insulating layer positioned between the portions of the top electrode and the portions of each of the two bottom electrodes that are positioned below the top electrode.
A method of making a resistance random access memory device including a top electrode is also disclosed which includes forming an isolation structure in a semiconducting substrate to thereby define an enclosed area, performing at least one ion implantation process to implant dopant atoms into the substrate within the enclosed area, after performing the at least one ion implantation process, forming a layer of refractory metal above at least portions of the substrate, and performing at least one heat treatment process to form at least one metal silicide bottom electrode at least partially in the substrate, wherein at least a portion of the at least one bottom electrode is positioned below at least a portion of a top electrode of the device.
The disclosure may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:
While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
DETAILED DESCRIPTIONVarious illustrative embodiments of the present subject matter are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.
The present subject matter will now be described with reference to the attached figures. Various structures and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present disclosure with details that are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present disclosure. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary and customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition will be expressly set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase.
As shown in
The insulation layer 210B depicted in
In the illustrative embodiment depicted in
As noted previously, the embodiment depicted in
One illustrative method of forming the RRAM devices disclosed herein will now be discussed with reference to
Next, as shown in
Next, as shown in
The thickness of the layer of refractory metal 220 and/or the parameters of the heat treatment process, e.g., temperature and/or duration, may be varied to achieve either the single-bit construction (a single bottom electrode 208) depicted in
Thereafter, as shown in
Various memory cell layouts are possible with the RRAM devices 200 disclosed herein. For example, using the illustrative dual-bit configuration RRAM device 200 depicted in
The operation of the RRAM devices 200 disclosed herein will now be discussed with reference to
In general, a voltage (Vg) is applied to the top electrode 206 of the RRAM devices 200 disclosed herein to establish or create one or more schematically depicted conductive paths 240 between the top electrode 206 and the bottom electrode 208, which is grounded. More specifically, in one example, by applying a positive voltage (Vg) of approximately 3 volts to the top electrode 206, the insulation layer 210 breaks down, and one or more of the conductive paths 240 are created. The conductive paths 240 can be switched off or closed by applying a reverse voltage of the opposite polarity, e.g., −3 volts, to the top electrode 206.
The exact number, size and location of the conductive paths 240 created during this process are unknown, and they may vary depending upon the particular materials used and the voltages applied to the top electrode 206. Moreover, such characteristics of the conductive paths 240 may vary depending upon the particular application. The exact mechanism by which the conductive paths 240 are established and broken is still a matter of investigation. See, e.g., W. H. Liu et al., “Observation of Switching Behaviors in Post-Breakdown Conduction in NiSi-gated Stacks,” June 2009, and N. Raghavan et al., “Unipolar Recovery of Dielectric Breakdown in Fully Silicided High-K Gate Stack Devices and its Reliability Implications,” published online Apr. 5, 2010, both of which are hereby incorporated by reference in their entirety. One possible mechanism that explains the formation of the conductive paths 240 is the movement of negatively charged oxygen ions from the insulation layer 210 to the top electrode 206 when a positive voltage is applied to the top electrode 206. These negatively charged oxygen ions are stored in the top electrode 206 during this process. When a negative voltage is applied to the top electrode 206, the negatively charged oxygen ions are effectively repelled from the top electrode 206 and driven back toward the insulating layer 210, thereby breaking the conductive path 240. Another possible mechanism for establishment of the conductive path(s) 240 is that one or more metal filaments are formed that conductively connect to the top electrode 206 and the bottom electrode 208.
The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Accordingly, the protection sought herein is as set forth in the claims below.
Claims
1. A resistance random access memory device, comprising:
- a semiconducting substrate;
- a metal silicide top electrode positioned above said substrate;
- a single metal silicide bottom electrode formed at least partially in said substrate, wherein at least a portion of said single bottom electrode is positioned below an entire width of said top electrode; and
- at least one insulating layer positioned between said top electrode and said single bottom electrode.
2. The device of claim 1, wherein said top electrode and said single bottom electrode are made of the same metal silicide material.
3. The device of claim 1, wherein said top electrode and said single bottom electrode are made of different metal silicide materials.
4. The device of claim 1, wherein said single bottom electrode is bounded by an isolation structure positioned in said substrate that surrounds said device.
5. A resistance random access memory device, comprising:
- a semiconducting substrate;
- a metal silicide top electrode positioned above said substrate;
- two separated metal silicide bottom electrodes formed at least partially in said substrate, wherein at least a portion of each of said two bottom electrodes is positioned below separate portions of said top electrode; and
- at least one insulating layer positioned between said portions of said top electrode and said at least said portion of each of said two bottom electrodes.
6. The device of claim 5, wherein said top electrode and each of said two bottom electrodes are made of nickel silicide.
7. The device of claim 5, wherein said two bottom electrodes are bounded by an isolation structure positioned in said substrate that surrounds said device.
8. The device of claim 5, wherein said at least one insulating layer is comprised of a single layer of a high-k dielectric material.
9. A method of making a resistance random access memory device comprising a top electrode, comprising:
- forming an isolation structure in a semiconducting substrate to thereby define an enclosed area;
- performing at least one ion implantation process to implant dopant atoms into said substrate within said enclosed area;
- after performing said at least one ion implantation process, forming a layer of refractory metal above at least portions of said substrate; and
- performing at least one heat treatment process to form at least one metal silicide bottom electrode at least partially in said substrate, wherein at least a portion of said at least one bottom electrode is positioned below at least a portion of said top electrode.
10. The method of claim 9, wherein said dopant atoms are arsenic.
11. The method of claim 9, wherein said top electrode and said at least one bottom electrode are made of nickel silicide.
12. The method of claim 9, wherein said at least one bottom electrode comprises two bottom electrodes that are separated from one another, wherein at least a portion of each of said two bottom electrodes is positioned below a portion of said top electrode.
13. The method of claim 9, wherein said at least one bottom electrode is a single bottom electrode.
14. The method of claim 13, wherein a portion of said single bottom electrode is positioned under an entire width of said top electrode.
15. The method of claim 14, wherein said single bottom electrode is bounded by an isolation structure in said substrate that surrounds said device.
16. A method of making a resistance random access memory device comprising a top electrode, comprising:
- forming an isolation structure in a semiconducting substrate to thereby define an enclosed area;
- forming said top electrode for said device above said enclosed area;
- after forming said top electrode, performing at least one ion implantation process to implant dopant atoms into said substrate within said enclosed area;
- after performing said at least one ion implantation process, forming a layer of refractory metal above said top electrode and at least portions of said substrate; and
- performing at least one heat treatment process to form at least one metal silicide bottom electrode at least partially in said substrate, wherein at least a portion of said at least one bottom electrode is positioned below at least a portion of said top electrode.
17. The method of claim 16, wherein said top electrode and said at least one bottom electrode are made of nickel silicide.
18. The method of claim 16, wherein said at least one bottom electrode comprises two bottom electrodes that are separated from one another, wherein at least a portion of each of said two bottom electrodes is positioned below a portion of said top electrode.
19. The method of claim 16, wherein said at least one bottom electrode is a single bottom electrode.
20. The method of claim 19, wherein a portion of said single bottom electrode is positioned under an entire width of said top electrode.
21. The method of claim 20, wherein said single bottom electrode is bounded by an isolation structure in said substrate that surrounds said device.
22. An array of resistance random access memory device, comprising:
- a semiconducting substrate;
- at least first and second resistance random memory devices formed in and above said substrate, each of said resistance random memory devices comprising two separated metal silicide bottom electrodes formed at least partially in said substrate; and
- a common top electrode structure that is electrically and operatively coupled to each of said separated metal silicide bottom electrodes.
23. The array of claim 22 wherein at least a portion of each of said two bottom electrodes is positioned below separate portions of said common top electrode.
24. The array of claim 23 further comprising at least one insulating layer positioned between said portions of said common top electrode and said at least said portion of each of said two bottom electrodes.
25. The array of claim 1, wherein said memory array defines a 2×2 memory cell.
26. The array of claim 1, wherein said memory array defines a 2×3 memory cell.
27. The array of claim 1, wherein said memory array defines a 3×3 memory cell.
Type: Application
Filed: Mar 21, 2011
Publication Date: Sep 27, 2012
Applicants: NANYANG TECHNOLOGICAL UNIVERSITY (Singapore), GLOBALFOUNDRIES SINGAPORE PTE LTD (Singapore)
Inventors: Wenhu Liu (Singapore), Kin-Leong Pey (Singapore), Nagarajan Raghavan (Singapore), Chee Mang Ng (Singapore)
Application Number: 13/052,864
International Classification: H01L 45/00 (20060101); H01L 21/02 (20060101);