Apparatus and method for shifting signal levels

Abstract

The electronic circuit (100) of the invention receives first signals DATA (170) having logical "1" at high (VCCH) or low (VCCL) levels and logical "0" at reference level (ZERO) and generates second signals OUT (186) between high level (VCCH) and reference level (ZERO) without changing the information. The circuit comprises a first switch (161) and a second switch (161) serially coupled together to a common output node (103). The first switch (162) is controlled by a control signal (CTRL) derived from DATA, OUT, or optionally from a clock signal CLK. The first switch (161) is switched off before the second switch (162) is switched off. Contention (conducting at the same time) is thereby avoided and the first switch (161) and the second switch (162) can be implemented by substantially equal-sized components.

Claims

1. An apparatus receiving a first signal with a first excursion, said apparatus having a first portion and a second portion for providing a second signal responding to said first signal, said second signal having a second excursion which is greater than said first excursion,

said apparatus CHARACTERIZED IN THAT

said first portion has a control block which receives said first signal and transfers said first excursion into a third excursion for switching said first portion on and off, whereby said first signal toggling in a first direction switches on said first portion, and whereby said control block switches off said first portion after a time delay, said time delay beginning when said second signal has been pulled to a first reference line and ending before said second portion is switched on again, thus bringing said apparatus into a state in which said first portion and said second portion are both switched off and whereby contention is avoided when said first signal toggling in a second direction switches on said second portion.

2. The apparatus of claim 1 wherein the length of said time delay is determined by a delay block receiving said second signal.

3. The apparatus of claim 1 operating as a transfer gate wherein said second signal is logical equal to said first signal as long as a third signal supplied to apparatus is at a first logical state.

4. The apparatus of claim 1 wherein said control block comprises a latch block receiving a third signal, and wherein said first portion is switched off when said third signal toggles.

5. The apparatus of claim 1 wherein said control block comprises a switch-off-block which switches said first portion off when said first signal toggles back in said second direction.

6. The apparatus of claim 1 wherein said first portion comprises at least a P-channel field effect transistor for pulling an output node to a first reference line and wherein said second portion comprises at least a N-channel field effect transistor and wherein in said control block said first excursion is transferred into said third excursion which is supplied to an input of said P-channel field effect transistor only by additional N-channel field effect transistors but not by additional P-channel field effect transistors.

7. An apparatus receiving a first signal and providing a second signal responsive to said first signal, whereby the excursion of said first signal is amplified,

said apparatus receiving a third signal arriving after said first signal,

said apparatus CHARACTERIZED IN THAT

a first signal level of said second signal is provided by a first transistor of a first type which is switched on by a first intermediate signal which is derived from a first serial arrangement of a first transistor of a second opposite type receiving said first signal and of a second transistor of said second type receiving said third signal;

a second signal level of said second signal is provided by a second serial arrangement of a third transistor of said second type receiving an inverted form of said first signal and a fourth transistor of said second type receiving said third signal; and

said first serial arrangement is coupled to an input of said first transistor of said first type without an intervening transistor of said first type.

8. The apparatus of claim 7 wherein said transistors of said first type are P-channel field effect transistors and said transistors of said second type are N-channel field effect transistors.

9. The apparatus of claim 7 wherein a latch block is coupled to the gate of said first transistor of said first type which keeps said first transistor of said first type switched on and switches said transistor of said first type off when said second signal toggles back.

10. The apparatus of claim 7 wherein a switch-off block is coupled to the gate of said first transistor of said first type which switches said first transistor of said first type off when said first signal toggles back.

11. An apparatus comprising a first transistor of a first type and a first transistor of a second type for amplifying a first signal having a first excursion to a second signal having a second excursion,

said apparatus CHARACTERIZED IN THAT

said first transistor of said first type and said first transistor of said second type are coupled serially between a first reference line and a second reference line via an output node carrying said second signal, that

said first excursion of said first signal is sufficient to switch said first transistor of said second type on and off and sufficient to switch said first transistor of said first type on but not off, that

said first signal is received and transferred to an input of said first transistor of said first type by at least a third transistor of said second type but not of said first type, and that

a fourth transistor controlled from said output node provides an intermediate signal which switches said first transistor of said first type off a first delay time after said first transistor of said first type has been switched on.

12. The apparatus of claim 11 wherein said fourth transistor is a transistor of said first type.

13. The apparatus of claim 11 wherein said fourth transistor has a gate coupled to said output node and a drain coupled to a gate of said first transistor.

14. A method for amplifying a first signal to a second signal by an apparatus, wherein said first signal alternates between a first logical state and a second logical state and assumes said second logical state during a first time interval, wherein said apparatus comprises a first transistor of a first type and a first transistor of a second type for providing said second signal, said method comprising the steps of:

transmitting said first signal in said second logical state through a second transistor of said second type but not through a transistor of said first type to an input of said first transistor of said first type and thereby making said first transistor of said first type conductive;

initiating a time delay when said first transistor of said first type becomes conductive, said time delay being determined by an inverter receiving said second signal and said time delay being shorter than said first time interval;

providing a control signal by said inverter at the end of said time delay to said first transistor of said first type and making said first transistor of said first type non-conductive; and

making said first transistor of said second type conductive when said first signal assumes said first logical state, whereby said first transistor of said first type and said first transistor of said second type are non-conductive after said time delay, thus providing contention.

15. The method of claim 14 wherein in said apparatus said first transistor of said first type is a P-channel field effect transistor and said first transistor of said second type is a N-channel field effect transistor, said transistors having their drains coupled together at an output node and their sources coupled to a first reference line and to a second reference line, respectively, and wherein said inverter is coupled to said first reference line and has (i) an input coupled to said output node for receiving said second signal to initiate said time delay and (ii) an output coupled to a gate of a second transistor of said first type, said second transistor of said second type connecting a gate of said first transistor of said first type to said first reference line at the end of said time delay so that said first transistor of said first type is switched off completely.

16. The method of claim 14 wherein in said step of transmitting said first signal said first transistor of said first type becomes completely conductive so that said second signal goes to a first signal level which is substantially equal to that of a first reference line to which an electrode of said first transistor of said first type is connected to.

17. A circuit receiving an input signal and providing an output signal, said circuit comprising:

a first switch coupled between a first reference line and an output node, said first switch controlled by said input signal and when conductive providing said output signal in a first state by pulling said output node to said first reference line;

a second switch coupled between said output node and a second reference line, said second switch controlled by said input signal and when conductive providing said output signal in a second state by pulling said output node to said second reference line; and

a feedback unit coupled to said output node, said feedback unit providing a control signal to said first switch which makes said first switch non-conductive a time delay after said first switch has been conductive so that when said input signal makes said second switch conductive, said first switch is already non-conductive.