Porous silicon electro-etching system and method
It is an object of this disclosure to provide high productivity, low cost-of-ownership manufacturing equipment for the high volume production of photovoltaic (PV) solar cell device architecture. It is a further object of this disclosure to reduce material processing steps and material cost compared to existing technologies by using gas-phase source silicon. The present disclosure teaches the fabrication of a sacrificial substrate base layer that is compatible with a gas-phase substrate growth process. Porous silicon is used as the sacrificial layer in the present disclosure. Further, the present disclosure provides equipment to produce a sacrificial porous silicon PV cell-substrate base layer.
Latest Solexel, Inc. Patents:
- Three-dimensional thin-film semiconductor substrate with through-holes and methods of manufacturing
- Structures and methods for high-efficiency pyramidal three-dimensional solar cells
- Three-dimensional semiconductor template for making high efficiency solar cells
- Systems and methods for enhanced light trapping in solar cells
- Monolithically isled back contact back junction solar cells
The present disclosure relates to solar cells and methods of manufacture. More specifically, the present disclosure relates to a high volume porous silicon process.
DESCRIPTION OF THE RELATED ARTIn the solar cell industry, known high-efficiency technologies usually use semiconductor-grade mono-crystalline silicon wafers, produced using extensive and costly process steps.
Presently, and into the foreseeable future, the use of costly high-quality bulk mono-crystalline-Silicon (c-Si) will be the cost barrier preventing all competing high-efficiency c-Si technologies from reaching the critical “grid-parity” cost threshold.
Existing technologies rely on a supply of semiconductor-grade substrates fabricated from expensive CZ or FZ mono-crystalline silicon ingots which are processed into substrates using a series of high-precision subtractive processes, such as ingot slicing, mechanical lapping, chemical etching and chemical-mechanical polishing.
The inherent cost of semiconductor-grade silicon substrates may prevent competing c-Si PV technologies from reaching grid-parity costs because of the high degree of silicon cost combined with the extensive substrate preparation steps.
SUMMARYTherefore, it is an object of this disclosure to provide high productivity, low cost-of-ownership manufacturing equipment for the high-volume production of photovoltaic (PV) solar cell devices.
The PV solar cell architecture of the present disclosure may deliver best-of-class efficiency, over 20%, while consuming a small fraction, as little as 15%, of source silicon material, at a much lower cost than that used in the production of present high-efficiency cells.
It is a further object of this disclosure to reduce material processing steps and material cost compared to existing technologies by using gas-phase source silicon.
The present disclosure achieves high efficiency and low cost by using the disclosed process to grow the PV cell substrate from gas-phase source silicon into a substantially finished shape with close to 100% source-material utilization.
The presently disclosed substrate growth process allows the in-situ formation of three-dimensional structured substrates or two-dimensional substrates that may enhance efficiency through formation of highly effective light trapping PN junction structures.
The present disclosure teaches the fabrication of a sacrificial substrate base layer that is compatible with a gas-phase substrate growth process. Porous silicon is used as the sacrificial layer in the present disclosure.
Further, the present disclosure provides equipment to produce a sacrificial porous silicon PV cell-substrate base layer, which may assist in the fabrication of highly cost-effective and efficient mono-crystalline silicon PV solar cells.
The porous silicon process uses electrochemical etching of the bulk silicon surface to produce a controlled thickness of a highly porous silicon layer or a stack of multiple porous silicon layers referred to as the porous silicon layer system. The porosity of the films may be controlled from 20% to 70% volumetric ratio of open porosity to silicon, and the thickness may be controlled from 0.2 μm to over 5 μm.
The electrochemical reaction is similar to processes most often referred to as “anodization” in the metal finishing industry. The basic reaction is shown in
The porous silicon layer system may provide two primary functions: 1) the porous silicon provides a sacrificial base on which the aforementioned gas-phase mono-crystalline silicon-cell substrate is grown, and 2) the porous silicon is removed after the growth of the mono-crystalline silicon-cell substrate, using a highly selective chemical etch process, a controlled mechanical process, or a combination of chemical and mechanical process, which results in the release of the cell substrate from the bulk-silicon wafer from which the porous silicon layer was originally formed.
These and other advantages of the disclosed subject matter, as well as additional novel features, will be apparent from the description provided herein. The intent of this summary is not to be a comprehensive description of the subject matter, but rather to provide a short overview of some of the subject matter's functionality. Other systems, methods, features and advantages here provided will become apparent to one with skill in the art upon examination of the following FIGURES and detailed description. It is intended that all such additional systems, methods, features and advantages included within this description, be within the scope of the claims.
The features, nature, and advantages of the disclosed subject matter may become more apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference numerals indicate like features and wherein:
The following description is not to be taken in a limiting sense, but is made for the purpose of describing the general principles of the present disclosure. The scope of the present disclosure should be determined with reference to the claims. Exemplary embodiments of the present disclosure are illustrated in the drawings, like numbers being used to refer to like and corresponding parts of the various drawings.
The present disclosure presents a PV cell substrate fabrication process flow using porous silicon as a sacrificial layer.
The system may produce porous silicon films with acceptable quality for supporting the manufacturing of PV cells.
At step 62, resist 71 has been stripped away from wafer 10, and wafer 10 has been cleaned. Then a sacrificial layer system 12 of porous silicon has been grown on the frontside of wafer 10.
At step 63, solar cell substrate 14 has been epitaxially deposited onto sacrificial layer system 12. At step 64, substrate 14 has been diced to the correct size (in one embodiment, five inches square), and its backside has been lapped (in one embodiment, to approximately 260 um).
At step 65, sacrificial layer system 12 has been selectively etched, releasing substrate 14 from wafer 10.
The present disclosure is focused on the characterization of films treated with varying levels of porosity and annealing conditions relative to etch rate and compatibility with several etch chemistries.
The present disclosure teaches a porous silicon process system used to develop a high quality porous silicon electro-etching process that can be scaled into high volume PV cell manufacturing and can deliver very high wafer throughputs, on the order of 1,500 to 2,000 substrates per hour.
To accomplish these wafer throughputs, the present disclosure teaches transitioning from the present single-wafer, cylindrical, sealed electrolytic “chamber” configuration to an open-cell, unconfined or suitably confined multi-wafer immersion configuration for the silicon electro-etching process. This transition may enable high-throughput, low cost-of-ownership in-line conveyor style wafer handling and transport.
Because the silicon wafer may have a higher resistance than the surrounding electrolyte, if a conduction path is available that does not pass through the wafer, current may flow through the electrolyte without affecting the wafer. It is thus an object of the present disclosure to eliminate such conduction paths that do not pass through the wafer. A wafer transport pallet that isolates electrochemical conduction paths other than through the silicon wafer may force the electrical field to pass only through the silicon wafer.
Palletized wafer handling may allow a higher rate of wafer throughput than the stationary immersion tank methods of
An embodiment 90 of a pallet according to the present disclosure is shown in
The present disclosure includes a pallet-based wafer transport system, where the electrolytic cell is oriented vertically, with the wafer frontside facing upward and the wafer backside facing downward. The wafer transport pallets may be connected in-line and oriented perpendicular to the vertical electrolytic cell orientation. This may enable simple in-line wafer transport through the immersion electro-etching process system, while providing a compact spacing of electro-etching cells and a non-confined chamber design.
The wafer transport pallet-based electrolytic cell design of the present disclosure may eliminate the reliance on circumferential seals applied directly to the front and back of a silicon wafer. The present disclosure relies on a circumferential seal to the silicon wafer backside combined with the pressure head of the electrolyte that is created by a column of electrolyte above the silicon wafer and pallet. Since the frontside seal is eliminated, electro-etching may span the entire front surface of the wafer, with no exclusion zones from the wafer center to around the wafer edge. Thus, this design may provide full wafer edge bevel wrap-around electro-etching due to the lack of a frontside wafer seal. This is an improvement over prior art electro-etching systems, which may have difficulty etching a wafer all the way to its edge.
Wafer 200 may be inserted into the electrolytic chamber by any suitable mechanism known in the art. For example, a robotic arm could be used to place the wafer in the chamber.
Inside the chamber, the back side of wafer 200 may rest on a circumferential sealing mechanism. As shown in
As shown in
A silicon wafer electro-etching cell in which the silicon wafer has a three dimensional surface topography that forms a cavity or trench pattern may be used in the formation of crystalline silicon PV solar cell substrates. The silicon PV substrate may be formed on a layer of porous silicon using gas-phase deposition of silicon and then released from the fragile structure provided by the porous silicon layer. The porous silicon layer produced by this system is used as a release layer for the gas-phase deposited silicon substrate. The 3D patterned silicon wafer processed through this system is referred to in the FIGURES as a template.
The silicon wafer template is the equivalent of a 3D reverse mold for the fabrication of 3D shaped silicon substrates. This pallet-based non-frontside-sealed electro-etching process cell design also has the advantage that frontside template topography does not interfere with the ability to produce a continuous, high-uniformity porous silicon layer, since there is no direct-contact frontside seal on the template wafer.
The present disclosure includes an open electrolytic cell that applies a differential pressure (top vs. bottom) on a silicon wafer by confining a tall column of electrolyte on the frontside of the wafer and providing an electrolytic contact on the backside of the silicon wafer that applies little or no upward force to the wafer. This ensures a differential pressure load on the wafer, which compresses the seal between the wafer backside and the pallet top-edge.
A non-confined silicon wafer electro-etching cell design may transport silicon wafers on pallets that are transported through a single or a series of electrolytic cells using a continuous conveyor system, or it may simply rely on a lip inside the electrolytic cells to support the wafer and ensure a uniform electric field across the entire wafer.
The present disclosure provides an electro-etching system which consists of conveyorized transport of wafer-holding pallets, in which the pallets form an integral and critical functional component of the electrolytic cell and a means of sealing a silicon wafer solely from the backside of the wafer. This sealing allows the prevention of shadowing, blocking, and exclusion zones on the wafer frontside. The pallets also provide transport from wafer loading to wafer un-loading through the electro-etching system. The pallets are a component of some embodiments of the present disclosure, but they are not a necessary component of all embodiments.
The transition from a single-wafer sealed cylindrical chamber in known systems to the newly presented in-line immersion configuration may result in a significant increase in the electrical field and an improved porous silicon distribution across the surface of the wafer in process.
The pallet and conveyor based in-line immersion porous silicon electro-etching process system embodiment of the present disclosure is designed with several key components and design considerations, which may be varied in order to change the characteristics of the resulting system. Some of these design considerations include the following: electrode shape, size and spacing; electrode segmentation (multi-staged electrodes); electrode material; electrode current density; AC, DC, or pulsed current supply; wafer-to-electrode spacing; wafer configuration (topography, via holes, wafer thickness, wafer doping conditions, and surface treatments); wafer orientation within the wafer processing zone; wafer processing zone shape and size; wafer transport speed through the processing zone; reactant-gas extraction from the wafer in process (avoidance of gas bubbles and the resulting blocked electro-etching); electrolyte concentrations, flow rates, and flow direction; and electrolyte stability.
The foregoing description of embodiments is provided to enable a person skilled in the art to make and use the disclosed subject matter. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without the use of the innovative faculty.
Claims
1. An apparatus for producing porous silicon on a front side of a silicon wafer comprising:
- a wafer handling pallet comprising: an opening for holding the peripheral edge of the silicon wafer; a wafer backside sealing mechanism comprising a seal contacting only the backside of the wafer;
- a housing comprising at least one vertically oriented non-confined electrolytic cell;
- said vertically oriented electrolytic cell comprising: an anode positioned at the bottom of said electrolytic cell; a cathode positioned at the top of said electrolytic cell; and an electrolyte; and
- the housing and the wafer handling pallet configured so that a column of said electrolyte above the silicon wafer is applying pressure to the front side of the silicon wafer greater than the pressure applied to the backside of the silicon wafer, the differential pressure sealing the backside surface of the silicon wafer to said sealing mechanism.
2. The apparatus of claim 1, further comprising a rinsing mechanism using a spray of deionized water.
3. The apparatus of claim 1 further comprising a rinsing mechanism using a tank of deionized water.
4. The apparatus of claim 1, further comprising a motor for moving said wafer handling pallet through said at least one electrolytic cell.
5. The apparatus of claim 1, wherein said sealing mechanism comprises a circumferential seal within said electrolytic cell.
6. The apparatus of claim 5, further comprising a mechanism capable of placing the silicon wafer inside said electrolytic cell and removing the silicon wafer from said electrolytic cell.
7. The apparatus of claim 1, wherein said at least one electrolytic cell comprises a plurality of electrolytic cells.
8. The apparatus of claim 1, wherein said electrolyte of said at least one electrolytic cell comprises HF/IPA.
9. The apparatus of claim 1, wherein said at least one electrolytic cell further comprises an electrolyte jet for removing a gas from said anode.
10. The apparatus of claim 1, wherein said at least one electrolytic cell further comprises an electrolyte jet for removing a gas from said cathode.
11. The apparatus of claim 1, wherein said silicon wafer is a p-type silicon wafer.
12. The apparatus of claim 1, wherein said wafer handling pallet is made of a non-conductive material.
13. The apparatus of claim 12, wherein said non-conductive material is high-density polyethylene.
14. The apparatus of claim 1, further comprising a plurality of wafer handling pallets.
15. The apparatus of claim 14, wherein said plurality of wafer handling pallets are connected in-line.
16. The apparatus of claim 14, further comprising a motor for moving said plurality of wafer handling pallets through said at least one electrolytic cell.
17. The apparatus of claim 7, further comprising a plurality of wafer handling pallets.
18. The apparatus of claim 17, wherein said plurality of wafer handling pallets are connected in-line.
19. The apparatus of claim 17, further comprising a motor for moving said plurality of wafer handling pallets through said plurality of electrolytic cells.
20. The apparatus of claim 7, wherein said electrolyte of said plurality of electrolytic cells comprises HF/IPA.
4043894 | August 23, 1977 | Gibbs |
4070206 | January 24, 1978 | Kressel et al. |
4082570 | April 4, 1978 | House et al. |
4165252 | August 21, 1979 | Gibbs |
4249959 | February 10, 1981 | Jebens |
4251679 | February 17, 1981 | Zwan |
4348254 | September 7, 1982 | Lindmayer |
4361950 | December 7, 1982 | Amick |
4409423 | October 11, 1983 | Holt |
4427839 | January 24, 1984 | Hall |
4461922 | July 24, 1984 | Gay et al. |
4479847 | October 30, 1984 | McCaldin et al. |
4626613 | December 2, 1986 | Wenham et al. |
4672023 | June 9, 1987 | Leung |
4922277 | May 1, 1990 | Carlson |
5024953 | June 18, 1991 | Uematsu et al. |
5073230 | December 17, 1991 | Maracas et al. |
5112453 | May 12, 1992 | Behr et al. |
5208068 | May 4, 1993 | Davis |
5248621 | September 28, 1993 | Sano |
5316593 | May 31, 1994 | Olson et al. |
5348618 | September 20, 1994 | Canham et al. |
5358600 | October 25, 1994 | Canham et al. |
5397400 | March 14, 1995 | Matsuno et al. |
5458755 | October 17, 1995 | Fujiyama et al. |
5459099 | October 17, 1995 | Hsu |
5494832 | February 27, 1996 | Lehmann et al. |
5538564 | July 23, 1996 | Kaschmitter |
5645684 | July 8, 1997 | Keller |
5660680 | August 26, 1997 | Keller |
5679233 | October 21, 1997 | Van Anglen et al. |
5681392 | October 28, 1997 | Swain |
5689603 | November 18, 1997 | Huth |
5882988 | March 16, 1999 | Haberern et al. |
5928438 | July 27, 1999 | Salami |
6091021 | July 18, 2000 | Ruby |
6096229 | August 1, 2000 | Shahid |
6114046 | September 5, 2000 | Hanoka |
6127623 | October 3, 2000 | Nakamura et al. |
6204443 | March 20, 2001 | Kiso et al. |
6254759 | July 3, 2001 | Rasmussen |
6294725 | September 25, 2001 | Hirschberg et al. |
6331208 | December 18, 2001 | Nishida et al. |
6399143 | June 4, 2002 | Sun et al. |
6416647 | July 9, 2002 | Dordi et al. |
6429037 | August 6, 2002 | Wenham et al. |
6441297 | August 27, 2002 | Keller et al. |
6448155 | September 10, 2002 | Iwasaki et al. |
6461932 | October 8, 2002 | Wang |
6517697 | February 11, 2003 | Yamagata |
6524880 | February 25, 2003 | Moon et al. |
6534336 | March 18, 2003 | Iwane |
6555443 | April 29, 2003 | Artmann et al. |
6566235 | May 20, 2003 | Nishida et al. |
6602760 | August 5, 2003 | Poortmans et al. |
6602767 | August 5, 2003 | Nishida et al. |
6613148 | September 2, 2003 | Rasmussen |
6624009 | September 23, 2003 | Green et al. |
6645833 | November 11, 2003 | Brendel |
6649485 | November 18, 2003 | Solanki et al. |
6653722 | November 25, 2003 | Blalock |
6664169 | December 16, 2003 | Iwasaki et al. |
6756289 | June 29, 2004 | Nakagawa et al. |
6881644 | April 19, 2005 | Malik et al. |
6946052 | September 20, 2005 | Yanagita et al. |
6964732 | November 15, 2005 | Solanki |
7014748 | March 21, 2006 | Matsumura et al. |
7022585 | April 4, 2006 | Solanki et al. |
7026237 | April 11, 2006 | Lamb |
7368756 | May 6, 2008 | Bruhns et al. |
7402523 | July 22, 2008 | Nishimura |
20020153039 | October 24, 2002 | Moon et al. |
20020168592 | November 14, 2002 | Vezenov |
20020179140 | December 5, 2002 | Toyomura |
20030017712 | January 23, 2003 | Brendel |
20030039843 | February 27, 2003 | Johnson |
20030124761 | July 3, 2003 | Baert |
20040028875 | February 12, 2004 | Van Rijn |
20040173790 | September 9, 2004 | Yeo |
20040217005 | November 4, 2004 | Rosenfeld et al. |
20040259335 | December 23, 2004 | Narayanan |
20040265587 | December 30, 2004 | Koyanagi |
20050160970 | July 28, 2005 | Niira |
20050172998 | August 11, 2005 | Gee et al. |
20050176164 | August 11, 2005 | Gee et al. |
20050177343 | August 11, 2005 | Nagae |
20050199279 | September 15, 2005 | Yoshimine et al. |
20050274410 | December 15, 2005 | Yuuki et al. |
20050281982 | December 22, 2005 | Li |
20060021565 | February 2, 2006 | Zahler et al. |
20060043495 | March 2, 2006 | Uno |
20060054212 | March 16, 2006 | Fraas et al. |
20060070884 | April 6, 2006 | Momoi et al. |
20060105492 | May 18, 2006 | Veres et al. |
20060196536 | September 7, 2006 | Fujioka |
20060231031 | October 19, 2006 | Dings et al. |
20060266916 | November 30, 2006 | Miller et al. |
20060283495 | December 21, 2006 | Gibson |
20070077770 | April 5, 2007 | Wang et al. |
20070082499 | April 12, 2007 | Jung et al. |
20080047601 | February 28, 2008 | Nag et al. |
20080157283 | July 3, 2008 | Moslehi |
20080210294 | September 4, 2008 | Moslehi |
20080264477 | October 30, 2008 | Moslehi |
20080277885 | November 13, 2008 | Duff et al. |
20080289684 | November 27, 2008 | Moslehi |
20080295887 | December 4, 2008 | Moslehi |
20090042320 | February 12, 2009 | Wang et al. |
20090107545 | April 30, 2009 | Moslehi |
20090301549 | December 10, 2009 | Moslehi |
20100022074 | January 28, 2010 | Wang et al. |
20100116316 | May 13, 2010 | Moslehi et al. |
0597428 | May 1994 | EP |
0879902 | November 1998 | EP |
06-260670 | September 1994 | JP |
- Alvin D. Compaan, Photovoltaics: Clean Power for the 21st Century, Solar Energy Materials & Solar Cells, 2006, pp. 2170-2180, vol. 90, Elsevier B.V.
- C.Berge, 150-mm Layer Transfer for Monocrystalline Silicon Solar Cells, Solar Energy Materials & Solar Cells, 2006, pp. 3102-3107, vol. 90, Elsevier B.V.
- C.Oules et al, Silicon on Insulator Structures Obtained by Epitaxial Growth of Silicon over Porous Silicon, Journal of the Electrochemical Society, Inc., 1992, p. 3595, vol. 139, No. 12, Meylan Cedex, France.
- C.S.Solanki, et al, Porous Silicon Layer Transfer Processes for Solar Cells, Solar Energy Materials & Solar Cells, 2004, pp. 101-113, vol. 83, Elsevier B.V., Leuven, Belgium.
- C.S.Solanki, et al, Self-Standing Porous Silicon Films by One-Step Anodizing, Journal of Electrochemical Society, 2004, pp. C307-C314, vol. 151, The Electrochemical Society, Inc., Leuven, Belgium.
- F.Duerinckx, et al, Reorganized Porous Silicon Bragg Reflectors for Thin-Film Silicon Solar Cells, IEEE Electron Device Letters, Oct. 2006, vol. 27, No. 10.
- Francois J. Henley, Layer-Transfer Quality Cleave Principles, SiGen, Jul. 8, 2005, pp. 1-6, The Silicon Genesis Corporation, San Jose, California.
- H.J.Kim, et al, Large-Area Thin-Film Free-Standing Monocrystalline Si Solar cells by Layer Transfer, Leuven, Belgium, IEEE.
- J.H.Werner et al, From Polycrystalline to Single Crystalline Silicon on Glass, Thin Solid Films, 2001, pp. 95-100, vol. 383, Issue 1-2, Elsevier Science B.V., Germany.
- J.J. Schermer et al., Epitaxial Lift-Off for large area thin film III/V devices, phys. Stat. sol. (a) 202, No. 4, 501-508 (2005).
- Jianhua Zhao, et al, A 19.8% Efficient Honeycomb Multicrystalline Silicon Solar Cell with Improved Light Trapping, IEEE Transactions on Electron Devices, 1999, vol. 46, No. 10.
- K. Van Nieuwenhuysen et al., Progress in epitaxial deposition on low-cost substrates for thin-film crystalline silicon solar cells at IMEC, Journal of Crystal Growth, 2006, pp. 438-441, vol. 287, Elsevier B.V., Leuven, Belgium.
- K.L. Chopra et al., Thin-Film Solar Cells: An Overview, Progress in Photovoltaics: Research and Applications, 2004, pp. 69-92, vol. 12, John Wiley & Sons, Ltd.
- Lammert et al., The Interdigitated Back Contact Solar Cell: A Silicon Solar Cell for Use in Concentrated Sunlight, IEEE Transactions on Electron Devices, pp. 337-342.
- MacDonald et al., “Design and Fabrication of Highly Topographic Nano-imprint Template for Dual Damascene Full 3-D Imprinting,” Dept. of Chemical Eng., University of Texas at Austin, Oct. 24, 2005.
- Martin A. Green, Consolidation of Thin-Film Photovoltaic Technology: The Coming Decade of Opportunity, Progress in Photovoltaics: Research and Applications, 2006, pp. 383-392, vol. 14, John Wiley & Sons, Ltd.
- Martin A. Green, Silicon Photovoltaic Modules: A Brief History of the First 50 Years, Progress in Photovoltaics: Research and Applications, 2005, pp. 447-455, vol. 13, John Wiley & Sons, Ltd.
- Nobuhiko Sato et al, Epitaxial Growth on Porous Si for a New Bond and Etchback Silicon-on-Insulator, Journal of Electrochemical Society, Sep. 1995, vol. 142, No. 9, The Electrochemical Society, Inc., Hiratsuka, Japan.
- P.J.Verlinden, et al, Sliver® Solar Cells: A New Thin-Crystalline Silicon Photovoltaic Technology, Solar Energy Materials & Solar Cells, 2006, pp. 3422-3430, vol. 90, Elsevier B.V.
- P.R. Hageman et al., Large Area, Thin Film Epitaxial Lift Off III/V Solar Cells, 25th PVSC, May 13-17, 1996, Washington D.C., IEEE.
- Photovoltaic Technology Research Advisory Council, A Vision for Photovoltaic Technology, 2005, pp. 1-41, European Commision Publications Office.
- Prometheus Institute, U.S. Solar Industry Year in Review: U.S. Solar Energy Industry Charging Ahead, (SEIA) The Solar Energy Industry Association.
- R.Brendel, et al, Sol-Gel Coatings for Light Trapping in Crystalline Thin Film Silicon Solar Cells, Journal of Non-Crystalline Solids, 1997, pp. 391-394, vol. 218, Elsevier Science B.V., Germany.
- Richard Auer et al, Simplified Transfer Process for High-Current Thin-Film Crystalline Si Solar Modules, 3rd World Conference on Photovoltaic Energy Conversion, May 11-18, 2003, Osaka, Japan.
- Richard M. Swanson, A Vision for Crystalline Silicon Photovoltaics, Progress in Photovoltaics: Research and Applications, 2006, pp. 443-453, vol. 14, John Wiley & Sons, Ltd.
- Rolf Brendel, A Novel Process for Ultrathin Monocrystalline Silicon Solar Cells on Glass, 14th European Photovolaic Solar Energy Conference, Jun. 30-Jul. 4, 1997, Barcelona, Spain.
- Rolf Brendel, Review of Layer Transfer Processes for Cystalline Thin-Film Silicon Solar Cells, The Japan Journal of Applied Physics, 2001, pp. 4431-4439, vol. 40, Part 1, No. 7, The Japan Society of Applied Physics, Japan.
- Rolf Brendel, Thin-Film Crystalline Silicone Mini-Modules Using Porous Si for Layer Transfer, Solar Energy, 2004, pp. 969-982, vol. 77, Elsevier Ltd., Germany.
- S. Hegedus, Thin Film Solar Modules: The Low Cost, High Throughput and Versatile Alternative to Si Wafers, Progress in Photvoltaics: Research and Applications, 2006, pp. 393-411, vol. 14, John Wiley & Sons, Ltd.
- Takao Yonehara, et al, Epitaxial Layer Transfer by Bond and Etch Back of Porous Si, Applied Physics Letter 64, Apr. 18, 1994, vol. 16, American Institute of Physics.
- Toshiki Yagi, et al, Ray-Trace Simulation of Light Trapping in Silicon Solar Cell with Texture Structures, Solar Energy Materials & Solar Cells, 2006, pp. 2647-2656, vol. 90, Elsevier B.V.
Type: Grant
Filed: Jan 15, 2010
Date of Patent: Jan 6, 2015
Patent Publication Number: 20110120882
Assignee: Solexel, Inc. (Milpitas, CA)
Inventors: Doug Crafts (Los Gatos, CA), Mehrdad Moslehi (Los Altos, CA), Subramanian Tamilmani (San Jose, CA), Joe Kramer (San Jose, CA), George D. Kamian (Scotts Valley, CA), Somnath Nag (Saratoga, CA)
Primary Examiner: Bryan D. Ripa
Application Number: 12/688,495
International Classification: C25D 17/00 (20060101); H01L 31/18 (20060101); H01L 21/67 (20060101); H01L 21/677 (20060101);