Abstract: An accessory mount (20) for a portable instrument (26) is provided. The device includes a housing (28a and 28b) and a recess (30) located in the housing. The accessory mount also includes a frame (24) received within the recess and a fastener member (36a and 36b) attached to the frame for selectively attaching the frame within the recess. The accessory mount also includes a slot (42) that is partially formed with the frame for selectively attaching and/or positioning equipment, such as an adapter (22), to the device, thereby permitting operation of the device without requiring the use of both hands of an operator.

Abstract: A flexible mounting for use in the forming section of a twin forming fabric paper making machine consisting essentially of a base member supported by the paper making machine structure to which is attached a flexible C-shaped beam. The C-shaped beam has one edge attached to the base member, and a fabric contacting blade attachment means at the other edge. A pressurized loading tube is located within the C-shaped beam between the base member and the second edge of the C-shaped beam. When the pressurized loading tube is loaded, the C-shaped beam flexes thus allowing the blade to move initially into contact with a forming fabric. As the pressurized tube is further loaded, the contact face of the blade is moved into further engagement with the forming fabric. In a preferred construction, the wrap angle of the fabrics at or about the blade leading edge can be minimized. The mounting thus can diminish wear of the fabric as it passes over the blade.

Abstract: A threshold device or comparator comprises an array of energy emitters, e.g. light emitting diodes (16) or diode arrangements. The bits of a binary string are supplied to respective diodes or diode arrangements, which have the property of emitting energy of a distinguishable different characteristic depending on whether the applied bit is a 0 or 1. Sensors (18, 20) sensitive to the intensities of the respective different characteristics detect the intensities and a comparator 24 provides an output indicating the relative quantities of 0's and 1's in the binary string.

Abstract: In order to measure a scanning light cut-off region, an output of a light receiving element and a threshold value set by an MPU are compared by a comparator and a region where the former is smaller than the latter is measured as the scanning light cut-off region. During one cycle of optical scanning, this threshold value is switched in a plurality of stages according to the scanning angle. By accurately measuring the scanning light cut-off region, the correct position and size of an indicator such as a finger or pen are calculated.

Abstract: A 3D shape measurement method and a device using the method eliminate harmful influences of periodic inconstancy in the phase shift method. Optical intensity patterns following periodic functions of sine waves are irradiated on an object while shifting the phases thereof. Based on the image picked up from the object, the 3D shape of the object is measured. In this method, a plurality of optical intensity patterns following periodic functions with varying wavelengths are projected onto the object so as not to interfere with each other. The least common multiple of the wavelengths of the periodic functions is larger than the extent having periodic inconstancy within the image pickup area.

Abstract: It is intended to prevent occurrence of random noise in an ion trap mass spectrometer with an electron impact (EI) ion source during mass analyzing. Specifically, two gates are placed between a filament and an end cap electrode. Positive or negative voltage is applied to the two electrodes in such a manner as to prevent both ions and electrons from entering an ion trap region in a mass analyzing step. This eliminates random noise on a mass spectrum, thereby allowing mass spectrum measurement of smaller quantities of components. It also eliminates noise on a chromatogram, thus allowing quantitative analysis of smaller quantities of components.

Abstract: An inspection method and apparatus which controls an acceleration voltage of an electron beam, irradiates the electron beam to an object to be inspected mounted on a stage which is continuously moving at least in one direction, detects at least one of a secondary electron and a reflected electron emanated from the object by the irradiating, obtains an image of the object from the detected electron by using positional information of the stage, conducts inspection or measurement of the object using the image obtained, and outputs a result of the inspection or the measurement through a network system which is connected to a computer.

Abstract: A secondary electron signal obtained from a specimen when the specimen is scanned with an electron beam is detected by a detector and a specimen image is displayed on a first display screen area of an image display unit on the basis of the detected signal. The specimen image is stored, as an image for observation position designation, in a storage unit together with a position of the image. A plurality of images at different positions on the specimen may be used as the image to be stored. One of the stored images is selected and read and displayed on a second display screen area. When a part of interest on the displayed image for observation position designation is selected, the specimen is horizontally moved so that a position of the part of interest may be positioned at the center of the first display screen area and an enlarged image of the part of interest may be displayed on the first display screen area. This facilitates view field search outside a view field range.

Abstract: The invention relates to an X-ray detector 8 which includes a sensor matrix and a scintillator arrangement 20 and in which wire elements 21 and 22 are spaced apart in layers A and B in order to reduce the crosstalk in neighboring detector elements; scintillators 23 are inserted at least partly in the grid openings 24 formed.

Abstract: An apparatus for optically checking a pattern of a semiconductor wafer, includes (a) a laser beam source which radiate a laser beam to the pattern, (b) a beam collector which collects a laser beam reflected from the pattern, (c) a photodetector which detects a defect in a shape in the pattern, based on the laser beam collected by the beam collector, the laser beam source and the beam collector being movable together in an area above the semiconductor wafer.

Abstract: The invention is a pin valve having a detachable valve body cover which makes the valve stem assembly accessible from the end of the valve in which the valve stem protrudes. The removable valve body cover can be replaced independently if this end of the valve is damaged. The valve body cover also has a valve seat which is more accessible and is more easily machined. The valve body cover is typically adapted to accommodate an allen wrench type tool to simplify removal and reattachment. The invention eliminates the need to disconnect the valve at the second open end when replacing the valve stem assembly.

Abstract: When a phase shift method is used as lithography where sense amplifiers are alternately placed in a one intersecting-point memory capable of implementing a reduction in the area of a DRAM, it was difficult to layout data lines in a boundary region between sense amplifiers and each memory array. Therefore, there is provided a semiconductor device according to the present invention. In the semiconductor device, two data lines continuous within the sub memory arrays or interposed therebetween are connected to the adjacent sense amplifiers as a system for drawing data lines from sub memory arrays (SMA) to sense amplifiers (SA) when the sense amplifiers are alternately placed. Namely, the number of data lines interposed between data lines respectively connected to two adjacent sense amplifiers is set to even numbers (0, 2, 4, . . . ).

Abstract: There is provided an electric device which can prevent a deterioration in a frequency characteristic due to a large electric power external switch connected to an opposite electrode and can prevent a decrease in the number of gradations. The electric device includes a plurality of source signal lines, a plurality of gate signal lines, a plurality of power source supply lines, a plurality of power source control lines, and a plurality of pixels. Each of the plurality of pixels includes a switching TFT, an EL driving TFT, a power source controlling TFT, and an EL element, and the power source controlling TFT controls a potential difference between a cathode and an anode of the EL element.

Abstract: A semiconductor device is provided which is capable of removing the heavy metal impurity in a SOI layer by gettering, and realizing an improvement in breakdown voltage and reliability. The semiconductor device (50) comprises polysilicon regions (17, 18) functioning as a gettering site, which are selectively formed in a buried fashion, such as to make no contact with a gate insulating film (6) and an element isolation insulating film (11), in a main surface of part of a SOI layer (4) where a drain region (8) and a source region (9) are disposed; and contact holes (13, 15) being filled with polysilicon plug functioning as a gettering site, and extending through an interlayer insulating film (12) between an upper surface of the interlayer insulating film (12) and an upper surface of the polysilicon regions (17, 18).

Abstract: A semiconductor configuration with an ohmic contact-connection includes a p-conducting semiconductor region made of silicon carbide. A p-type contact region serves for the contact-connection. The p-type contact region is composed of a material containing at least nickel and aluminum. A substantially uniform material composition is present in the entire p-type contact region. A method for contact-connecting p-conducting silicon carbide with a material containing at least nickel and aluminum is also provided. The two components nickel and aluminum are applied simultaneously on the p-conducting semiconductor region.

Abstract: A semiconductor device that is easily operated with a single positive voltage supply and exhibits an excellent linearity of mutual conductance and source-gate capacitance with regard to a gate voltage is provided. The semiconductor device comprises a second barrier layer of AlGaAs, a channel layer of InGaAs and a first barrier layer of AlGaAs that are stacked in this order on a substrate of GaAs with a buffer layer of u-GaAs between the substrate and the second barrier layer. Carrier supply regions doped with n-type impurity are formed in part of the first and second barrier layers. A low resistivity region including a high concentration of p-type impurity (Zn) is formed in the first barrier layer. The low resistivity region is buried in a high resistivity region and brought to contact with a gate electrode. Upon an application of positive voltage to the gate electrode, a carrier deficient region disappears in the channel layer and no parasitic resistance component remains.

Abstract: A MOSFET simulation apparatus includes an output unit, and a processor which simulates an operation of MOSFET using a new MOSFET model, and outputs the simulation result to the output unit. The new MOSFET model includes a MOSFET model, a first circuit model and a second circuit model. The MOSFET model is known as BSIM3V3 and has a gate, a source, a drain and a gate insulating film. The first circuit model is connected between the gate and the source, and includes first and second diode models connected in parallel in opposite directions to each other. The second circuit model connected between the gate and the drain, and including third and fourth diode models connected in parallel in opposite directions to each other.

Abstract: It is an object of the present invention to provide a ferroelectric capacitor which maintains high ferroelecticity. A silicon oxide layer 2, a lower electrode 12, a ferroelectric layer 8 and an upper electrode 10 are formed on a silicon substrate 2. The lower electrode 12 is formed by an alloy layer made of iridium and platinum. The alloy layer of the lower electrode 12 can be formed under appropriate lattice constant correspond with a kind and composition of the ferroelectric layer 8. So that, a ferroelectric layer having excellent ferroelectricity can be obtained. Also, it is possible to prevent vacancy of oxygen in the ferroelectric layer 8.

Abstract: A method of making a semiconductor device and the device. The device, according to a first embodiment, is fabricated by providing a silicon (111) surface, forming on the surface a dielectric layer of crystalline silicon nitride and forming an electrode layer on the dielectric layer of silicon nitride. The silicon (111) surface is cleaned and made atomically flat. The dielectric layer if formed of crystalline silicon nitride by placing the surface in an ammonia ambient at a pressure of from about 1×10−7 to about 1×10−5 Torr at a temperature of from about 850° C. to about 1000° C. The electrode layer is heavily doped silicon. According to a second embodiment, there is provided a silicon (111) surface on which is formed a first dielectric layer of crystalline silicon nitride having a thickness of about 2 monolayers.

Abstract: Exemplary embodiments of the present invention disclose process steps to form high aspect ratio structures, such as a capacitor during semiconductor fabrication by the steps of: forming a first layer of planarized boro-phospho-silicate glass (BPSG) material over a conductive region; forming a first opening in said first layer of planarized BPSG material, said first opening aligning to said conductive region; forming a planarized polysilicon material into said first opening; forming a second layer of planarized BPSG material directly on said first layer of planarized BPSG material and said planarized polysilicon material; forming a second opening in said second layer of planarized BPSG material to expose a major portion of said planarized polysilicon material; removing said planarized polysilicon material to expose said underlying conductive region, said step of removing said planarized polysilicon comprises an etch possessing an etching selectivity ratio of polysilicon material to BPSG material that is greate

Abstract: An improved storage node junction between a doped active area in a semiconductor substrate and an overlying layer of polysilicon, such as the storage node junction in a DRAM memory cell. The area and perimeter of the storage node junction is significantly reduced and the junction is moved away from the adjacent isolation structure. An exemplary semiconductor device incorporating the new junction includes a storage node junction between a conductive polysilicon layer and an active area on a semiconductor substrate, the substrate having been subjected to LOCOS steps to create active areas bounded by a region of field oxide. An insulated gate electrode is formed over an active area on the substrate, which has been doped to a first conductivity type. A contact region comprising a portion of the active area extends laterally between one side of the gate electrode and the field oxide region.

Abstract: A tunneling insulating film is formed on the partial surface area of a semiconductor substrate. A floating gate electrode is formed on the tunneling insulating film. A gate insulating film covers the side wall of the floating gate electrode and a partial surface area of the semiconductor substrate on both sides of the floating gate electrode. A first control gate electrode is disposed on the gate insulating film over the side wall of the floating gate electrode and over a partial surface area of the semiconductor substrate on both sides of the floating gate electrode. A pair of impurity doped regions is formed in a surface layer of the semiconductor substrate on both sides of a gate structure including the floating gate structure and first control gate structure.

Abstract: In a bit line contact section, a contact hole is formed through a silicon oxide film, and a contact plug made of a polysilicon film doped with impurities is buried in the contact hole. The silicon oxide film is formed with a wiring groove overlapping the contact hole. A bit line made of a metal film is buried in the wiring groove. The contact plug extends through the bit line, and has its upper surface substantially coplanar with an upper surface of the bit line. The contact plug is in contact with the bit line only on its side surfaces.

Abstract: A method for fabricating floating gate semiconductor devices, such as flash EEPROMs, and flash EEPROM memory arrays, is provided. The method includes providing a semiconductor substrate and forming active areas on the substrate. Each active area includes elements of a field effect transistor (FET) including a source, a drain, a channel region, and a gate dielectric layer. Trench isolation structures are also formed in the substrate for electrically isolating the active areas. In addition, a conductive layer (e.g., polysilicon) is deposited on the active areas, and chemically mechanically planarized to an endpoint of the trench isolation structures to form self aligned floating gates on the active areas. Control gate dielectric layers, and control gates are then formed on the floating gates.

Abstract: A vertical Field Effect Transistor (FET) that may be an N-type FET (NFET) or a P-type FET (PFET); a multi-device vertical structure that may be two or more NFETs or two or more PFETS; logic gates including at least one vertical FET or at least one multi-device vertical; a Static Random Access Memory (SRAM) cell and array including at least one vertical FET; a memory array including at least one such SRAM cell; and the process of forming the vertical FET structure, the vertical multi-device (multi-FET) structure, the logic gates and the SRAM cell. The vertical FETs are epitaxially grown layered stacks of NPN or PNP with the side of a polysilicon gate layer adjacent the device's channel layer. The multi-FET structure may be formed by forming sides of two or more gates adjacent to the same channel layer or, by forming multiple channel layers in the same stack, e.g., PNPNP or NPNPN, each with its own gate, i.e., the side of a polysilicon gate layer.

Abstract: The present invention provides an SOI device and its isolation method capable of solving both Well-resistance and punch-through problems. To realize foregoing device, there is provided a semiconductor layer that a region in which a field oxide film having relatively wider width is formed later, is thicker than a region in which a field oxide film having relatively narrower width is formed later. Those field oxide films having different widths with an equal thickness are formed on the field regions of the semiconductor layer. Herein, the thickness of the semiconductor layer below the field oxide film having relatively wider width is thicker than the thickness of the semiconductor layer below the field oxide film having relatively narrower width owing to the fact that the semiconductor layer has various thicknesses according to the respective regions.

Abstract: On one side of a shallow trench isolation region formed on the surface of a p type well, an n type source region is provided while on the other side thereof, an n type drain region is provided so as to sandwich the shallow trench isolation region. In the drain region, a bent portion to allow a breakdown current to flow is provided and connected to a gate of a MOSFET comprising a circuit to be protected. Furthermore, a well contact connected to the source region is formed on the well surface and this well contact is grounded. When a positive high voltage which is higher than a predetermine voltage is applied to the drain region, since electric fields concentrate at the bent portion, a breakdown current flows from this bent portion toward the well contact. Thereafter, a current flows between the source and the drain.

Abstract: In a memory cell arrangement which comprises vertical MOS transistors as memory cells, the information is stored by means of at least three different threshold voltage values of the transistors by multi-level programming. One threshold voltage value is realised by the thickness of the gate dielectric in the sense of a thick oxide transistor and the other threshold voltage values are realised by different channel dopings. The arrangement can be produced with an area requirement for each memory cell of 2 F2 (F: minimum structure size).

Abstract: A gate insulating film in a memory cell portion is thicker than a gate insulating film in a peripheral circuitry. Source/drain of an MOS transistor in the memory cell portion have double-diffusion-layer structures, respectively, and source/drain of an MOS transistor in the peripheral circuitry have triple-diffusion-layer structures, respectively.

Abstract: In a MOS transistor using shallow trench isolation, a pattern of an element formation region has a shape of a modified hexagon in which a hexagon is compressed into a shape like a rhombus in a direction perpendicular to an extension direction of a gate electrode wiring. The pattern of element formation region is constructed as described above, so that an element formation region is formed in a lager current path in a corner device. Thus, a lowering of a threshold voltage (a short channel effect) due to the corner device can be restricted without increasing a width of the gate electrode wiring.

Abstract: A semiconductor fuse is positioned between conductors for connecting wiring lines. The fuse comprises spacers positioned on adjacent ones of the conductors, and a fuse element positioned between the spacers and connected to the wiring lines. A space between the conductors comprises a first width comprising a smallest possible photolithographic width and the fuse element has a second width smaller than the first width.

Abstract: Disclosed is a capacitor of semiconductor integrated circuit and a method for fabricating the same by which characteristic of a capacitor and bit resolution can be improved to thereby obtain an improved analogue device of high accuracy. The capacitor of semiconductor integrated circuit includes a conductive lower electrode formed on a predetermined portion of an insulating substrate, an insulating layer formed on the insulating substrate including the conductive lower electrode and provided with a via hole so that the surface of the lower electrode is exposed in its predetermined portion, a dielectric layer formed on the insulating layer and in the via hole, and an conductive upper electrode formed on the predetermined portion of the dielectric layer including the via hole to have a piled structure such as “conductive plug/conductive layer pattern”.

Abstract: In a motor driving device, an IC chip of a drive circuit for driving a motor is die-bonded to one island of a leadframe, and a diode chip of a protection diode for preventing the drive circuit from being destroyed when supplied power is connected to the IC chip with reverse polarities is die-bonded to another island of the leadframe. The supplied-power pad of the IC chip is wire-bonded to the second island, which serves as the cathode electrode of the diode chip.

Abstract: A ball grid array type semiconductor package includes a semiconductor chip formed with bonding pads, an elastomer bonded to the semiconductor chip, a flexible wiring substrate bonded to the elastomer and formed with wirings connected at one end of the bonding pads of the semiconductor chip, a solder resist formed on the main surface of the flexible wiring substrate and solder bump electrodes connected to the other ends of the wirings. The elastomer is bonded to the flexible wiring substrate on the side of the tape, the solder resist is formed on the side of the wirings, and the solder bump electrodes are connected with the wirings by way of through holes formed in the solder resist.

Abstract: A device for protecting a touch-activated data terminal device having a touch-activated input surface, with a protective foil affixable to the input surface by a holding mechanism, the protective foil fully covering the input surface, includes a multilayer structure receivable at the input surface. Thus, the multilayer structure can be accepted at the input surface or unwound from a material web supply. Also provided are a control console for a rotary printer, and a central control desk for a rotary printer and/or a folder.

Abstract: A semiconductor device includes a semiconductor chip having a main surface formed with an electrode pad, a package containing the semiconductor chip, a component element connected with the electrode pad within the package, a gold bump formed on the electrode pad, and a gold connecting member. The gold connecting member has an end bonded to the gold bump, and the other end bonded to the component.

Abstract: A semiconductor device is made by mounting semiconductor elements on both sides of a wiring board having three-dimensional wiring including inner-via holes. A high operating speed and smaller size are made possible by employing a laminated structure of semiconductor elements without using the chip-on-chip configuration. Semiconductor elements are mounted on both sides of a wiring board having three-dimensional wiring including inner via holes so that the semiconductor elements oppose each other via the wiring board. The electrodes of the semiconductor elements are connected with each other by the three-dimensional wiring of the wiring board.

Abstract: A printed circuit board 1 providing superior adhesion between a substrate 2 and a conductor pattern 3 and preventing damage of the substrate 2. The width c of the bottom surface 310 of the conductor pattern 3 is greater than the width d of the top surface 320. Accordingly, the conductor pattern 3 has a trapezoidal cross-section. The two side surfaces 315 of a lower portion 31 of the conductor pattern 3 are coated by a solder resist. The two side surfaces 325 at the upper portion 32 of the conductor pattern 3 are exposed from the solder resist 4. A solder ball 6 engages the two side surfaces 325.

Abstract: The present invention provides an improved heat sink retention assembly, such that the heat sink is physically supported by a base rather than by an integrated circuit. Traditional heat sinks have an alignment feature that physically aligns and supports the heat sink by contact of the feature with an integrated circuit, and that transfers force applied to the heat sink to the integrated circuit. This transferred force nay be seen as shear stress at the pins of integrated circuits such as pin-grid arrays, and may damage the integrity of the integrated circuit or its connection to an external circuit. The present invention provides alignment and support features remote from contact with the integrated circuit, and therefore provides support for the heat sink in a manner that does not place substantial stress on the integrated circuit.

Abstract: A ball grid array type semiconductor package includes a semiconductor chip formed with bonding pads, an elastomer bonded to the semiconductor chip, a flexible wiring substrate bonded to the elastomer and formed with wirings connected at one end of the bonding pads of the semiconductor chip, a solder resist formed on the main surface of the flexible wiring substrate and solder bump electrodes connected to the other ends of the wirings. The elastomer is bonded to the flexible wiring substrate on the side of the tape, the solder resist is formed on the side of the wirings, and the solder bump electrodes are connected with the wirings by way of through holes formed in the solder resist.

Abstract: An etching mask having high etching selectivity for an inorganic inter layer film of SiO2 or Si3N4, an organic interlayer film such as ARC and an electrically conductive film and a contact hole using such an etching mask, a process for forming same and a resultant semiconductor device. On formation of contact holes for connecting wirings disposed through interlayer films of inorganic or organic material (20, 23 in FIG. 2), a thin film of silicon carbide (21 in FIG. 2) having high etching selectivity for any of the inorganic and organic materials is deposited on an interlayer film, and a mask pattern of silicon carbide is formed using a resist pattern (22 in FIG. 2). Thereafter, high aspect ratio contact holes having a size which is exactly same as that of the mask is formed by etching the interlayer film using the silicon carbide mask.

Abstract: Metal structures that can be produced by a damascene process are disposed in a first insulating layer and a second insulating layer is disposed above the latter. There is in each case at least one cavity which is disposed between the metal structures, is disposed in the first insulating layer and is covered by the second insulating layer. The cavities and the metal structures are produced next to one another by self-aligned process steps.

Abstract: A semiconductor device has (a) a semiconductor component; (b) a circuit substrate; (c) a base material which is placed between the semiconductor component and the circuit substrate; and (d) a conductive paste, which is filled into a hole formed in the base material, for electrically connecting between a terminal electrode of the semiconductor component and an internal connection electrode of the circuit substrate.

Abstract: Solder ball bond pads and wire bond pads may be selectively coated so that the wire bond bond pads have a thicker gold coating than the solder ball bond pads. This may reduce the embrittlement of solder ball joints while providing a sufficient thickness of gold for the wire bonding process. In general, gold coatings are desirable on electrical contact surfaces to prevent oxidation. However, the thickness of gold which is necessary on solder ball bond pads may be less and excessive gold may be disadvantageous. Thus, by masking the solder ball bond pads during the gold coating of the wire bond bond pads, a differential gold thickness may be achieved which is more advantageous for each application.

Abstract: A method of manufacturing a diffusion plate for use in a screen plate of projection TV is disclosed. The diffusion plate having a plurality of quadrangular pyramid protrusions almost over one side thereof is manufactured by means of injection molding process of plastic material. This method uses a first molding die having a first molding die surface, a pre-molding die capable of forming a first volume of molding cavity in matching with the first molding die, and a second molding die capable of forming a second volume of molding cavity smaller than the first volume in matching with the first molding die.

Abstract: A method of producing a rubber thread for a golf ball comprises (a) an extruding process of extruding a rubber composition in the shape of a sheet by using an extruder (2) to obtain a sheet material (6); (b) a rolling process of rolling the sheet material (6) to make it thin to obtain a thin sheet material (10); (c) a cross-linking process of cross-linking the thin sheet material (10) to obtain a cross-linked sheet material; and (d) a cutting process of cutting the cross-linked sheet material to obtain a rubber thread. The rolling process is performed successively to the extruding process. The thickness t1 of the sheet material (6) obtained in the extruding process is set to the range of 1 mm to 8 mm both inclusive. The thickness t2 of the thin sheet material (10) obtained in the rolling process is set to the range of 0.3 mm to 0.6 mm both inclusive.

Abstract: Disclosed is a method of copolymerizing polyethylene glycol (PEG) into polyethylene terephthalate (PET) to achieve a polyethylene glycol-modified polyester composition that can be spun into filaments. The method includes the steps of copolymerizing polyethylene glycol into polyethylene terephthalate in the melt phase to form a copolyester composition, then polymerizing the copolyester composition in the solid phase until the copolyester is capable of achieving a melt viscosity that facilitates the spinning of filaments, and thereafter spinning filaments from the copolyester. A copolyester composition comprised of polyethylene glycol and polyethylene terephthalate is also disclosed. Fabrics made from fibers formed from the copolyester composition possess wetting, wicking, drying, flame-retardancy, static-dissipation, and soft hand properties that are superior to those of fabrics formed from conventional polyethylene terephthalate fibers of the same yarn and fabric construction.

Abstract: The present invention is directed to a golf ball comprising a soft core and a hard cover to produce a golf ball having a reduced spin rate. The present invention is also directed to an improved golf ball comprising at least one interior layer and/or a core comprising a silicone material. It is preferred to also utilize a multi-layer cover in conjunction with the silicone materials. The golf ball of the present invention may also utilize an enlarged diameter which serves to further reduce spin rate. The resulting golf ball exhibits properties of reduced spin without sacrificing durability, playability and resilience.

Abstract: A stay damper for a door etc., includes a cylinder member filled with filler gas under pressure, a piston rod slidable in the cylinder member and a cover supported by the projecting end of the piston rod so that the lower end of the cover can move radially toward and away from the cylinder. The upper end of the cylinder member is formed with a notch opening upward. When the stay damper is extended, the notch of the cylinder member catches the lower end of the cover and prevents inward movement of the piston rod to hold the stay damper in the extended state.

Abstract: Stabilizer (1) for motor vehicles which has a toroidal cross section, and which is formed of several stabilizer sections that, together, create a U-shape having a pair of U-legs (2) connected by a U-back (3) via arcuately shaped transitional shoulder areas (4). The stabilizer (1), as a pipe stabilizer, is able to withstand the required number of load cycles even under very high stress or enables even greater weight reduction under normal stresses, by important stabilizer sections having an increased strength as compared to other stabilizer sections by either dimensioning, and/or increasing the carbon content of an outer and/or inner surface layer of the stabilizer (1) by carburization, and also, optionally, by at least partially shot peening the inner surface, preferably at least in the transitional shoulder areas (4).