Abstract: A microelectromechanical (MEMS) device is provided that includes a microelectronic substrate and a thermally actuated microactuator and associated components disposed on the substrate and formed as a unitary structure from a single crystalline material, wherein the associated components are actuated by the microactuator upon thermal actuation thereof. For example, the MEMS device may be a valve. As such, the valve may include at least one valve plate that is controllably brought into engagement with at least one valve opening in the microelectronic substrate by selective actuation of the microactuator. While the MEMS device can include various microactuators, the microactuator advantageously includes a pair of spaced apart supports disposed on the substrate and at least one arched beam extending therebetween.

Abstract: A control valve for a fuel injection nozzle, having a control chamber, into which a fluid conduit discharges, and a valve element, which rests on a valve seat in the control chamber, so that the fluid conduit is closed. An armature plate, which is disposed in a damping chamber and has a pressure piece that cooperates with the valve element, and an armature coil. The armature, formed by the pressure piece and the armature plate is prevented from bouncing in response to a closing motion. For that purpose, an overflow conduit is provided between the control chamber and the damping chamber.

Abstract: A solenoid valve includes an electromagnetic drive unit for generating a magnetomotive force when being fed with electric power. There are a controlled-fluid passage and an accommodation chamber containing the electromagnetic drive unit. A partition wall defines a part of the controlled-fluid passage. A valve opening extends through the partition wall. A shaft extending through the valve opening is driven by the electromagnetic drive unit. A valve member fixed to the shaft moves into and out of contact with the partition wall to block and unblock the valve opening in accordance with movement of the shaft. A thin-film sealing member made of rubber-based resilient material operates for airtightly separating the controlled-fluid passage and the accommodation chamber from each other. A communication passage connects the accommodation chamber and an exterior. An orifice provides a smaller effective cross-sectional area of the communication passage.

Abstract: The tap intended for controlling the flow of a fluid, for example of a gas, comprises a tap body (34), an inner member (36) for opening and closing the passage of the gases, an outer rotary operating handwheel (42), a connection means (40) connecting the operating handwheel (42) to the closing member (36) and means limiting the movement of the operating handwheel (42) and of the opening and closing member (36) in the opening direction of the tap. In order to avoid the tap becoming jammed in the open position, said means limiting the movement of the operating member consist of an abutment (44) and a counterabutment (46) with frontal contact, which are arranged respectively on a rotary element and on the body (34) of the tap, or vice versa.

Abstract: A flap valve for liquid containers and liquid conduits has a valve housing having a cylindrical through bore extending in a longitudinal direction of the valve housing. A circular flap is positioned in the through bore and arranged in the valve housing rotatably about an axis extending perpendicularly to the longitudinal direction. A grip is located external to the housing and connected to the circular flap, wherein the grip is configured to turn the circular flap for opening and closing the through bore depending on a position of the circular flap. The throughbore has a seat having a spherical geometry for receiving the circular flap in a closed position of the circular flap.

Abstract: The present invention provides a Mn—Zn ferrite having an electrical resistivity exceeding 1 &OHgr;m order and having a high initial permeability of 4000 or more at 100 kHz and 100 or more at 10 MHz. The main components of the Mn—Zn ferrite include 44.0 to 49.8 mol % Fe2O3, 15.0 to 26.5 mol % ZnO, 0.1 to 3.0 mol % CoO, 0.02 to 1.00 mol % Mn2O3, and the remainder MnO. The Mn—Zn ferrite can be used in a wide frequency region of 100 kHz to 10 MHz by limiting Fe2O3 content to a range of less than 50 mol %, that is the stoichiometric composition, inhibiting formation of Mn2O3 and adding a proper amount of CoO.

Abstract: A refrigerant composition comprising difluoromethane (R-32), pentafluoroethane (R-125), 1,1,1,2-tetrafluoroethane (R-134a), and n-pentane, preferably prepared by mixing n-pentane preliminarily in R-134a, and mixing into a refrigerant of R-32 and R-125, with the n-pentane contained in a range of 0.1 wt. % to 14 wt. % of the total weight, and a refrigerating apparatus employing the refrigerant composition composed of above. It is an object of the present invention to develop a nonflammable refrigerant composition capable of using refrigerating machine oil such as mineral oil and alkyl benzene which is used in refrigerating apparatus, none in risk of destroying the ozone layer, excellent in cooling performance, superior in lubricating performance, and outstanding in heat resistance.

Abstract: A method of preparing coprecipitated inorganic particles, including subjecting a first portion of an aqueous solution containing two or more metal ions to a coprecipitation reaction to form a liquid containing nucleus particles; mixing the nucleus particles-containing liquid with a second portion of the aqueous solution to form a mixture; and subjecting the mixture to a coprecipitation reaction to produce coprecipitated inorganic particles. The coprecipitated inorganic particles are calcined to obtain calcined inorganic particles having an average particle diameter of 0.5-10 &mgr;m.

Abstract: A device for setting and automatic adjustment of the tractive forces of the cable of an overhead winch for a ski slope preparation and maintenance machine comprising an adjustment control unit connected to a controllable winch drive and a processing device connected to sensors and to the adjustment control unit is described.

Abstract: A fieldless CMOS image sensor that include a non-LOCOS isolation structure surrounding the photodiode diffusion region of each pixel. The isolation structure is formed by an anti-punchthrough (APT) implant isolation region formed in the substrate around the photodiode diffusion region, and spacer oxide that is formed using a special mask to cover the APT implant region. The APT implant isolation region is self-aligned with the special spacer oxide mask. A width of the isolation structure between two adjacent photodiodes is 0.5 &mgr;m or more. Similarly, LOCOS structures that are used, for example, in the image sensor active circuitry, are separated from the image-sensing (e.g., photodiode) region of each pixel by portions of the isolation structure having a width of 0.5 &mgr;m or more.

Abstract: Semiconductor devices and methods of sampling data therefrom are provided in which data is sampled from a memory cell array based on a relative position of a memory cell array section that contains the data. A sense amplifier generates an output signal in response to an address of one or more cells in a memory cell array. A control circuit generates a sample control signal in response to at least a portion of the address (e.g. one or more high order bits of the address) of the one or more cells in the memory cell array. A data sampling circuit then samples the output signal of the sense amplifier in response to the sample control signal. The portion of the memory cell array address used to drive the control circuit may logically divide the memory cell array into two or more sections. The control circuit may adjust the timing of the sample control signal in accordance with the proximity of a memory cell array section to the sense amplifier.

Abstract: An electron-emitting device includes an electron source layer made of a metal, a metal alloy or a semiconductor, an insulating layer formed on the electron source layer and a metal thin film electrode formed on the insulating layer. Electrons are emitted upon application of an electric field between the electron source layer and the metal thin film electrode. The insulating layer has at least one island region which constitutes an electron-emitting section in which the film thickness of the insulating layer is gradually reduced. The electron-emitting device further includes a carbon region made of carbon or a carbon compound on at least one of a top, bottom and inside of the island region.

Abstract: A high electron mobility transistor (HEMT) is disclosed that includes a semi-insulating silicon carbide substrate, an aluminum nitride buffer layer on the substrate, an insulating gallium nitride layer on the buffer layer, an active structure of aluminum gallium nitride on the gallium nitride layer, a passivation layer on the aluminum gallium nitride active structure, and respective source, drain and gate contacts to the aluminum gallium nitride active structure.

Abstract: A display device includes pixels disposed in a matrix on a transparent base plate. Each pixel includes an opening region, in which an electro-optic element for emitting light through the base plate is formed, and a non-opening region, in which a thin film transistor for driving the electro-optic element is formed. The non-opening region has a first film structure including the thin film transistor. The opening region has a second film structure extending from the first film structure and existing between the electro-optic element and the base plate. The second film structure is different from the first film structure so as to adjust the light passing through the opening region.

Abstract: An inexpensive display device, as well as an electrical apparatus employing the same, can be provided. In the display device in which a pixel section and a driver circuit are included on one and the same insulating surface, the driver circuit includes a decoder 100 and a buffer section 101. The decoder 100 includes a plurality of NAND circuits each including p-channel TFTs 104 to 106 connected to each other in parallel and other p-channel TFTs 107 to 109 connected to each other in series. The buffer section 101 includes a plurality of buffers each including three p-channel TFTs 114 to 116.

Abstract: A diamond interconnection substrate of the present invention includes a diamond substrate, and an implantation layer constituted by the presence of metal elements having a thickness of at least 10 nm and a concentration of at least 1020 cm−3 in the diamond substrate. The implantation layer is formed by ion implanting metal elements with a high energy level of at least 1 MeV and a high dose of at least 1016 cm−2. Thus, a technique is provided by which a multi-layer interconnection is realized in the diamond having the highest thermal conductivity of all materials.

Abstract: A semi-insulating bulk single crystal of silicon carbide is disclosed that has a resistivity of at least 5000 &OHgr;-cm at room temperature and a concentration of deep level trapping elements that is below the amounts that will affect the resistivity of the crystal, preferably below detectable levels. A method of forming the crystal is also disclosed, along with some resulting devices that take advantage of the microwave frequency capabilities of devices formed using substrates according to the invention.

Abstract: A method of fabricating a semiconductor light-emitting device in which the window structure can readily be obtained without relying upon an advanced process technology. In the method of the present invention, a first multi-layered film formed on a substrate is patterned into a groove pattern having a widened portion and narrowed portions provided on both sides of such widened portion. A second multi-layered film is then epitaxially grown on the substrate so as to cover the groove pattern, by successively growing an n-type second lower clad layer, a second active layer, a p-type second upper clad layer and a p-type cap layer. The cap layer is then patterned to thereby form a current injection layer on the second multi-layered film within the groove pattern so as to be extended along the longitudinal direction of such groove pattern.

Abstract: A package for optical components and a method for making the package are disclosed. The package comprises a quasi-planar substrate having a positioning floor, a platform and an optional ring frame of precisely determined height. Optical components picked and placed on a substrate floor, a raised platform and frame. A flexure assembly allows fine positioning of components requiring critical optical alignment.

Abstract: A TRIAC which is one species of chip-type semiconductors includes an element body made of silicon, electrodes provided on one face of the element body, a molybdenum plate provided on one of the electrodes by an alloy plate made of aluminum and silicon, a molybdenum plate provided on the other face of the element body by a similar alloy plate, and nickel layers provided on connection faces of the molybdenum plates to outer electrode plates, so that the electrode and molybdenum plate are firmly connected without conventional high-temperature solder which includes a great amount of lead, and that the alloy plate never melt even when newly developed low-temperature institute is employed, and that the operation of the molybdenum plates is sufficiently realized.

Abstract: A semiconductor device includes an electrically conductive III-V doped semiconductor substrate of a first conduction type, a photodiode array having photodiode structures disposed on the III-V doped semiconductor substrate, a first III-V doped semiconductor layer of a second conduction type disposed between the photodiode structures and the III-V doped semiconductor substrate, etching trenches disposed on the III-V doped semiconductor substrate, each of the trenches having inner sides, the inner sides having an insulation layer and a metallization layer for electrically connecting the photodiode structures in series, the metallization layer disposed on the insulation layer, and partition lines separating each of the photodiode structures from others of the photodiode structures for producing an individual photodiode structure when the array is cut through the first III-V doped semiconductor layer along the partition lines.

Abstract: A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown voltages to be achieved. In particular, the device will not break down at the bottom of the base-collector junction which is the weak spot for conventional devices. A process for manufacturing this device is described. A particular feature of this new process is that the N type epitaxial layer that is grown over the P+ layer is only about half the thickness of its counterpart in the conventional device. The process is fully compatible with conventional BiCMOS processes and has lower cost.

Abstract: Memory cell blocks respectively have a plurality of memory cell rows and a redundancy memory cell row for relieving a defect in these memory cell rows, memory cells being arranged in the memory cell rows. A first decoder selects any of the memory cell blocks. A second decoder selects any of the memory cell rows in the memory cell block. The operation of the second decoder not in use for decoding in the redundancy memory cell row is suspended when the redundancy memory cell row operates. The absence of unnecessary circuit operation allows a reduction in power consumption when the redundancy memory cell row operates. Even in a semiconductor integrated circuit having a plurality of memory banks each including the plurality of memory cell blocks, the first decoder, and the second decoder, it is possible to reduce power consumption when the redundancy memory cell rows operates.

Abstract: Disclosed is a solid state imaging device, comprising a unit pixel 101 including a photo diode 111 and a MOS transistor 112 for optical signal detection provided with a high-density buried layer 25 for storing optically generated charges generated by light irradiation in the photo diode 111, a vertical scanning signal driving scanning circuit 102 for outputting a scanning signal to a gate electrode 19, and a voltage boost scanning circuit 108 for outputting a boosted voltage higher than a power source voltage to a source region 16. In this case, a boosted voltage is applied from the voltage boost scanning circuit 108 to the source region 16, and the optically generated charges stored in the high-density buried layer 25 are swept out from the high-density buried layer 25 by a source voltage and a gate voltage risen by the boosted voltage.

Abstract: A photodiode for use in an imager having an improved charge leakage. The photodiode has a doped region that is spaced away from the field isolation to minimize charge leakage. A second embodiment of invention provides a second implant to improve charge leakage to the substrate. The photodiodes according to the invention provide improve charge leakage, improved reactions to dark current and an improved signal to noise ratio. Also disclosed are processes for forming the photodiode.

Abstract: A matching capacitor array is implemented on a single, monolithic integrated circuit. The array features a matrix of bottom electrodes and a plurality of continuous top electrode strips, where each continuous top electrode strip spans numerous bottom electrodes. The conductive contacts for each continuous top electrode strip are removed from the capacitor interface to the terminal ends of each of the continuous top electrode strips. The invention seeks to match or control parasitic and fringe capacitance, rather than to eliminate or minimize such capacitances. By creating a matched array, the parasitic and fringe capacitances of each matching capacitor unit cell are incorporated into the total capacitance of the unit cell.

Abstract: A method of forming a shallow outdiffused buried bitline in a vertical semiconductor memory device is disclosed which utilizes annealing and oxidation to drive-in and pile-up the dopant atom into an outdiffused region. The anneal/oxidation which is carried out at two different temperature ranges allows for fabricating buried bitlines having the lowest resistance as possible at a maximum dopant concentration, yet being formed near the surface interface of the vertical pillars. Semiconductor memory devices containing the outdiffused buried bitline regions are also disclosed.

Abstract: To provide a semiconductor device configuration in which a cell capacitor with an MIM or MIS structure is formed using a conductive material with a low resistivity such as Ru for the upper electrode and a resistance element is formed using a conductive material with high resistance such as polysilicon without causing any practical increase of fabrication process.

Abstract: The state of a ferroelectric transistor in a memory cell is read or stored, and the threshold voltage of further ferroelectric transistors in further memory cells in the memory matrix is increased during the reading or storing, or is increased permanently. A memory configuration including ferroelectric memory cells is also provided.

Abstract: A method is provided for forming buried source line in semiconductor devices. It is known in the art to form buried contacts on the surface of a semiconductor substrate. The present invention discloses a method of fabricating a semiconductor device, particularly a memory cell, having both the source region and the source line buried within the substrate. The source line is formed in a trench in the substrate over the source region. The trench walls are augmented with voltage anti-punch-through protection. The trench also provides the attendant advantages of extended sidewall area, smaller sheet resistance, and yet smaller cell area, therefore, smaller chip size, and faster access time as claimed in the embodiments of this invention. The buried source disclosed here is integrated with source line which is also buried within the substrate.

Abstract: The semiconductor device has a semiconductor body (1) having a field effect transistor (4) at a first surface (2) and a second gate (10) at a second surface (3). The second gate is present in a recess (11) in the semiconductor body (1) which is accurately aligned with a first gate (8) of the field effect transistor (4) on the first surface (2). The method of manufacturing the semiconductor device comprises the step of implanting ions into a semiconductor body (1) which has a first gate (8) on a first surface (2) and a silicon oxide layer (17) on a second surface (3). The implantation is done from the first surface (2) in a direction substantially perpendicular to that surface. The implantation has the effect that behind the first gate (8) an implanted region (18) is formed in the semiconductor body (1) and a circumferential implanted zone (19) in the silicon oxide layer (17). Silicon oxide is formed in the implanted region (18) by dopant-enhanced oxidation.

Abstract: The invention relates to a so-called punch-through diode comprising a stack of, for example, an n++, p−, p+, n++ region (1, 2, 3, 4). In the known diode, these regions (1, 2, 3, 4) are arranged on a substrate (11) in said order. The diode is provided with connection conductors (5, 6). Such a diode does not have a steep I-V characteristic and hence is less suitable as a TVSD (=Transient Voltage Suppression Device). Particularly at voltages below 5 volts, a punch-through diode could form an attractive alternative for use as a TVSD.

Abstract: A field effect transistor (FET) structure, and method for making the same, which further suppresses short-channel effects based on variations within the gate dielectric itself. The FET structure utilizes non-uniform gate dielectrics to alter the vertical electric field presented along the channel. The thickness and/or dielectric constant of the gate dielectric is varied along the length of the channel to present a vertical electric field which varies in a manner that tends to reduce the short-channel effects and gate capacitances.

Abstract: A method of fabricating a semiconductor device includes the steps of: forming a well of first conductivity type and well of second conductivity type in a substrate; forming a field oxide layer and gate oxide layer on the substrate; forming first and second polysilicon layers on the field oxide layer and gate oxide layer, the first polysilicon layer being doped with impurities of second conductivity type, the second polysilicon layer being doped with impurities of first conductivity, the first and second polysilicon layers coming into contact with each other; patterning the first and second polysilicon layers to be isolated from each other, to thereby forming first and second gates; and forming a conductive layer between the first and second gates. Accordingly, isolation of N-type and P-type polysilicon layers from each other, and patterning of them for the purpose of forming a gate are carried out using one mask, effectively simplifying the etching process during a gate patterning process.

Abstract: MOSFET comprising:

Abstract: A diode is provided which includes a first-conductivity-type cathode layer, a first-conductivity-type drift layer placed on the cathode region and having a lower concentration than the cathode layer, a generally ring-like second-conductivity-type ring region formed in the drift layer, second-conductivity-type anode region formed in the drift layer located inside the ring region, a cathode electrode formed in contact with the cathode layer, and an anode electrode formed in contact with the anode region, wherein the lowest resistivity of the second-conductivity-type anode region is at least {fraction (1/100)} of the resistivity of the drift layer, and the thickness of the anode region is smaller than the diffusion depth of the ring region.

Abstract: A semiconductor wafer 10 has a chip region 20 and a non-chip region 22. Dummy trench isolation regions 40 are formed in at least a part of the non-chip region 22 of the semiconductor wafer 10. The dummy trench isolation regions 40 are formed in a region extending by a specified distance D10 into the non-chip region 22 from a boundary between the chip region 20 and the non-chip region 22. A method is also provided for processing a semiconductor wafer 10 having a chip region 20 and a non-chip region 22. The method includes a process for forming trench isolation regions in the semiconductor wafer 10. The process includes the steps of forming dummy trench isolation regions 40 in at least a part of the non-chip region 22 of the semiconductor wafer 10, wherein the dummy trench isolation regions 40 are formed in a region extending by a specified distance D10 into the non-chip region 22 from a boundary between the chip region 20 and the non-chip region 22.

Abstract: Certain embodiments relate to an inductor that can be manufactured with the existing manufacturing facility, and greatly contributes to a further miniaturization of apparatuses. Embodiments include a semiconductor device having an inductor 100 and a CMOSFET 200 on a SOI. The inductor 100 is obtained by conducting a photolithography and an etching on a cobalt thin film formed on the LOCOS film 6.

Abstract: The present invention teaches fabrication of a high-resistance integrated circuit diffusion resistor that uses standard CMOS process steps. By appropriate masking during ion-implantation of source/drain diffusion regions, diffusion resistors created during NMOS source/drain implant may be counterdoped during PMOS source/drain implants and vice-versa. By appropriate choice of relative concentrations of a resistor dopant and counterdopant, and choice of diffusion depths, junction diodes can be formed which create a pinched resistor by constricting the current flow. The relative dopant concentrations can also be chosen to create regions of light effective doping within the diffusion resistor rather than creating junction diodes.

Abstract: A clipped thin-film resistor with an out-gassing preventing layer formed on a dielectric layer of a semiconductor substrate, and an isolated resistor layer interposed between the underlying out-gassing preventing layer and an overlying protective layer is provided to electrically connect with a semiconductor device fabricated on the semiconductor substrate. Two tungsten plugs, electrically connecting a metal wire with the isolated resistor layer, are positioned atop two respective ends of the resistor layer. Each tungsten plug first fills a self-aligned wet etched via formed within the protective layer atop two respective ends of the resistor layer and then etched back. The protective layer serves to protect the resistor layer from damage during the formation of the via.

Abstract: A substrate potential limiting device for an integrated circuit that includes a semiconductor substrate is provided. The device includes at least one unidirectional element connected between a substrate contact on the semiconductor substrate and a reference potential. The unidirectional element may be a bipolar transistor. The bipolar transistor includes a base and a collector connected to the at least one substrate contact and an emitter connected to the reference potential.

Abstract: A bipolar transistor according to the invention is provided with structure that an intrinsic base made of single crystal Si—Ge and a base leading-out electrode are connected via a link base made of polycrystal Si—Ge by doping at high concentration, further, a part immediately under the intrinsic base has the same conductive type as that of a collector and in a peripheral part, a single crystal Si—Ge layer having the same conductive type as that of a base is provided between the intrinsic base and a collector layer. Hereby, the reduction of the resistance of the link base between the intrinsic base and the base leading-out electrode and the reduction of capacitance between the collector and the base are simultaneously realized, and a self-aligned bipolar transistor wherein capacitance between an emitter and the base and capacitance between the collector and the base are respectively small, power consumption is small and high speed operation is enabled is acquired.

Abstract: Expansion promotion means (24) for more efficiently promoting the expansion of the depletion layer (19) than the electrically insulating film (14) having a suppressor electrode layer (20) buried therein is arranged between narrow portions (23b) of the suppressor electrode layer to control the expansion of the depletion layer (19), by which arrangement the spacing s between the narrow portions (23b) can be reduced without decreasing the field reducing effect of the field reduction means, which contains the suppressor electrode layer.

Abstract: A method and apparatus for endpointing a planarization process of a microelectronic substrate. In one embodiment, the microelectronic substrate can include a semiconductor base, a first material, such as an oxide, disposed on the base, a second material, such as a nitride, disposed on the first material to stiffen the first material, and an endpointing material, such as polysilicon, disposed on the second material. The endpointing material can have a hardness and/or a fracture resistance that is less than a hardness and/or a fracture resistance of the stiffening material and, in one embodiment, can have a coefficient of friction that is different than surrounding material of the microelectronic substrate so as to be detected when exposed to a planarizing medium.

Abstract: A first HSQ film composed of a Si—O-based film with a low dielectric constant is formed on a first wiring via a protective insulation film, and the surface of this first HSQ film is reformed to form a first SRO layer. Then, a second HSQ film is formed on this first SRO layer, and the surface of the second HSQ film is reformed to form a second SRO layer. Next, a via-hole is formed within a predetermined region, which reaches the protective insulation film on the first wiring. Then, wiring trenches forming a second wiring are formed within predetermined regions of the second HSQ film and the second SRO film while using the first SRO film as an etching stopper film. Thereafter, the protective insulation film at the bottom of the via-hole is etched and removed, and the wiring trenches and the via-hole are embedded with a conductive film. Then, the conductive film on the second SRO layer is removed while using the second SRO layer as a CMP stopper film.

Abstract: A push-up pin used for separating a semiconductor element attached by adhesive to an adhesive sheet of a semiconductor element pushing-up device in a die bonding apparatus from the adhesive sheet by pushing up the semiconductor element from the rear surface side of the adhesive sheet includes a tip end portion having a shape for applying pushing-up pressure with the thicknesses of the adhesive sheet and the adhesive kept constant when the pushing-up pressure for pushing up the semiconductor element from the rear surface side of the adhesive sheet is applied, and a base portion for supporting the tip end portion.

Abstract: A hybrid semiconductor package is formed from a die having two opposed elongate die edges with conductive bond pads arranged transversely relative to the rows of outer leads. A first portion of inner leads is off-die wire bonded to some of the bond pads, and a second portion of inner leads is insulatively attached as LOC leads between the bond pads along the opposed die edges. The hybrid package results in shorter inner leads of increased pitch enabling improved line yield at wire bond and encapsulation, as well as improved electrical performance, particularly for packages with very small dice.

Abstract: A method of manufacturing a solid-state image pickup device including the steps of preparing a package including a housing section to house a solid-state image pickup element chip and an opening section in an upper section thereof, sporadically applying adhesive with a predetermined thickness on a bottom surface of the housing section, moving the solid-state image pickup element toward the housing section, an upper surface of the package and an upper surface of the element each having desired parallelism with respect to a predetermined reference surface with high precision, bringing a rear surface of the solid-state image pickup element into contact with the adhesive and stopping the movement of the element before the element comes into contact with the bottom surface of the housing section, curing the adhesive while the solid-state image pickup element is floating on the adhesive and fixing the element in the housing section.

Abstract: A structure of a stackable semiconductor package, includes a stacked semiconductor package in which a plurality of semiconductor packages are stacked, each semiconductor package having a plurality of external leads at side surfaces thereof, and conductive wires for electrically connecting the corresponding external leads of said semiconductor packages of said stacked semiconductor package. The stacked structure of stackable semiconductor packages and the method of stacking the same improves the productivity by using an automatic wiring technique for electrically connecting the corresponding external leads. In addition, since the thickness of each wire which is used for lastly transmitting signals can be adjusted, the flexibility thereof increases and thereby the reliability can be improved in the solder joint.

Abstract: A method for packaging a semiconductor device includes connecting a plurality of wire leads to a corresponding plurality of electrical connection pads on the semiconductor device, covering at least a portion of the semiconductor device and at least a portion of each of the wire leads with an encapsulating material, and removing a portion of the encapsulating material and a portion of each of the wire leads to form a packaged semiconductor device wherein each of the wire leads has an exposed portion only at an end. The invention also includes a packaged semiconductor device having an integrated circuit device with a plurality of electrical connection pads, a plurality of wire leads coupled to the plurality of electrical connection pads, and a covering of encapsulating material covering at least a portion of the integrated circuit device and covering each of the wire leads, wherein each of the wire leads has an exposed end.