Including Change In A Growth-influencing Parameter (e.g., Composition, Temperature, Concentration, Flow Rate) During Growth (e.g., Multilayer Or Junction Or Superlattice Growing) Patents (Class 117/89)
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Publication number: 20140251203Abstract: A selective epitaxial growth method includes preparing a target object including a single crystal substrate in which an epitaxial growth region is partitioned by a suppression film; and growing the epitaxial layer on the epitaxial growth region of the target object until a predetermined film thickness is obtained. The growing the epitaxial layer includes first source gas supply process of supplying a source gas onto the target object under a first pressure to grow a first epitaxial layer on the epitaxial growth region, first removing process of removing deposits on the suppression film, second source gas supply process of supplying the source gas onto the target object under a second pressure higher than the first pressure, and second removing process of removing the deposits on the suppression film. The second source gas supply process and the second removing process are repeated until the predetermined film thickness is obtained.Type: ApplicationFiled: March 5, 2014Publication date: September 11, 2014Applicant: TOKYO ELECTRON LIMITEDInventors: Daisuke SUZUKI, Akinobu KAKIMOTO, Satoshi ONODERA
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Patent number: 8822263Abstract: It is provided a hetero epitaxial growth method, a hetero epitaxial crystal structure, a hetero epitaxial growth apparatus and a semiconductor device, the method includes forming a buffer layer formed with the orienting film of an oxide, or the orienting film of nitride on a heterogeneous substrate; and performing crystal growth of a zinc oxide based semiconductor layer on the buffer layer using a halogenated group II metal and an oxygen material. It is provided a homo epitaxial growth method, a homo epitaxial crystal structure, a homo epitaxial growth apparatus and a semiconductor device, the homo epitaxial growth method includes introducing reactant gas mixing zinc containing gas and oxygen containing gas on a zinc oxide substrate; and performing crystal growth of a zinc oxide based semiconductor layer on the zinc oxide substrate.Type: GrantFiled: June 29, 2009Date of Patent: September 2, 2014Assignees: National University Corporation Tokyo University of Agriculture and Technology, Rohm Co., Ltd., Tokyo Electron LimitedInventors: Akinori Koukitu, Yoshinao Kumagai, Tetsuo Fujii, Naoki Yoshii
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Patent number: 8821635Abstract: Si—Ge materials are grown on Si(100) with Ge-rich contents (Ge>50 at. %) and precise stoichiometries SiGe, SiGe2, SiGe3 and SiGe4. New hydrides with direct Si—Ge bonds derived from the family of compounds (H3Ge)xSiH4-x (x=1-4) are used to grow uniform, relaxed, and highly planar films with low defect densities at unprecedented low temperatures between about 300-450° C. At about 500-700° C., SiGex quantum dots are grown with narrow size distribution, defect-free microstructures and highly homogeneous elemental content at the atomic level. The method provides for precise control of morphology, composition, structure and strain. The grown materials possess the required characteristics for high frequency electronic and optical applications, and for templates and buffer layers for high mobility Si and Ge channel devices.Type: GrantFiled: April 8, 2005Date of Patent: September 2, 2014Assignee: Arizona Board of Regents on Behalf of Arizona State UniversityInventors: John Kouvetakis, Ignatius S. T. Tsong, Changwu Hu, John Tolle
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Publication number: 20140209013Abstract: A crystal growth method for nitride semiconductors, including the steps of growing a first semiconductor layer containing InxGa1-xN (0<x?1) on a substrate, with the use of a first carrier gas formed with an inert gas; growing a second semiconductor layer containing InyGa1-yN (0?y<1, y<x) on the first semiconductor layer, with the use of a second carrier gas containing the inert gas and H2 gas, an amount of the H2 gas being smaller than an amount of the inert gas; and growing a third semiconductor layer containing InzGa1-zN (0?z<1, z<x) on the second semiconductor layer, with the use of a third carrier gas containing the inert gas and H2 gas, an amount of the H2 gas in the third carrier gas being a smaller than the amount of H2 gas in the second carrier gas.Type: ApplicationFiled: April 3, 2014Publication date: July 31, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tomonari SHIODA, Toshiki Hikosaka, Yoshiyuki Harada, Koichi Tachibana, Shinya Nunoue
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Patent number: 8790463Abstract: Disclosed is a hot wall type substrate processing apparatus, including a processing chamber which is to accommodate at least one product substrate therein; a heating member which is disposed outside of the processing chamber and which is to heat the product substrate; a processing gas supply system connected to the processing chamber; and an exhaust system, wherein with a member from which a Si film is exposed being disposed such as to be opposed to a surface on which selective growth is to be effected of the product substrate, an epitaxial film including Si is allowed to selectively grow on a Si surface of the product substrate.Type: GrantFiled: March 11, 2005Date of Patent: July 29, 2014Assignee: Hitachi Kokusai Electric Inc.Inventors: Atsushi Moriya, Yasuhiro Inokuchi, Yasuo Kunii
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Patent number: 8790462Abstract: A nanoengineered structure comprising an array of more than about 1000 nanowhiskers on a substrate in a predetermined spatial configuration, for use for example as a photonic band gap array, wherein each nanowhisker is sited within a distance from a predetermined site not greater than about 20% of its distance from its nearest neighbour. To produce the array, an array of masses of a catalytic material are positioned on the surface, heat is applied and materials in gaseous form are introduced such as to create a catalytic seed particle from each mass, and to grow, from the catalytic seed particle, epitaxially, a nanowhisker of a predetermined material, and wherein each mass upon melting, retains approximately the same interface with the substrate surface such that forces causing the mass to migrate across said surface are less than a holding force across a wetted interface on the substrate surface.Type: GrantFiled: October 6, 2009Date of Patent: July 29, 2014Assignee: Qunano ABInventors: Lars Ivar Samuelson, Bjorn Jonas Ohlsson, Thomas M. I. Martensson
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Publication number: 20140174342Abstract: The present invention generally related to adding Indium precursors to deposition processes for thin films. Indium precursors are added in order to increase the growth rate per cycle of the deposition process. A plurality of deposition processes are disclosed herein which comprising a plurality of deposition cycles and providing an In-precursor pulse before at least one reactant pulse in at least one deposition cycle. The In-precursor can be added for increasing the average growth rate per cycle by at least 50% and in many examples above 500% compared to the growth rate of a similar deposition process without providing an In-precursor. Examples disclosed herein include the deposition of thin films comprising pnictides or chalcogenides, made by atomic layer deposition.Type: ApplicationFiled: December 20, 2012Publication date: June 26, 2014Applicant: ASM IP HOLDING B.V.Inventor: Viljami Pore
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Patent number: 8754448Abstract: A semiconductor device includes a semiconductor substrate and a plurality of transistors. The semiconductor substrate includes at least an iso region (namely an open region) and at least a dense region. The transistors are disposed in the iso region and the dense region respectively. Each transistor includes at least a source/drain region. The source/drain region includes a first epitaxial layer having a bottom thickness and a side thickness, and the bottom thickness is substantially larger than or equal to the side thickness.Type: GrantFiled: November 1, 2011Date of Patent: June 17, 2014Assignee: United Microelectronics Corp.Inventors: Chin-I Liao, Teng-Chun Hsuan, Chin-Cheng Chien
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Patent number: 8734584Abstract: In accordance with one aspect, the present invention provides a method for providing polycrystalline films having a controlled microstructure as well as a crystallographic texture. The methods provide elongated grains or single-crystal islands of a specified crystallographic orientation. In particular, a method of processing a film on a substrate includes generating a textured film having crystal grains oriented predominantly in one preferred crystallographic orientation; and then generating a microstructure using sequential lateral solidification crystallization that provides a location-controlled growth of the grains orientated in the preferred crystallographic orientation.Type: GrantFiled: August 20, 2009Date of Patent: May 27, 2014Assignee: The Trustees of Columbia University in the City of New YorkInventors: James S. Im, Paul C. van der Wilt
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Patent number: 8728236Abstract: Large area single crystal III-V nitride material having an area of at least 2 cm2, having a uniformly low dislocation density not exceeding 3×106 dislocations per cm2 of growth surface area, and including a plurality of distinct regions having elevated impurity concentration, wherein each distinct region has at least one dimension greater than 50 microns, is disclosed. Such material can be formed on a substrate by a process including (i) a first phase of growing the III-V nitride material on the substrate under pitted growth conditions, e.g., forming pits over at least 50% of the growth surface of the III-V nitride material, wherein the pit density on the growth surface is at least 102 pits/cm2 of the growth surface, and (ii) a second phase of growing the III-V nitride material under pit-filling conditions.Type: GrantFiled: January 17, 2011Date of Patent: May 20, 2014Assignee: Cree, Inc.Inventors: Xueping Xu, Robert P. Vaudo
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Patent number: 8728237Abstract: A method for growing nitride semiconductor crystals contains: growing a first semiconductor layer containing InxGa1-xN (0<x?1) on a substrate at a first growth temperature, using a first carrier gas containing an inert gas; growing a second semiconductor layer containing InyGa1-yN (0?y<1, y<x) on the first semiconductor layer at a second growth temperature higher than the first growth temperature, using a second carrier gas containing the inert gas and H2 gas, an amount of the H2 gas being smaller than an amount of the inert gas; and growing a third semiconductor layer containing InzGa1-zN (0?z<1, z<x) on the second semiconductor layer at the second growth temperature, using a third carrier gas containing the inert gas and H2 gas, an amount of the H2 gas in the third carrier gas being a smaller than the amount of H2 gas in the second carrier gas.Type: GrantFiled: September 2, 2010Date of Patent: May 20, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Tomonari Shioda, Toshiki Hikosaka, Yoshiyuki Harada, Koichi Tachibana, Shinya Nunoue
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Patent number: 8722526Abstract: Embodiments relate to growing an epitaxy gallium-nitride (GaN) layer on a porous silicon (Si) substrate. The porous Si substrate has a larger surface area compared to non-porous Si substrate to distribute and accommodate stress caused by materials deposited on the substrate. An interface adjustment layer (e.g., transition metal silicide layer) is formed on the porous silicon substrate to promote growth of a buffer layer. A buffer layer formed for GaN layer may then be formed on the silicon substrate. A seed-layer for epitaxial growth of GaN layer is then formed on the buffer layer.Type: GrantFiled: July 27, 2012Date of Patent: May 13, 2014Assignee: Veeco ALD Inc.Inventor: Sang In Lee
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Patent number: 8715413Abstract: The invention provides a method for manufacturing a Group III nitride semiconductor crystal. The method includes the steps of preparing a seed crystal and performing a convex surface-growing step to grow the group III nitride semiconductor crystal. The growth surface of the group III nitride semiconductor crystal is constituted only by a plurality of surfaces not vertical to a growth direction and the group III nitride semiconductor crystal grows while forming a convex shape as a whole by the growth surface constituted of the plurality of surfaces. The invention also provides a method for manufacturing a group III nitride semiconductor substrate.Type: GrantFiled: June 16, 2010Date of Patent: May 6, 2014Assignee: Hitachi Cable, Ltd.Inventor: Yuichi Oshima
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Publication number: 20140090688Abstract: A backside illuminated multi-junction solar cell module includes a substrate, multiple multi-junction solar cells, and a cell interconnection that provides a series connection, between at least two of the multi-junction solar cells. The substrate may include a material that is substantially transparent to solar radiation. Each multi-junction solar cell includes a first active cell, grown over the substrate, for absorbing a first portion of the solar radiation for conversion into electrical energy and a second active cell, grown over the first active cell, for absorbing a second portion of the solar radiation for conversion into electrical energy. At least one of the first and second active cells includes a nitride.Type: ApplicationFiled: December 4, 2013Publication date: April 3, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Jizhong Li
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Publication number: 20140070377Abstract: A method for fabricating a compound semiconductor epitaxial structure includes the following steps. Firstly, a first compound epitaxial layer is formed on a substrate. Then, a continuous epitaxial deposition process is performed to form a second compound epitaxial layer on the first compound epitaxial layer, so that the second compound epitaxial layer has a linearly-decreased concentration gradient of metal. Afterwards, a semiconductor material layer is formed on the second compound epitaxial layer.Type: ApplicationFiled: September 7, 2012Publication date: March 13, 2014Applicant: UNITED MICROELECTRONICS CORPORATIONInventors: Tien-Wei YU, Chin-Cheng CHIEN, I-Ming LAI, Shin-Chi CHEN, Chih-Yueh LI, Fong-Lung CHUANG, Chin-I LIAO, Kuan-Yu LIN
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Patent number: 8664094Abstract: The present invention relates to the growing of nitride semiconductors, applicable for a multitude of semiconductor devices such as diodes, LEDs and transistors. According to the method of the invention nitride semiconductor nanowires are grown utilizing a CVD based selective area growth technique. A nitrogen source and a metal-organic source are present during the nanowire growth step and at least the nitrogen source flow rate is continuous during the nanowire growth step. The V/III-ratio utilized in the inventive method is significantly lower than the V/III-ratios commonly associated with the growth of nitride based semiconductor.Type: GrantFiled: October 18, 2012Date of Patent: March 4, 2014Assignee: QuNano ABInventors: Werner Seifert, Damir Asoli, Zhaoxia Bi
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Patent number: 8663389Abstract: A method and apparatus for depositing III-V material is provided. The apparatus includes a reactor partially enclosed by a selectively permeable membrane 12. A means is provided for generating source vapors, such as a vapor-phase halide of a group III element (IUPAC group 13) within the reactor volume 10, and an additional means is also provided for introducing a vapor-phase hydride of a group V element (IUPAC group 15) into the volume 10. The reaction of the group III halide and the group V hydride on a temperature-controlled substrate 18 within the reactor volume 10 produces crystalline III-V material and hydrogen gas. The hydrogen is preferentially removed from the reactor through the selectively permeable membrane 12, thus avoiding pressure buildup and reaction imbalance. Other gases within the reactor are unable to pass through the selectively permeable membrane.Type: GrantFiled: May 21, 2011Date of Patent: March 4, 2014Inventor: Andrew Peter Clarke
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Patent number: 8658449Abstract: A method of manufacturing a semiconductor layer with which inactivation of impurity is able to be inhibited by a simple method, a semiconductor layer in which inactivation of impurity is inhibited, a method of manufacturing a laser diode with which inactivation of impurity is able to be inhibited by a simple method, and a laser diode including a semiconductor layer in which inactivation of impurity is inhibited are provided. In the method of manufacturing a semiconductor layer, after a semiconductor layer is formed by epitaxial growth with the use of AsH3, supply of AsH3 is stopped without separately supplying new gas when process temperature is 500 deg C. or more.Type: GrantFiled: March 31, 2010Date of Patent: February 25, 2014Assignee: Sony CorporationInventors: Naoki Jogan, Takahiro Arakida
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Patent number: 8659023Abstract: A monocrystalline layer having a first lattice constant on a monocrystalline substrate having a second lattice constant at least in a near-surface region, wherein the second lattice constant is different from the first lattice constant. Lattice matching atoms are implanted into the near-surface region. The near-surface region is momentarily melted. A layer is epitaxially deposited on the near-surface region that has solidified in monocrystalline fashion.Type: GrantFiled: September 11, 2012Date of Patent: February 25, 2014Assignee: Infineon Technologies Austria AGInventors: Franz Hirler, Hans-Joachim Schulze
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Patent number: 8658118Abstract: An object of the present invention is to provide more inexpensive high purity crystalline silicon which can satisfy not only a quality required to a raw material of silicon for a solar cell but also a part of a quality required to silicon for an up-to-date semiconductor and a production process for the same and provide high purity silicon tetrachloride used for production of high purity crystalline silicon and a production process for the same. The high purity crystalline silicon of the present invention has a boron content of 0.015 ppmw or less and a zinc content of 50 to 1000 ppbw. The production process for high purity crystalline silicon according to the present invention is characterized by that a silicon tetrachloride gas and a zinc gas are supplied to a vertical reactor to react them at 800 to 1200° C.Type: GrantFiled: September 4, 2009Date of Patent: February 25, 2014Assignees: JNC Corporation, JX Nippon Mining & Metals Corporation, Toho Titanium Co., ltd.Inventors: Satoshi Hayashida, Wataru Kato
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Patent number: 8652255Abstract: A method of: flowing a silicon source gas, a carbon source gas, and a carrier gas into a growth chamber under growth conditions to epitaxial grow silicon carbide on a wafer in the growth chamber; stopping or reducing the flow of the silicon source gas to interrupt the silicon carbide growth and maintaining the flow of the carrier gas while maintaining an elevated temperature in the growth chamber for a period of time; and resuming the flow of the silicon source gas to reinitiate silicon carbide growth. The wafer remains in the growth chamber throughout the method.Type: GrantFiled: October 9, 2008Date of Patent: February 18, 2014Assignee: The United States of America, as represented by the Secretary of the NavyInventors: Robert E Stahlbush, Brenda L VanMil, Kok-Keong Lew, Rachael L Myers-Ward, David Kurt Gaskill, Charles R. Eddy, Jr.
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Patent number: 8647435Abstract: HVPE reactors and methods for growth of p-type group III nitride materials including p-GaN. A reaction product such as gallium chloride is delivered to a growth zone inside of a HVPE reactor by a carrier gas such as Argon. The gallium chloride reacts with a reactive gas such as ammonia in the growth zone in the presence of a magnesium-containing gas to grow p-type group III nitride materials. The source of magnesium is an external, non-metallic compound source such as Cp2Mg.Type: GrantFiled: October 11, 2007Date of Patent: February 11, 2014Assignee: Ostendo Technologies, Inc.Inventors: Vladimir A. Dmitriev, Oleg V. Kovalenkov, Vladimir Ivantsov, Lisa Shapovalov, Alexander L. Syrkin, Anna Volkova, Vladimir Sizov, Alexander Usikov, Vitali A. Soukhoveev
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Publication number: 20140027777Abstract: Embodiments relate to growing an epitaxy gallium-nitride (GaN) layer on a porous silicon (Si) substrate. The porous Si substrate has a larger surface area compared to non-porous Si substrate to distribute and accommodate stress caused by materials deposited on the substrate. An interface adjustment layer (e.g., transition metal silicide layer) is formed on the porous silicon substrate to promote growth of a buffer layer. A buffer layer formed for GaN layer may then be formed on the silicon substrate. A seed-layer for epitaxial growth of GaN layer is then formed on the buffer layer.Type: ApplicationFiled: July 27, 2012Publication date: January 30, 2014Applicant: SYNOS TECHNOLOGY, INC.Inventor: Sang In LEE
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Patent number: 8636844Abstract: A method of forming a template on a silicon substrate includes epitaxially growing a template of single crystal ternary rare earth oxide on a silicon substrate and epitaxially growing a single crystal semiconductor active layer on the template. The active layer has either a cubic or a hexagonal crystal structure. During the epitaxial growth of the template, a partial pressure of oxygen is selected and a ratio of metals included in the ternary rare earth oxide is selected to match crystal spacing and structure of the template at a lower interface to the substrate and to match crystal spacing and structure of the template at an upper interface to crystal spacing and structure of the semiconductor active layer. A high oxygen partial pressure during growth of the template produces a stabilized cubic crystal structure and a low oxygen partial pressure produces a predominant peak with a hexagonal crystal structure.Type: GrantFiled: July 6, 2012Date of Patent: January 28, 2014Assignee: Translucent, Inc.Inventors: Rytis Dargis, Andrew Clark, Michael Lebby
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Patent number: 8617312Abstract: A method of forming (and system for forming) layers, such as calcium, barium, strontium, and/or magnesium, tantalates and/or niobates, and optionally titanates, on a substrate by employing a vapor deposition method, particularly a multi-cycle atomic layer deposition process.Type: GrantFiled: September 14, 2006Date of Patent: December 31, 2013Assignee: Micron Technology, Inc.Inventors: Brian A. Vaartstra, Stefan Uhlenbrock
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Patent number: 8608848Abstract: Shaped nanocrystal particles and methods for making shaped nanocrystal particles are disclosed. One embodiment includes a method for forming a branched, nanocrystal particle. It includes (a) forming a core having a first crystal structure in a solution, (b) forming a first arm extending from the core having a second crystal structure in the solution, and (c) forming a second arm extending from the core having the second crystal structure in the solution.Type: GrantFiled: October 6, 2011Date of Patent: December 17, 2013Assignee: The Regents of the University of CaliforniaInventors: A. Paul Alivisatos, Erik C. Scher, Liberato Manna
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Patent number: 8603243Abstract: A method of: supplying sources of carbon and silicon into a chemical vapor deposition chamber; collecting exhaust gases from the chamber; performing mass spectrometry on the exhaust gases; and correlating a partial pressure of a carbon species in the exhaust gases to a carbon:silicon ratio in the chamber.Type: GrantFiled: July 31, 2008Date of Patent: December 10, 2013Assignee: The United States of America, as represented by the Secretary of the NavyInventors: Brenda L VanMil, Kok-Keong Lew, Rachael L Myers-Ward, Charles R. Eddy, Jr., David Kurt Gaskill
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Patent number: 8597427Abstract: A semiconductor device is provided which is constituted by semiconductor devices including a thin film transistor with a GOLD structure, the GOLD structure thin film transistor being such that: a semiconductor layer, a gate insulating film, and a gate electrode are formed in lamination from the side closer to a substrate; the gate electrode is constituted of a first-layer gate electrode and a second-layer gate electrode shorter in the size than the first-layer gate electrode; the first-layer gate electrode corresponding to the region exposed from the second-layer gate electrode is formed into a tapered shape so as to be thinner toward the end portion; a first impurity region is formed in the semiconductor layer corresponding to the region with the tapered shape; and a second impurity region having the same conductivity as the first impurity region is formed in the semiconductor layer corresponding to the outside of the first-layer gate electrode, which is characterized in that a dry etching process consistingType: GrantFiled: August 29, 2008Date of Patent: December 3, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Satoru Okamoto
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Patent number: 8591651Abstract: A method of epitaxially growing a SiC layer on a single crystal SiC substrate is described. The method includes heating a single-crystal SiC substrate to a first temperature of at least 1400° C. in a chamber, introducing a carrier gas, a silicon containing gas and carbon containing gas into the chamber; and epitaxially growing a layer of SiC on a surface of the SiC substrate. The SiC substrate is heated to the first temperature at a rate of at least 30° C./minute. The surface of the SiC substrate is inclined at an angle of from 1° to 3° with respect to a basal plane of the substrate material.Type: GrantFiled: June 15, 2012Date of Patent: November 26, 2013Assignee: Power Integrations, Inc.Inventor: Jie Zhang
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Patent number: 8580034Abstract: A method of forming a semiconductor device includes providing a substrate in a vacuum processing tool, the substrate having a strained Ge-containing layer on the substrate and a Si layer on the strained Ge-containing layer, maintaining the substrate at a temperature less than 700° C., and generating a soft plasma in the vacuum processing tool. The Si layer is exposed to the soft plasma to form a Si-containing dielectric layer while minimizing oxidation and strain relaxation in the underlying strained Ge-containing layer. A semiconductor device containing a substrate, a strained Ge-containing layer on the substrate, and an Si-containing dielectric layer formed on the strained Ge-containing layer is provided. The semiconductor device can further contain a gate electrode layer on the Si-containing dielectric layer or a high-k layer on the Si-containing dielectric layer and a gate electrode layer on the high-k layer.Type: GrantFiled: March 31, 2006Date of Patent: November 12, 2013Assignee: Tokyo Electron LimitedInventor: Gert Leusink
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Patent number: 8568530Abstract: Precursors suitable for chemical vapor deposition, especially ALD, of hafnium oxide or zirconium oxide, have the general formula: (R1Cp)2MR2 wherein Cp represents a cyclopentadienyl ligand, R1 is H or a substituting alkyl group, alkoxy group or amido group of the Cp ligand, R2 is an alkyl group, an alkoxy group or an amido group and M is hafnium or zirconium.Type: GrantFiled: June 8, 2006Date of Patent: October 29, 2013Assignee: Sigma-Aldrich Co. LLCInventors: Peter Nicholas Heys, Paul Williams, Fuquan Song
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Patent number: 8562737Abstract: A crystal growth method, comprising the steps of: a) bringing a nitrogen material into a reaction vessel in which a mixed molten liquid comprising an alkaline metal and a group-III metal; and b) growing a crystal of a group-III nitride using the mixed molten liquid and the nitrogen material brought in by the step a) in the reaction vessel, wherein a provision is made such as to prevent a vapor of the alkaline metal from dispersing out of the reaction vessel.Type: GrantFiled: June 13, 2008Date of Patent: October 22, 2013Assignee: Ricoh Company, Ltd.Inventors: Seiji Sarayama, Masahiko Shimada, Hisanori Yamane, Masato Aoki
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Publication number: 20130269600Abstract: The method includes a step of growing an MgZnO-based single-crystal layer at a growth pressure of less than 10 kPa and a growth temperature equal to or greater than an upper limit temperature for ZnO single-crystal growth, wherein the MgZnO-based single-crystal layer is grown using a magnesium-based metal-organic compound having a Cp group, water vapor (H2O) and a zinc-based metal-organic compound that does not contain oxygen.Type: ApplicationFiled: March 22, 2013Publication date: October 17, 2013Inventors: Yuka SATO, Naochika HORIO
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Patent number: 8551246Abstract: A method for manufacturing a silicon single crystal wafer, having at least: a step of preparing a silicon single crystal ingot; a step of slicing the silicon single crystal ingot to fabricate a plurality of sliced substrates; a processing step of processing the plurality of sliced substrates into a plurality of substrates by performing at least one of lapping, etching, and polishing; a step of sampling at least one from the plurality of substrates; a step of measuring surface roughness of the substrate sampled at the sampling step by an AFM and obtaining an amplitude (an intensity) of a frequency band corresponding to a wavelength of 20 nm to 50 nm to make a judgment of acceptance; and a step of sending the substrate to the next step if a judgment result is acceptance or performing reprocessing if the judgment result is rejection.Type: GrantFiled: May 7, 2009Date of Patent: October 8, 2013Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Fumio Tahara, Tsuyoshi Ohtsuki, Takatoshi Nagoya, Kiyoshi Mitani
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Patent number: 8545626Abstract: A method for efficiently producing a plate-like nitride semiconductor crystal having the desired principal plane in a simple method is provided. A raw material gas is fed to a seed crystal in which a ratio (L/W) of length L in a longitudinal direction and maximum width W, of a plane of projection obtained by projecting a crystal growth face on the seed crystal in a growth direction is from 2 to 400, and the maximum width W is 5 mm or less, thereby growing a plate-like semiconductor crystal on the seed crystal.Type: GrantFiled: March 2, 2009Date of Patent: October 1, 2013Assignee: Mitsubishi Chemical CorporationInventors: Kenji Fujito, Shuichi Kubo, Yoko Mashige
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Publication number: 20130247816Abstract: A film-forming apparatus and method for the formation of silicon carbide comprising, a film-forming chamber to which a reaction gas is supplied, a temperature-measuring unit which measures a temperature within the chamber, a plurality of heating units arranged inside the chamber, an output control unit which independently controls outputs of the plurality of heating units, a substrate-transferring unit which transfers a substrate into, and out of the chamber, wherein the output control unit turns off or lowers at least one output of the plurality of heating units when the film forming process is completed, when the temperature measured by the temperature-measuring unit reaches a temperature at which the substrate-transferring unit is operable within the chamber, then at least one output of the plurality of heating units turned off or lowered, is turned on or raised, and the substrate is transferred out of the film-forming chamber by the substrate-transferring unit.Type: ApplicationFiled: March 15, 2013Publication date: September 26, 2013Applicants: Denso Corporation, NuFlare Technology, Inc.Inventors: Kunihiko SUZUKI, Yuusuke Sato, Hideki Ito, Hidekazu Tsuchida, Isaho Kamata, Masahiko Ito, Masami Naito
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Publication number: 20130233240Abstract: The present application relates to methods for depositing a smooth, germanium rich epitaxial film by introducing silylgermane as a source gas into a reactor at low temperatures. The epitaxial film can be strained and serve as an active layer, or relaxed and serve as a buffer layer. In addition to the silylgermane gas, a diluent is provided to modulate the percentage of germanium in a deposited germanium-containing film by varying the ratio of the silylgermane gas and the diluent. The ratios can be controlled by way of dilution levels in silylgermane storage containers and/or separate flow, and are selected to result in germanium concentration greater than 55 atomic % in deposited epitaxial silicon germanium films. The diluent can include a reducing gas such as hydrogen gas or an inert gas such as nitrogen gas. Reaction chambers are configured to introduce silylgermane and the diluent to deposit the silicon germanium epitaxial films.Type: ApplicationFiled: March 6, 2012Publication date: September 12, 2013Applicant: ASM AMERICA, INC.Inventors: Nyles W. Cody, Shawn G. Thomas
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Patent number: 8529699Abstract: A method includes the steps of, using water vapor and a metalorganic compound not containing oxygen, (a) performing crystal growth at a low growth temperature and at a low growth pressure in the range of 1 kPa to 30 kPa to form a low-temperature grown single-crystal layer; and (b) performing crystal growth at a high growth temperature and at a pressure higher than the low growth pressure to form a high-temperature grown single-crystal layer on the low-temperature grown single-crystal layer.Type: GrantFiled: September 16, 2009Date of Patent: September 10, 2013Assignee: Stanley Electric Co., Ltd.Inventors: Naochika Horio, Masayuki Makishima
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Patent number: 8529697Abstract: A process for growing a crystal of a nitride semiconductor in which after the step of mounting a substrate (12) in a reaction tube (11), the step of feeding a first material gas containing a Group 3 element onto the substrate in the reaction tube and the step of feeding a second material gas containing elemental nitrogen onto the substrate in the reaction tube are carried out alternately to deposit a nitride semiconductor crystal directly on the substrate. The number of moles of the elemental nitrogen contained in the second material gas has a ratio of 200 or more to the number of moles of the Group 3 element in the first material gas.Type: GrantFiled: August 31, 2005Date of Patent: September 10, 2013Assignees: Honda Motor Co., Ltd.Inventors: Hideki Hashimoto, Akihiko Horiuchi, Hideo Kawanishi
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Patent number: 8507950Abstract: A method of producing a semiconductor wafer includes placing a base wafer within a reaction chamber, and epitaxially growing a p-type Group 3-5 compound semiconductor on the base wafer by supplying, into the reaction chamber, a Group 3 source gas consisting of an organometallic compound of a Group 3 element, a Group 5 source gas consisting of a compound of a Group 5 element, and an impurity gas including an impurity that is to be incorporated as a dopant into a semiconductor to serve as a donor. Here, during the epitaxial growth of the p-type Group 3-5 compound semiconductor, the flow rate of the impurity gas and the flow rate ratio of the Group 5 source gas to the Group 3 source gas are set so that the product N×d (cm?2) of the residual carrier concentration N (cm?3) and the thickness d (cm) of the p-type Group 3-5 compound semiconductor may be 8.0×1011 or less.Type: GrantFiled: July 26, 2011Date of Patent: August 13, 2013Assignee: Sumitomo Chemical Company, LimitedInventors: Junya Hada, Tsuyoshi Nakano
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Patent number: 8501141Abstract: An object of the present invention is to effectively add Ge in the production of GaN through the Na flux method. In a crucible, a seed crystal substrate is placed such that one end of the substrate remains on the support base, whereby the seed crystal substrate remains tilted with respect to the bottom surface of the crucible, and gallium solid and germanium solid are placed in the space between the seed crystal substrate and the bottom surface of the crucible. Then, sodium solid is placed on the seed crystal substrate. Through employment of this arrangement, when a GaN crystal is grown on the seed crystal substrate through the Na flux method, germanium is dissolved in molten gallium before formation of a sodium-germanium alloy. Thus, the GaN crystal can be effectively doped with Ge.Type: GrantFiled: March 26, 2010Date of Patent: August 6, 2013Assignees: Toyoda Gosei Co., Ltd., NGK Insulators, Ltd., Osaka UniversityInventors: Takayuki Sato, Seiji Nagai, Makoto Iwai, Shuhei Higashihara, Yusuke Mori, Yasuo Kitaoka
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Patent number: 8470091Abstract: A direction of a dislocation line of a threading dislocation is aligned, and an angle between the direction of the dislocation line of the threading dislocation and a [0001]-orientation c-axis is equal to or smaller than 22.5 degrees. The threading dislocation having the dislocation line along with the [0001]-orientation c-axis is perpendicular to a direction of a dislocation line of a basal plane dislocation. Accordingly, the dislocation does not provide an extended dislocation on the c-face, so that a stacking fault is not generated. Thus, when an electric device is formed in a SiC single crystal substrate having the direction of the dislocation line of the threading dislocation, which is the [0001]-orientation c-axis, a SiC semiconductor device is obtained such that device characteristics are excellent without deterioration, and a manufacturing yield ration is improved.Type: GrantFiled: January 21, 2010Date of Patent: June 25, 2013Assignee: DENSO CORPORATIONInventors: Yasuo Kitou, Hiroki Watanabe, Masanori Nagaya, Kensaku Yamamoto, Eiichi Okuno
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Patent number: 8470090Abstract: Affords large-diametric-span AlN crystals, applicable to various types of semiconductor devices, with superior crystallinity, a method of growing the AlN crystals, and AlN crystal substrates. The AlN crystal growth method is a method in which an AlN crystal (4) is grown by vapor-phase epitaxy onto a seed crystal substrate (2) placed inside a crystal-growth compartment (24) within a crystal-growth vessel (12) provided within a reaction chamber, and is characterized in that during growth of the crystal, carbon-containing gas is supplied to the inside of the crystal-growth compartment (24).Type: GrantFiled: July 10, 2006Date of Patent: June 25, 2013Assignee: Sumitomo Electric Industries, Ltd.Inventors: Naho Mizuhara, Michimasa Miyanaga, Tomohiro Kawase, Shinsuke Fujiwara
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Patent number: 8449675Abstract: A semiconductor wafer is formed of a substrate wafer of single crystal silicon doped with dopant atoms of the n type or p type, with a front surface and a back surface, contains a layer deposited epitaxially on the front surface of the substrate wafer. The substrate wafer additionally includes an n++ or p++ doped layer, which extends from the front surface of the substrate wafer into the substrate wafer and has a defined thickness. The semiconductor wafer is produced by a process in which dopant atoms of the n type or p type are introduced into the substrate wafer through the front surface of the substrate wafer, the dopant concentration in a layer which extends from the front surface of the substrate wafer into the substrate wafer being increased from the level n+ or p+ to the level n++ or p++, and an epitaxial layer is then deposited on this layer.Type: GrantFiled: July 28, 2008Date of Patent: May 28, 2013Assignee: Siltronic AGInventors: Rupert Krautbauer, Gerhard Huettl, Andrej Lenz, Erwin-Peter Mayer, Rainer Winkler
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Patent number: 8430959Abstract: Disclosed are a method and an apparatus for preparing a polycrystalline silicon rod using a mixed core means, comprising: installing a first core means made of a resistive material together with a second core means made of silicon material in an inner space of a deposition reactor; electrically heating the first core means and pre-heating the second core by the first core means which is electrically heated; electrically heating the preheated second core means; and supplying a reaction gas into the inner space in a state where the first core means and the second core means are electrically heated for silicon deposition.Type: GrantFiled: May 11, 2007Date of Patent: April 30, 2013Assignee: Korea Research Institute of Chemical TechnologyInventors: Hee Young Kim, Kyung Koo Yoon, Yong Ki Park, Won Choon Choi, Won Wook So
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Patent number: 8409350Abstract: Affords gallium nitride crystal growth methods, gallium nitride crystal substrates, epi-wafers, and methods of manufacturing the epi-wafers, that make it possible to curb cracking that occurs during thickness reduction operations on the crystal, and to grow gallium nitride crystal having considerable thickness. A gallium nitride crystal growth method in one aspect of the present invention is a method of employing a carrier gas, a gallium nitride precursor, and a gas containing silicon as a dopant, and by hydride vapor phase epitaxy (HVPE) growing gallium nitride crystal onto an undersubstrate. The gallium nitride crystal growth method is characterized in that the carrier-gas dew point during the gallium nitride crystal growth is ?60° C. or less.Type: GrantFiled: July 25, 2008Date of Patent: April 2, 2013Assignee: Sumitomo Electric Industries, Ltd.Inventor: Shunsuke Fujita
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Patent number: 8394196Abstract: Methods for formation epitaxial layers containing silicon and carbon doped with phosphorus are disclosed. The pressure is maintained equal to or above 100 torr during deposition. The methods result in the formation of a film including substitutional carbon. Specific embodiments pertain to the formation and treatment of epitaxial layers in semiconductor devices, for example, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices.Type: GrantFiled: December 12, 2006Date of Patent: March 12, 2013Assignee: Applied Materials, Inc.Inventor: Yihwan Kim
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Patent number: 8394197Abstract: Enhanced corrosion resistance is achieved in a coating by using a germanium-containing precursor and hollow cathode techniques to form a first layer directly on the surface of a workpiece, prior to forming an outer layer, such as a layer of diamond-like carbon (DLC). The use of a germanium or germanium-carbide precursor reduces film stress and enables an increase in the thickness of the subsequently formed DLC. Germanium incorporation also reduces the porosity of the layer. In one embodiment, a cap layer containing germanium is added after the DLC in order to further reduce the susceptibility of the coating to chemical penetration from the top.Type: GrantFiled: July 11, 2008Date of Patent: March 12, 2013Assignee: Sub-One Technology, Inc.Inventors: Andrew W. Tudhope, Thomas B. Casserly, Karthik Boinapally, Deepak Upadhyaya, William J. Boardman
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Publication number: 20130049014Abstract: Provided is an epitaxial silicon carbide single-crystal substrate in which a silicon carbide epitaxial film having excellent in-plane uniformity of doping density is disposed on a silicon carbide single-crystal substrate having an off angle that is between 1° to 6°. The epitaxial film is grown by repeating a dope layer that is 0.5 ?m or less and a non-dope layer that is 0.1 ?m or less. The dope layer is formed with the ratio of the number of carbon atoms to the number of silicon atoms (C/Si ratio) in a material gas being 1.5 to 2.0, and the non-dope layer is formed with the C/Si ratio being 0.5 or more but less than 1.5. The resulting epitaxial silicon carbide single-crystal substrate comprises a high-quality silicon carbide epitaxial film, which has excellent in-plane uniformity of doping density, on a silicon carbide single-crystal substrate having a small off angle.Type: ApplicationFiled: May 10, 2011Publication date: February 28, 2013Applicant: NIPPON STEEL CORPORATIONInventors: Takashi Aigo, Hiroshi Tsuge, Taizo Hoshino, Tatsuo Fujimoto, Masakazu Katsuno, Masashi Nakabayashi, Hirokatsu Yashiro
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Patent number: 8377205Abstract: The present disclosure relates to an apparatus for producing silicon nanocrystals, which can minimize plasma diffusion by finely adjusting a plasma region created by an ICP coil. The apparatus includes a reactor having an ICP coil wound around an outer wall thereof and a tube inserted into the reactor, wherein a primary gas for forming silicon nanocrystals and a secondary gas for surface reaction of the silicon nanocrystals are separately supplied to the reactor through an inner side and an outer side of the tube, respectively.Type: GrantFiled: October 26, 2009Date of Patent: February 19, 2013Assignee: Korea Institute of Energy ResearchInventors: Bo-Yun Jang, Chang-Hyun Ko, Jeong-Chul Lee, Joon-Soo Kim, Joo-Seok Park