Abstract: Various embodiments may provide a termination element for a radio frequency (RF) power amplifier module. The termination element may include a resistive body having a first end, a second end, and first and second edges running from the first end to the second end opposite one another. The termination element may further include a first ground contact coupling the first end of the resistive body to a ground potential, and a second ground contact coupling the second end of the resistive body to the ground potential. The termination element may further include a conductive contact extending into the resistive body through the first edge, wherein an end of the conductive contact that is closest to the second edge is remotely disposed from the second edge by a gap.

Abstract: An apparatus including a printed circuit board including a body of a plurality of alternating layers of conductive material and insulating material; and a package including a die disposed within the body of the printed circuit board. A method including forming a printed circuit board including a core and a build-up section including alternating layers of conductive material and insulating material coupled to the core; and coupling a package including a die to the core of the printed circuit board such that at least a portion of a sidewall of the package is embedded in at least a portion of the build-up section. An apparatus including a printed circuit board including a body; a computing device including a package including a microprocessor disposed within the body of the printed circuit board; and a peripheral device that provides input or output to the computing device.

Abstract: A modular power device is used for mounting on a main plate. The modular power device includes a first substrate, a driving module and a converting module. The first substrate having a first axial direction and a second axial direction substantially perpendicular to the first axial direction is inserted into the main plate, such that the second axial direction is substantially perpendicular to the main plate. The driving module is located on one side of the first substrate and electrically connected thereon. The converting module is located on the other side of the first substrate and electrically connected to the driving module. A length of the converting module is substantially equal to that of the first substrate in the first axial direction, and a width of the converting module is smaller than a length of the first substrate in the first axial direction.

Abstract: A gold finger, includes a substrate, an embossable adhesive layer and a plurality of wires. The gold finger is achieved through adhering an embossable adhesive layer to a side of the substrate, providing grid-shaped grooves on a side of the embossable adhesive layer away from the substrate, embedding conductive grids of the wires in the grooves to form the wires. The gold finger is disposed on a sensing component, the wires of the gold finger are electrically connected with a circuit board through an anisotropic conductive adhesive. The contact area of the wire and the embossable adhesive layer is increased through embedding the conductive grid of the wire, which is grid-shaped structure, in the grooves such that the wires are tightly combined to the embossable adhesive layer and not easy to fall off or be scratched. The present invention further provides a touch screen containing the gold finger.

Abstract: An edge launch and fabrication method wherein spaced elongated slots are formed through a circuit board. The slots are plated at least along one side thereof connecting ground planes of the circuit board thus forming spaced edge plated regions. Circuit modules are produced by singulating the circuit board along a cut line offset outwardly from the plated slot sides to form an edge launch outwardly extending from and between the spaced edge plated regions.

Abstract: The disclosure relates to a stacked package and a method for manufacturing the same. The stacked package includes: a lower package including a substrate formed with ball lands in a periphery of an upper surface thereof, a semiconductor chip mounted over the upper surface, first solder balls formed over the ball lands and each having a side surface cut along an edge of the substrate and a polished upper surface, and a mold part for molding the upper surface including the semiconductor chip and the first solder balls, the cutted side surfaces and polished upper surfaces being exposed by the mold part; and an upper package stacked over the lower package and provided with second solder balls bonded to the first solder balls.

Abstract: A load control device for controlling the power delivered from a power source to an electrical load includes an antenna and a communication circuit to receive and transmit messages via radio frequency (RF) signals. The communication circuit is coupled to the power source but is capacitively coupled to the antenna. The capacitive coupling is formed through multiple layers of a printed circuit board (PCB) in which each layer includes a conductive trace that neighbors another conductive trace on an adjacent layer. The capacitive coupling provides that the antenna is electrically isolated from the communication circuit which accordingly, provides that the antenna is electrically isolated from the power source.

Abstract: A thermistor includes a metal substrate, a semiconductor ceramic layer on the metal substrate, and a pair of split electrodes on the semiconductor layer. The semiconductor ceramic layer is formed by a solid-phase method. The metal substrate includes ceramic particles and is not interrupted in the direction of thickness by the ceramic particles or a pillar defined by a chain of the ceramic particles. Preferably, the metal substrate and the ceramic layer of the thermistor have a thickness of about 10 ?m to about 80 ?m and about 1 ?m to about 10 ?m, respectively.

Abstract: A number of semiconductor chips each include a first main face and a second main face opposite to the first main face. A first encapsulation layer is applied over the second main faces of the semiconductor chips. An electrical wiring layer is applied over the first main faces of the first semiconductor chips. A second encapsulation layer is applied over the electrical wiring layer. The thickness of the first encapsulation layer and the thicknesses of the first semiconductor chips is reduced. The structure can be singulated to obtain a plurality of semiconductor devices.

Abstract: Disclosed herein is a mounting structure of a circuit board having a multi-layered ceramic capacitor thereon. The mounting structure of a circuit board having a multi-layered ceramic capacitor thereon, in which a dielectric layer on which inner electrodes are disposed is stacked and external electrode terminals connecting the inner electrodes in parallel are disposed on both ends thereof, wherein the inner electrodes of the multi-layered ceramic capacitor and the circuit board are disposed so as to be a horizontal direction to connect the external electrode terminals with a land on the circuit board by a conductive material and a ratio of a bonding area ASOLEDER of the conductive material to the area AMLCC of the external electrode terminals AMLCC is set to be less than 1.4, thereby remarkably reducing the vibration noise.

Abstract: In a semiconductor device including unit cells which are aligned in one direction, wirings disposed along end portions in the one direction have high Young's moduli.

Abstract: A module includes a circuit board, a resin layer, an external connection conductor, a solder bump. The resin layer is disposed on a first principal surface of the circuit board. The external connection conductor is arranged in the resin layer, has a first end connected to the circuit board and a second end protruding through the surface of the resin layer and includes a projection extending along the surface of the resin layer in a portion that protrudes through the surface of the resin layer. The solder bump is disposed on the second end of the external connection conductor.

Abstract: A printed circuit board has a first solder land, a second solder land, and a signal line pattern. The first solder land is configured to be soldered with an electronic part. The second solder land is configured to accumulate solder, the second solder land being disposed on a downstream side of the first solder land as viewed in a direction in which the printed circuit is carried. The signal line pattern includes an exposed part that is not covered with a resist, the exposed part being disposed between the solder land and the solder bridge prevention land.

Abstract: A structure comprises a first pad protruding over a top surface of a package substrate, wherein the first pad is of a first elongated shape, a second pad embedded in the package substrate, wherein the second pad is of a second elongated shape and a via coupled between the first pad and the second pad.

Abstract: In a layered structure having at least a substrate and a photosensitive resin layer or cured film layer formed on the substrate and containing an inorganic filler, the content of the inorganic filler in the photosensitive resin layer or cured film layer is low on the side contacting the substrate and high on the surface side away from the substrate, so that a linear thermal expansion coefficient of the photosensitive resin layer or cured film layer as a whole is maintained as low as possible. Preferably, the inorganic filler content in the layer gradually increases continuously obliquely or stepwise from the side contacting the substrate to the surface side away from the substrate. A photosensitive dry film containing the above-mentioned photosensitive resin layer is suitable for use as a solder resist or an interlayer resin insulation layer of a printed wiring board.

Abstract: This invention relates to a substrate with via and pad structure(s) to reduce solder wicking. Each via and pad structure connects a component to conductive layers associated with the substrate. The substrate includes one or more plated vias, solder mask(s) surrounding the plated vias, and a conductive pad with a conductive trace connected to each plated via. The conductive pad extends beyond the terminal sides to increase solder formation and the solder mask reduces solder formation at the terminal end of the component. The via and pad structure is suitable for a variety of components and high component density. The invention also provides a computer implemented method for calculating the maximum distance of a conductive pad extending beyond the terminal side of a component.

Abstract: A semiconductor package is provided, which includes: a first dielectric layer having opposite first and second surfaces and a cavity penetrating the first and second surfaces; a first circuit layer embedded in the first dielectric layer and exposed from the first surface of the first dielectric layer; at least an adhesive member formed in the cavity and adjacent to the first surface of the first dielectric layer; an electronic element disposed on the adhesive member; a second dielectric layer formed on the second surface of the first dielectric layer and in the cavity to encapsulate the adhesive member and the electronic element; a second circuit layer formed on the second dielectric layer; and a plurality of conductive vias formed in the second dielectric layer for electrically connecting the second circuit layer and the electronic element, thereby reducing the package size and cost and increasing the wiring space and flexibility.

Abstract: The present invention provides a wiring board wherein the resistance difference between multiple connection lines is reduced. The wiring board of the present invention comprises: a control region and a peripheral region. The control region includes multiple gate lines extending in a row direction and multiple source lines extending in a column direction. The peripheral region includes a gate driver connected with the gate lines; a source driver connected with the source lines; and multiple connection lines which extend around the control region and which connect the gate driver with the gate lines. Each of the connection lines includes a gate metal portion formed from a material of the gate lines and a source metal portion formed from a material of the source lines. An insulating layer is disposed between the gate metal portion and the source metal portion. The gate metal portion and the source metal portion are connected with each other via a contact portion which penetrates the insulating layer.

Abstract: A functional element including a substrate having a principal surface, a groove portion (a first groove portion, a second groove portion) disposed on the principal surface, and a fixed electrode section (a first fixed electrode finger, a second fixed electrode finger) laid across the groove portion on the substrate, wherein, in the groove portion, a raised portion formed by using at least one of the substrate and the fixed electrode section is provided in a position overlapping with the fixed electrode section in a plan view, the raised portion has a bonded surface (an end face), a wiring line (a first wiring line, a second wiring line) is disposed on the bonded surface, and the substrate and the fixed electrode section are connected with the wiring line sandwiched between the substrate and the fixed electrode section.

Abstract: A printed wiring board includes multiple conductive layers having conductive circuits, multiple resin insulation layers having openings and including the uppermost resin insulation layer positioned as the outermost layer of the resin insulation layers, multiple via conductors formed in the openings, respectively, and connecting the conductive circuits in the conductive layers, and multiple component-loading pads formed of a copper foil and positioned to load an electronic component. The resin insulation layers and the conductive layers are alternately laminated, and the component-loading pads are formed on the uppermost resin insulation layer.

Abstract: In manufacturing an LSI, or semiconductor integrated circuit device, the step of assembling device (such as resin sealing step) is normally followed by a voltage-application test in an environment of high temperature (e.g., from 85 to 130° C.) and high humidity (e.g., about 80% RH). It has been found that separation of a titanium nitride anti-reflection film from an upper film and generation of cracks in the titanium nitride film at an upper surface edge part of the aluminum-based bonding pad applied with a positive voltage in the test is caused by an electrochemical reaction due to moisture incoming through the sealing resin and the like to generate oxidation and bulging of the titanium nitride film. These problems are addressed by removing the titanium nitride film over the pad in a ring or slit shape at peripheral area of the aluminum-based bonding pad.

Abstract: A wiring board of the present invention includes an insulating board having a mounting portion on an upper surface to mount a semiconductor element, and semiconductor element connection pads formed on the mounting portion, on which at least three first dummy pads arranged on a center portion of the mounting portion, and at least three second dummy pads arranged on a peripheral portion of the mounting portion, are formed, and a dummy solder bump is formed on each of the first dummy pad and the second dummy pad.

Abstract: There is provided a wiring board capable of strengthening the bonding between an external terminal and a wiring of an external circuit board. A wiring board includes an insulating substrate having two main surfaces facing each other, side surfaces connecting to the two main surfaces and concave portions concave from the side surfaces and connecting to at least one of the two main surfaces; and external terminals disposed from one of the main surfaces to inner surfaces of the respective concave portions, each of the external terminals having a convex-shaped section disposed on one main surface side along each of the concave portions.

Abstract: A method of reducing the amount of mold flash created during the molding process of a molded integrated circuit package by extending a protrusion from the leadframe dambar into the mold flash area.

Abstract: A packaging substrate is disclosed, which includes: a dielectric layer; a circuit layer embedded in and exposed from a surface of the dielectric layer, wherein the circuit layer has a plurality of conductive pads; and a plurality of conductive bumps formed on the conductive pads and protruding above the surface of the dielectric layer. As such, when an electronic element is disposed on the conductive pads through a plurality of conductive elements, the conductive elements can come into contact with both top and side surfaces of the conductive bumps so as to increase the contact area between the conductive elements and the conductive pads, thereby strengthening the bonding between the conductive elements and the conductive pads and preventing delamination of the conductive elements from the conductive pads.

Abstract: A wiring board includes a first multilayer wiring board having first conductive layers and having a surface, a second multilayer wiring board having second conductive layers and positioned such that the second multilayer wiring board has a surface facing the surface of the first multilayer wiring board, and an adhesive layer including an adhesive sheet and interposed between the first multilayer wiring board and the second multilayer wiring board such that the adhesive layer is adhering the first multilayer wiring board and the second multilayer wiring board. The first multilayer wiring board has a first pad on the surface of the first multilayer wiring board, the second multilayer wiring board has a second pad on the surface of the second multilayer wiring board, and the first pad and the second pad are positioned such that the first pad and the second pad face each other across the adhesive layer.

Abstract: In some embodiments, an improved mechanical adhesion of copper metallization to dielectric with partially cured epoxy fillers is presented. In this regard, a substrate build-up film is introduced having epoxy material and a plurality of epoxy microspheres, wherein an interior of the microspheres is not fully cured. Other embodiments are also disclosed and claimed.

Abstract: A contact structure and assembly and a method for manufacturing the same for a microelectronics device includes first and second electrically conductive contacts being helically shaped. A carrier element is attached to and positioned between the first and second contacts. The first and second contacts are in electrical communication with each other, and the first and second contacts are in a mirror image relationship with each other. A pair of insulating substrates each include electrically conductive members. A contact point on each of the first and second contacts is attached and electrically communicating to respective electrically conductive members such that the first and second electrically conductive contacts between the pair of insulating substrates form an electrically conductive package. A metal layer on the carrier element provides electrical conductivity through a first opening defined by the carrier element between the first and second portions of the helix shaped contact.

Abstract: A semiconductor package is disclosed, which includes: a die paddle portion; a plurality of conductive portions circumventing the die paddle portion; a power bus bar and a ground bus bar formed around the periphery of the die paddle portion; a semiconductor element attached to the die paddle portion and electrically connected to the conductive portions, the power bus bar, and the ground bus bar by a plurality of bonding wires; and an encapsulant encapsulating the semiconductor element and the bonding wires. The ground bus bar extends outward along the power bus bar and is mutually configured with the power bus bar so as to reduce the loop inductance and resistance of the power bus bar while in use.

Abstract: Disclosed herein are a printed circuit board and a method for manufacturing the same. According to a preferred embodiment of the present invention, the printed circuit board includes: an insulating layer having a connection pad; and a resist layer formed on the insulating layer and provided with an opening so that the connection pad is exposed, wherein a wall surface of an opening of the resist layer may have at least one protrusion.

Abstract: A method of making an array of integral terminals on a circuit assembly. The method includes the steps of depositing at least a first liquid dielectric layer on the first surface of a first circuit member, imaged to include a plurality of first recesses corresponding to the array of integral terminals. The selected surfaces of the first recesses are processed to accept electro-less conductive plating deposition. Electro-lessly plating is applied to the selected surfaces of the first recesses to create a plurality of first conductive structures electrically coupled to, and extending generally perpendicular to, the first circuitry layer. Electro-plating is applied to the electro-less plating to substantially first recesses with a conductive material. The steps of depositing, processing, electro-less plating, and electro-plating are repeated to form the integral terminals of a desired shape. The dielectric layers are removed to expose the terminals.

Abstract: Electronic devices to output signals at different frequencies are mounted to a circuit board that has a group of layers, where the group of layers include reference plane layers and signal layers between the reference plane layers. A first signal layer has conductive traces having a first dimension to communicate the signals at a first frequency, and a second signal layer has conductive traces having a second, different dimension to communicate signals at a second, different frequency. The first and second signal layers are successive layers without any reference plane layer in between the first and second signal layers.

Abstract: Disclosed herein is a circuit board including: a core layer including a via hole; a metal film covering an inner wall of the via hole; a circuit pattern connected to the metal film on the core layer; and a plug surrounded by the metal film in the via hole and having a thickness thinner than a thickness of the core layer.

Abstract: A connecting member such as a terminal base is used in connection with a printed circuit board unit in which circuit elements such as a power module are mounted on a printed circuit board. The connecting member connects the circuit element of an electrical circuit including the printed circuit board, to an electrical wire. The connecting member includes a terminal connecting section to be directly connected to terminal pins of the circuit element; a wire connecting section to be connected to the electrical wire; and attachment sections for attaching the connecting member to the printed circuit board.

Abstract: A circuit board comprising a circuit carrier, a cover layer composed of a nonconductive material, comprising an organic substance, arranged on the circuit carrier, a first metallization layer at least partly arranged on the cover layer, wherein the first metallization layer has a flexible region.

Abstract: Provided is a circuit board having a tie bar buried therein. The circuit board includes a dielectric stack, at least a first tie bar, at least a first gold finger and at least a first microvia. The dielectric stack includes a first dielectric layer and a second dielectric layer. The first dielectric layer is located on the second dielectric layer. The dielectric stack includes a wireline region and a gold finger region. The first tie bar is buried in the gold finger region between the first dielectric layer and the second dielectric layer. The at least a first gold finger is located in the gold finger region on the first dielectric layer. The first microvia is located in the gold finger region in the first dielectric layer, and electrically connects the first gold finger to the first tie bar.

Abstract: A wiring seat includes an insulative base and a connecting member. The insulative base has a fixing hole and an engagement hole or a through hole beside the fixing hole. The connecting member has a conductive body. The conductive body is bendingly extended with a positioning sheet engaging with the engagement hole or a terminal pin passing the through hole. The conductive body has a passing hole corresponding to the fixing hole.

Abstract: A double-shot injection molding formed LED lead frame structure includes an inner base having an inner bottom portion and an inner surrounding wall surrounding on top of the inner bottom portion, the inner surrounding wall forming a central hollow portion on top of the inner bottom portion, and the inner bottom portion having an inner surface facing toward the central hollow portion; a plurality of conductive pins with each one thereof constructed by a soldering section, a securement section and an extension section respectively; and an outer base comprising an outer bottom portion attached to a bottom of the inner bottom portion and an outer surrounding wall surrounding on top of the outer bottom portion and enclosing an outer of the inner surrounding wall; wherein each one of the securement sections of the conductive pins extends to arch between the inner bottom portion and the inner surrounding wall.

Abstract: A multilayered printed circuit board or a substrate for mounting a semiconductor device includes a semiconductor device, a first resin insulating layer accommodating the semiconductor device, a second resin insulating layer provided on the first resin insulating layer, a conductor circuit provided on the second resin insulating layer, and via holes for electrically connecting the semiconductor device to the conductor circuit, wherein the semiconductor device is accommodated in a recess provided in the first resin insulating layer, and a metal layer for placing the semiconductor device is provided on the bottom face of the recess. A multilayered printed circuit board in which the installed semiconductor device establishes electrical connection through the via holes is provided.

Abstract: An apparatus capable of selectively applying different types of connectors to a substrate is disclosed. The memory apparatus includes a substrate having a controller. First and second connector pads may be arranged on edges of top and bottom surfaces of the substrate. A via hole may be arranged between the controller and the first and second connector pads. A first passive device pad may be arranged between the via hole and the first connector pads. A second passive device pad may be arranged between the via hole and the second connector pads. A passive device may be coupled to only one of the first passive device pad or the second passive device pad.

Abstract: A printed wiring board including a rigid multilayer board, a first substrate having multiple conductors, and a second substrate having multiple conductors electrically connected to the conductors of the first substrate. The conductors of the second substrate have an existing density which is set higher than an existing density of the conductors of the first substrate, and the first substrate and/or the second substrate is embedded in the rigid multilayer board.

Abstract: Read wiring traces and write wiring traces are formed on an insulating layer that is formed on a support substrate. Connection terminals that are electrically connectable to external circuits are formed at parts of the read wiring traces and write wiring traces on the insulating layer, respectively. Openings are formed in the support substrate so as to partially or entirely surround overlap regions that overlap with the connection terminals and have the same plane shape as the connection terminals. Parts of the insulating layer are exposed in the openings.

Abstract: In one embodiment, a ball grid array (BGA) of a packaged semiconductor device and a corresponding landing pad array of a printed circuit board each have a layout defined by an interconnection array having (i) an inner sub-array of locations having connectors arranged in rows and columns separated by a specified pitch and (ii) an outer rectangular ring of locations having connectors arranged in rows and columns separated by the specified pitch. The outer rectangular ring is separated from the inner sub-array by a depopulated rectangular ring having a width of at least twice the specified pitch, wherein the depopulated rectangular ring has no connectors. The outer rectangular ring has empty locations having no connectors. Some of those empty locations define depopulated sets that divide the outer rectangular ring into a number of different contiguous sets of locations having connectors that enable pin escape for connectors of the device's BGA.

Abstract: A semiconductor package includes a chip, a sealing body covering the chip, and a plurality of external connection terminals connected to the chip. The external connection terminals expose from a surface of the sealing body and are arranged in a grid on the surface of the sealing body. In the grid on the surface of the sealing body, each external connection terminal is adjacent to an area vacant of an other external connection terminal in at least one direction of eight directions from each external connection terminal, the eight directions including first linear directions along a row of the grid, second linear directions along a row of the grid perpendicular to the first linear directions, and four diagonal directions defined between the first linear directions and the second linear directions.

Abstract: Provided are a printed circuit board which can be used as a substrate for a package, a method of manufacturing the printed circuit board, and a semiconductor package using the printed circuit board, the printed circuit board including: a first substrate having a first mounting area for mounting a package substrate and a second mounting area for mounting a semiconductor element; a single layer or multi-layered circuit pattern of the first substrate; and a post bump connected to the circuit pattern, provided on an external insulating layer of the first mounting area, and having a concave upper surface.

Abstract: A touch panel includes a touch sensor layer including a first transparent electrode and a second transparent electrode, wherein an arrangement direction of the first transparent electrode can be perpendicular to that of the second transparent electrode, and both of the first and second transparent electrodes include two transparent metallic patterns which are stacked and electrically connected to each other.

Abstract: An electric-element mount seat adapted to receive at least one electric element is disclosed. The electric-element mount seat includes a seat body that has a base wall and two opposite side walls extending from the base wall, and a plurality of pins that are separately disposed on the side walls of the seat body in a plug-in manner. Each of the pins includes a wire-wrapped section adapted to be electrically connected to the electric element. The wire-wrapped section has a rod portion that protrudes from the bottom surface of a corresponding one of the side walls in a top-down direction and a hook portion that extends from the rod portion and that is bent toward the rod portion.

Abstract: A printed circuit board includes: a substrate; a land that is disposed on a surface of the substrate, and includes a central portion and a plurality of extended portions, the central portion having the same shape and the same size as a land of a surface mount device, and the extended portions being up-and-down symmetry and right-and-left symmetry with respect to a straight line which passes through the center of the central portion; gaps that are disposed on the surface of the substrate, each of the gaps being disposed on a periphery of the central portion and between the extended portions; and a resist that is disposed on the surface of the substrate, and has an opening portion formed at a position corresponding to the central portion and the gaps.

Abstract: An optronic porthole comprises a substrate with two faces. It comprises on one of the faces of the substrate or on both faces, a stack of several hetero-structures, each hetero-structure being composed of at least two semi-conducting layers SC1, SC2, the layer SC1 being doped, the layer SC2 itself comprising a two-dimensional electron gas layer formed at the interface with the layer SC1. It furthermore comprises an electrode in contact with all the electron gas layers, a bi-periodic metallic grid buried in the stack, in contact with the electrode. The substrate and the layers are transparent in the 0.4 ?m-5 ?m band.

Abstract: An electronic board includes conducting traces having an upper surface at least partially sunken with respect to a gluing surface of the board. A surface mount technology electronic device for mounting to the board includes insulating windows that define gluing sites within one or more pins. An electronic system is formed by one or more of such surface mount technology electronic devices mounted to electronic board. The devices are attached using a wave soldering technique that flows through channels formed by the sunken conductive traces.